From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by ml01.01.org (Postfix) with ESMTP id D41281A1E6A for ; Fri, 29 Jul 2016 11:15:49 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 29 Jul 2016 11:15:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,440,1464678000"; d="scan'208";a="1016339242" Received: from jfan12-desk.ccr.corp.intel.com ([10.239.9.5]) by fmsmga001.fm.intel.com with ESMTP; 29 Jul 2016 11:15:48 -0700 From: Jeff Fan To: edk2-devel@ml01.01.org Cc: Michael Kinney , Feng Tian , Giri P Mudusuru , Laszlo Ersek Date: Sat, 30 Jul 2016 02:14:51 +0800 Message-Id: <1469816112-8200-26-git-send-email-jeff.fan@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1469816112-8200-1-git-send-email-jeff.fan@intel.com> References: <1469816112-8200-1-git-send-email-jeff.fan@intel.com> Subject: [Patch v4 25/46] UefiCpuPkg/MpInitLib: Sort processor by ascending order of APIC ID X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jul 2016 18:15:50 -0000 Cc: Michael Kinney Cc: Feng Tian Cc: Giri P Mudusuru Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 72 ++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index c8d361f..539fbbc 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -222,6 +222,73 @@ GetApLoopMode ( } /** + Sort the APIC ID of all processors. + + This function sorts the APIC ID of all processors so that processor number is + assigned in the ascending order of APIC ID which eases MP debugging. + + @param[in] CpuMpData Pointer to PEI CPU MP Data +**/ +VOID +SortApicId ( + IN CPU_MP_DATA *CpuMpData + ) +{ + UINTN Index1; + UINTN Index2; + UINTN Index3; + UINT32 ApicId; + CPU_AP_DATA CpuData; + UINT32 ApCount; + CPU_INFO_IN_HOB *CpuInfoInHob; + + ApCount = CpuMpData->CpuCount - 1; + + if (ApCount != 0) { + for (Index1 = 0; Index1 < ApCount; Index1++) { + Index3 = Index1; + // + // Sort key is the hardware default APIC ID + // + ApicId = CpuMpData->CpuData[Index1].ApicId; + for (Index2 = Index1 + 1; Index2 <= ApCount; Index2++) { + if (ApicId > CpuMpData->CpuData[Index2].ApicId) { + Index3 = Index2; + ApicId = CpuMpData->CpuData[Index2].ApicId; + } + } + if (Index3 != Index1) { + CopyMem (&CpuData, &CpuMpData->CpuData[Index3], sizeof (CPU_AP_DATA)); + CopyMem ( + &CpuMpData->CpuData[Index3], + &CpuMpData->CpuData[Index1], + sizeof (CPU_AP_DATA) + ); + CopyMem (&CpuMpData->CpuData[Index1], &CpuData, sizeof (CPU_AP_DATA)); + } + } + + // + // Get the processor number for the BSP + // + ApicId = GetInitialApicId (); + for (Index1 = 0; Index1 < CpuMpData->CpuCount; Index1++) { + if (CpuMpData->CpuData[Index1].ApicId == ApicId) { + CpuMpData->BspNumber = (UINT32) Index1; + break; + } + } + + CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; + for (Index1 = 0; Index1 < CpuMpData->CpuCount; Index1++) { + CpuInfoInHob[Index1].InitialApicId = CpuMpData->CpuData[Index1].InitialApicId; + CpuInfoInHob[Index1].ApicId = CpuMpData->CpuData[Index1].ApicId; + CpuInfoInHob[Index1].Health = CpuMpData->CpuData[Index1].Health; + } + } +} + +/** Enable x2APIC mode on APs. @param[in, out] Buffer Pointer to private data buffer. @@ -336,6 +403,11 @@ CollectProcessorCount ( SetApicMode (LOCAL_APIC_MODE_X2APIC); } DEBUG ((DEBUG_INFO, "APIC MODE is %d\n", GetApicMode ())); + // + // Sort BSP/Aps by CPU APIC ID in ascending order + // + SortApicId (CpuMpData); + DEBUG ((DEBUG_INFO, "MpInitLib: Find %d processors in system.\n", CpuMpData->CpuCount)); return CpuMpData->CpuCount; -- 2.7.4.windows.1