From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x230.google.com (mail-wm0-x230.google.com [IPv6:2a00:1450:400c:c09::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C2B381A1DFC for ; Fri, 5 Aug 2016 07:54:06 -0700 (PDT) Received: by mail-wm0-x230.google.com with SMTP id p129so8384299wmp.0 for ; Fri, 05 Aug 2016 07:54:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KUv24LuRnuowCUQZNQiHKASgZbNn2uwcDRTPSq0cERk=; b=QwbvtIkawSJ4ZsM1rRNR/u45dofjMDdkTBWk1zpxnSsxEPS59Sj2YdJ6krcfxqh1cZ 3zT8Uv1s1uH30WaIHfmgSTmGQUTbmXVZ4RDAKLTHXXdcXof1e23ogHrgTfGIr1aZUO4w gHakjK0X7bXeqbElP31+7UNK1FI5cJPrZWolY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KUv24LuRnuowCUQZNQiHKASgZbNn2uwcDRTPSq0cERk=; b=mb7PI3LDl13efWZiUoEH8cK50pdxpm6ODQ9tx6SmuCyhuwEjonNoukk2T80V7tU10E G4Up9uEWqcCQ5MjGV+P2vXZY/L2mpgeC0qnsft5IhDmNsGn9jux7YQm8/yIFmNweKYiN F0QY0lw8L1gslLhON0Ot3c09VMm6L2WvZsGuDRWoHDBcOAD3yEVk69eCKJ1dPSu8VlV6 E9SYC8KUDJZKNMBY2mu8RiPSv9cLTkZBw+tL+KW2KMgJP5ymM1n0J3vh8wI1kDAOSr05 6jYN/Yq9IaYXnJLkf4aDcLfL1IlbzOIi9h97/ASQKy5rvIQocKoUXUG1sjwcMGeRjBpw fdyA== X-Gm-Message-State: AEkoouuMpxi4odb4n9zpYRlDF0Og8dsVP7g8L4sj3Eabq22tRAYT99buNZQ4fSTgQbYe49U9 X-Received: by 10.28.20.77 with SMTP id 74mr4125576wmu.1.1470408845166; Fri, 05 Aug 2016 07:54:05 -0700 (PDT) Received: from localhost.localdomain (3.red-81-34-118.dynamicip.rima-tde.net. [81.34.118.3]) by smtp.gmail.com with ESMTPSA id d64sm8956201wmc.22.2016.08.05.07.54.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 05 Aug 2016 07:54:04 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, lersek@redhat.com, Ard Biesheuvel Date: Fri, 5 Aug 2016 16:53:58 +0200 Message-Id: <1470408838-1020-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1470408838-1020-1-git-send-email-ard.biesheuvel@linaro.org> References: <1470408838-1020-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH 2/2] ArmPlatformPkg/PrePi: use correct callee saved regs X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Aug 2016 14:54:07 -0000 The AARCH64 version of the PrePi code 'preserves' values across a function call using registers that are not in fact callee saved. So fix that. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoint.S | 32 ++++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoint.S b/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoint.S index 9538c70a237c..e939d2c5aa5e 100644 --- a/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoint.S +++ b/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPoint.S @@ -36,7 +36,7 @@ ASM_PFX(_ModuleEntryPoint): // Get ID of this CPU in Multicore system bl ASM_PFX(ArmReadMpidr) // Keep a copy of the MpId register value - mov x10, x0 + mov x20, x0 _SetSVCMode: // Check if we can install the stack at the top of the System Memory or if we need @@ -88,55 +88,55 @@ _SetupStack: // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the // top of the memory space) - adds x11, x1, #1 + adds x21, x1, #1 b.cs _SetupOverflowStack _SetupAlignedStack: - mov x1, x11 + mov x1, x21 b _GetBaseUefiMemory _SetupOverflowStack: // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE // aligned (4KB) - LoadConstantToReg (EFI_PAGE_MASK, x11) - and x11, x11, x1 - sub x1, x1, x11 + LoadConstantToReg (EFI_PAGE_MASK, x21) + and x21, x21, x1 + sub x1, x1, x21 _GetBaseUefiMemory: // Calculate the Base of the UEFI Memory - sub x11, x1, x4 + sub x21, x1, x4 _GetStackBase: // r1 = The top of the Mpcore Stacks // Stack for the primary core = PrimaryCoreStack LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2) - sub x12, x1, x2 + sub x22, x1, x2 // Stack for the secondary core = Number of Cores - 1 LoadConstantToReg (FixedPcdGet32(PcdCoreCount), x0) sub x0, x0, #1 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x1) mul x1, x1, x0 - sub x12, x12, x1 + sub x22, x22, x1 - // x12 = The base of the MpCore Stacks (primary stack & secondary stacks) - mov x0, x12 - mov x1, x10 + // x22 = The base of the MpCore Stacks (primary stack & secondary stacks) + mov x0, x22 + mov x1, x20 //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize) LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), x2) LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), x3) bl ASM_PFX(ArmPlatformStackSet) // Is it the Primary Core ? - mov x0, x10 + mov x0, x20 bl ASM_PFX(ArmPlatformIsPrimaryCore) cmp x0, #1 bne _PrepareArguments _PrepareArguments: - mov x0, x10 - mov x1, x11 - mov x2, x12 + mov x0, x20 + mov x1, x21 + mov x2, x22 // Move sec startup address into a data register // Ensure we're jumping to FV version of the code (not boot remapped alias) -- 2.7.4