From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x235.google.com (mail-wm0-x235.google.com [IPv6:2a00:1450:400c:c09::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 072DC1A1E1B for ; Mon, 8 Aug 2016 03:40:42 -0700 (PDT) Received: by mail-wm0-x235.google.com with SMTP id o80so129559274wme.1 for ; Mon, 08 Aug 2016 03:40:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y6l2pkakUABG5sr0duVSyg0L0o27cp7Se33NKx4RzlI=; b=diqZ4SdS0ZlASfh0GaPUAN8ycw7mcz3uX9Bcuchyv3jbEzwAqiKx1sYyHdAo/wlIU7 TSE1QwBRSRaS/aC+HAt8rgp3jrj5/VdjSROplFJFosQJUnpc6iQ2RGQD0Gt6oCKd6TU7 9ISNNKIBhjt43g8cljNk6dhu+XnCuBTHRZkMo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y6l2pkakUABG5sr0duVSyg0L0o27cp7Se33NKx4RzlI=; b=RwAmT0EWsFbOaYtEfwhpvYp5pqx1YH0Yoi6uWS632UZgypyjj/IaeSb+aO5RW+1y+N 2rF1gsBvtl9vmWEr4GFxc8DLJ9D/zbuSre9DxXmO3WaZeizACdC87N6J7mFRT8tV7uO7 wKHJ/ubqIqFw3oFgD0FCBGuUA6NTUt5Fg7gst+UzCfjRUwdiBK1s+KtOHwTJENNzNC3x qYd9p+8TfNwWrnU+R0WCM0Td90xI5tx1mKn/RcU2s0yLGFGwPnrGpCb90ND6Nuo2mcVw K8Oa5g1oWMElc61YLj6NKfP9NVyGEpjUuFkKdu2A3KBljZ1I+Isml1FX6j6ub9L4FcFP dW8g== X-Gm-Message-State: AEkoouuDWquaII0ozQu9iDzUH75IyCjo5NtjcmKzlFvs1BOmbjMzUhRZzVjaSsZU9p09MDL3 X-Received: by 10.28.113.20 with SMTP id m20mr15663661wmc.82.1470652840605; Mon, 08 Aug 2016 03:40:40 -0700 (PDT) Received: from localhost.localdomain (222.red-88-1-55.dynamicip.rima-tde.net. [88.1.55.222]) by smtp.gmail.com with ESMTPSA id ub8sm32274344wjc.39.2016.08.08.03.40.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Aug 2016 03:40:39 -0700 (PDT) From: Ard Biesheuvel To: leif.lindholm@linaro.org, yonghong.zhu@intel.com, liming.gao@intel.com, edk2-devel@lists.01.org Cc: Ard Biesheuvel Date: Mon, 8 Aug 2016 12:40:26 +0200 Message-Id: <1470652827-22986-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1470652827-22986-1-git-send-email-ard.biesheuvel@linaro.org> References: <1470652827-22986-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH 1/2] BaseTools CLANG35: add missing XIP flags for AARCH64 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Aug 2016 10:40:42 -0000 When building for AARCH64, code that may execute with the MMU off should not perform unaligned accesses, which is why we set -mstrict-align for BASE, SEC, PEI_CORE and PEIM modules when building with GCCx. However, this setting is missing from CLANG35 so set it there as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- BaseTools/Conf/tools_def.template | 1 + 1 file changed, 1 insertion(+) diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template index 4f1dd4be378e..76ec62f4bb0d 100644 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -5422,6 +5422,7 @@ RELEASE_CLANG35_ARM_CC_FLAGS = DEF(CLANG35_ARM_CC_FLAGS) $(ARCHCC_FLAGS) $(P *_CLANG35_AARCH64_RC_FLAGS = DEF(GCC_AARCH64_RC_FLAGS) *_CLANG35_AARCH64_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANG35_AARCH64_TARGET) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) *_CLANG35_AARCH64_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANG35_AARCH64_TARGET) +*_CLANG35_AARCH64_CC_XIPFLAGS = DEF(GCC_AARCH64_CC_XIPFLAGS) DEBUG_CLANG35_AARCH64_CC_FLAGS = DEF(CLANG35_AARCH64_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -O0 RELEASE_CLANG35_AARCH64_CC_FLAGS = DEF(CLANG35_AARCH64_CC_FLAGS) $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) -Oz -- 2.7.4