From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x235.google.com (mail-wm0-x235.google.com [IPv6:2a00:1450:400c:c09::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 236F51A1DF8 for ; Wed, 10 Aug 2016 08:18:34 -0700 (PDT) Received: by mail-wm0-x235.google.com with SMTP id q128so100371238wma.1 for ; Wed, 10 Aug 2016 08:18:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3MZ2A94QbQaTeg4Dxn7Sa80XmRypQd4mLWhi+ggk0uM=; b=PHazdyp7rSw8Z7sikr38f6RzEfyAwX/kaKrpjBQ4i85jOapzSMOCj7wS8WkAgVUBni QGbldiimJX4VQ/WbpspY6S3AtEQMesHmkG9D+jMeJgOtMte8KgeOOCRwfOCxW/XBycQF 5TIF8CFr73dXZM2CHpgyxCjNsPNODF/i08ooE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3MZ2A94QbQaTeg4Dxn7Sa80XmRypQd4mLWhi+ggk0uM=; b=fqEllM/PC7h59G8nRmcOrh+G3MPyjShYeX7xbhJB2rJSfLCqKGm//PjNvQc237UKaZ gq0yTAgm/SphK+vFslXVAClI+LGLHItEOgl+16Xg1Vd3tANY107Ezey2BI461Nz+6ApF hJQQVgAArkouwLlSDrZfKta6PERYXYDYmwAzXiMeE7uXE7j38HkfSQDGU3Ioju4F0vKn MxpmH5NuQ3JEBz3TMJXjK/Ca0sqdlnKokZmZ58cnp36TuCG5bIaGia/kVfaP1HGKjG3V zbNwivGULHJ1JSwiG3Ters/B2vsZtbzQ94aY66WBuOaJW2THV2ZTqVtw3RF3Fq09yATv E5vg== X-Gm-Message-State: AEkoouvkGFc41fwFCDg1by7l04FkypDlkQDCw/IYenDUmqLxppw1U7PZBss7woauMFHbcgx4 X-Received: by 10.28.157.148 with SMTP id g142mr4193089wme.2.1470842312746; Wed, 10 Aug 2016 08:18:32 -0700 (PDT) Received: from localhost.localdomain (46.red-81-37-107.dynamicip.rima-tde.net. [81.37.107.46]) by smtp.gmail.com with ESMTPSA id c16sm8908374wme.4.2016.08.10.08.18.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 10 Aug 2016 08:18:32 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, eugene@hp.com Cc: lersek@redhat.com, Ard Biesheuvel Date: Wed, 10 Aug 2016 17:17:45 +0200 Message-Id: <1470842282-8415-10-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1470842282-8415-1-git-send-email-ard.biesheuvel@linaro.org> References: <1470842282-8415-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH 09/26] ArmPkg/ArmCpuLib: switch to ASM_FUNC() asm macro X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Aug 2016 15:18:34 -0000 Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/AArch64/ArmCortexA5xHelper.S | 9 ++------- ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S | 9 +-------- 2 files changed, 3 insertions(+), 15 deletions(-) diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/AArch64/ArmCortexA5xHelper.S b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/AArch64/ArmCortexA5xHelper.S index e5fbc86bc1c4..ba3d48f11f6d 100644 --- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/AArch64/ArmCortexA5xHelper.S +++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/AArch64/ArmCortexA5xHelper.S @@ -14,16 +14,11 @@ #include -.text -.align 3 -GCC_ASM_EXPORT (ArmReadCpuExCr) -GCC_ASM_EXPORT (ArmWriteCpuExCr) - -ASM_PFX(ArmReadCpuExCr): +ASM_FUNC(ArmReadCpuExCr) mrs x0, S3_1_c15_c2_1 ret -ASM_PFX(ArmWriteCpuExCr): +ASM_FUNC(ArmWriteCpuExCr) msr S3_1_c15_c2_1, x0 dsb sy isb diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S index 5db586192206..365d57d7e8bd 100644 --- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S +++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Helper.S @@ -12,17 +12,10 @@ // #include -#include -#include - -.text -.align 3 - -GCC_ASM_EXPORT(ArmGetScuBaseAddress) // IN None // OUT r0 = SCU Base Address -ASM_PFX(ArmGetScuBaseAddress): +ASM_FUNC(ArmGetScuBaseAddress) // Read Configuration Base Address Register. ArmCBar cannot be called to get // the Configuration BAR as a stack is not necessary setup. The SCU is at the // offset 0x0000 from the Private Memory Region. -- 2.7.4