From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22b.google.com (mail-wm0-x22b.google.com [IPv6:2a00:1450:400c:c09::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4953C1A1E54 for ; Wed, 10 Aug 2016 08:18:36 -0700 (PDT) Received: by mail-wm0-x22b.google.com with SMTP id o80so111004206wme.1 for ; Wed, 10 Aug 2016 08:18:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tJXNqtuzsZfw6xvE4L9Y8Q2p1RlqKbZPD7E0+ewyT3A=; b=WIPmeKkN6YplCyrGmW3iY1GG7yNGnz4B/Bv0xvl91v99qAfLJCUxbPhyFDvBqVGPJL /W43E5bmCEsfs3W7V7aGbSEJ0QNDsaLT31opZfBB5sfk9etvpjq88szvQEfV1WnjSC/Z wktNUKS6O/PQrM4re2NBaz3OBHNW6iWG2MtvQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tJXNqtuzsZfw6xvE4L9Y8Q2p1RlqKbZPD7E0+ewyT3A=; b=hX2JHxRWaL2XZvMBsrTteqqmwhwhovRvIWvznev9/Huie44LkMmNJ/WpAgoEAMTokL 4k6elAPaSZvRi9sxuGKZJa1q+HmByTDs2Fa+2sZIvwF/BKiY2nIqIyqjVv59tSX372EW MI08p0aNuZcCTgsYEQkYU+/RE4uVPBYJq+NNN5vUi3OOJ0NoBfFXRyRZf9ul33OEhuEE gmFsVuGFw4uruoq5vaS3nV86uiORhhH5v8zR8wDFbtQ0X8lMik2K/QA1Kpzn4nTyoQkq 3Nh+ELyyL9Og+gxOKuZwua3XyrzyUvKgTORDTlPzAJH1SgD4QsDm/yVEKb0Fcj9wz/sW ubLA== X-Gm-Message-State: AEkoout7DMGEW6JCKhjiAlRuYJs4c/ZCLFdwhRaojDXd5Kk4VRGtwHiwVYX444gp09yIGib8 X-Received: by 10.194.134.234 with SMTP id pn10mr4557071wjb.35.1470842314790; Wed, 10 Aug 2016 08:18:34 -0700 (PDT) Received: from localhost.localdomain (46.red-81-37-107.dynamicip.rima-tde.net. [81.37.107.46]) by smtp.gmail.com with ESMTPSA id c16sm8908374wme.4.2016.08.10.08.18.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 10 Aug 2016 08:18:34 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, eugene@hp.com Cc: lersek@redhat.com, Ard Biesheuvel Date: Wed, 10 Aug 2016 17:17:46 +0200 Message-Id: <1470842282-8415-11-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1470842282-8415-1-git-send-email-ard.biesheuvel@linaro.org> References: <1470842282-8415-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH 10/26] ArmPkg/ArmGicV3: switch to ASM_FUNC() asm macro X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Aug 2016 15:18:36 -0000 Annotate functions with ASM_FUNC() so that they are emitted into separate sections. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S | 28 ++++++-------------- ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S | 28 ++++++-------------- 2 files changed, 16 insertions(+), 40 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S b/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S index f1c227f2c421..a4e0a4170a03 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S +++ b/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S @@ -32,24 +32,12 @@ #endif -.text -.align 2 - -GCC_ASM_EXPORT(ArmGicV3GetControlSystemRegisterEnable) -GCC_ASM_EXPORT(ArmGicV3SetControlSystemRegisterEnable) -GCC_ASM_EXPORT(ArmGicV3EnableInterruptInterface) -GCC_ASM_EXPORT(ArmGicV3DisableInterruptInterface) -GCC_ASM_EXPORT(ArmGicV3EndOfInterrupt) -GCC_ASM_EXPORT(ArmGicV3AcknowledgeInterrupt) -GCC_ASM_EXPORT(ArmGicV3SetPriorityMask) -GCC_ASM_EXPORT(ArmGicV3SetBinaryPointer) - //UINT32 //EFIAPI //ArmGicV3GetControlSystemRegisterEnable ( // VOID // ); -ASM_PFX(ArmGicV3GetControlSystemRegisterEnable): +ASM_FUNC(ArmGicV3GetControlSystemRegisterEnable) EL1_OR_EL2_OR_EL3(x1) 1: mrs x0, ICC_SRE_EL1 b 4f @@ -63,7 +51,7 @@ ASM_PFX(ArmGicV3GetControlSystemRegisterEnable): //ArmGicV3SetControlSystemRegisterEnable ( // IN UINT32 ControlSystemRegisterEnable // ); -ASM_PFX(ArmGicV3SetControlSystemRegisterEnable): +ASM_FUNC(ArmGicV3SetControlSystemRegisterEnable) EL1_OR_EL2_OR_EL3(x1) 1: msr ICC_SRE_EL1, x0 b 4f @@ -77,7 +65,7 @@ ASM_PFX(ArmGicV3SetControlSystemRegisterEnable): //ArmGicV3EnableInterruptInterface ( // VOID // ); -ASM_PFX(ArmGicV3EnableInterruptInterface): +ASM_FUNC(ArmGicV3EnableInterruptInterface) mov x0, #1 msr ICC_IGRPEN1_EL1, x0 ret @@ -86,7 +74,7 @@ ASM_PFX(ArmGicV3EnableInterruptInterface): //ArmGicV3DisableInterruptInterface ( // VOID // ); -ASM_PFX(ArmGicV3DisableInterruptInterface): +ASM_FUNC(ArmGicV3DisableInterruptInterface) mov x0, #0 msr ICC_IGRPEN1_EL1, x0 ret @@ -95,7 +83,7 @@ ASM_PFX(ArmGicV3DisableInterruptInterface): //ArmGicV3EndOfInterrupt ( // IN UINTN InterruptId // ); -ASM_PFX(ArmGicV3EndOfInterrupt): +ASM_FUNC(ArmGicV3EndOfInterrupt) msr ICC_EOIR1_EL1, x0 ret @@ -103,7 +91,7 @@ ASM_PFX(ArmGicV3EndOfInterrupt): //ArmGicV3AcknowledgeInterrupt ( // VOID // ); -ASM_PFX(ArmGicV3AcknowledgeInterrupt): +ASM_FUNC(ArmGicV3AcknowledgeInterrupt) mrs x0, ICC_IAR1_EL1 ret @@ -111,7 +99,7 @@ ASM_PFX(ArmGicV3AcknowledgeInterrupt): //ArmGicV3SetPriorityMask ( // IN UINTN Priority // ); -ASM_PFX(ArmGicV3SetPriorityMask): +ASM_FUNC(ArmGicV3SetPriorityMask) msr ICC_PMR_EL1, x0 ret @@ -119,6 +107,6 @@ ASM_PFX(ArmGicV3SetPriorityMask): //ArmGicV3SetBinaryPointer ( // IN UINTN BinaryPoint // ); -ASM_PFX(ArmGicV3SetBinaryPointer): +ASM_FUNC(ArmGicV3SetBinaryPointer) msr ICC_BPR1_EL1, x0 ret diff --git a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S index af14b91b9cfb..a72f3c865163 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S +++ b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S @@ -16,24 +16,12 @@ // For the moment we assume this will run in SVC mode on ARMv7 -.text -.align 2 - -GCC_ASM_EXPORT(ArmGicV3GetControlSystemRegisterEnable) -GCC_ASM_EXPORT(ArmGicV3SetControlSystemRegisterEnable) -GCC_ASM_EXPORT(ArmGicV3EnableInterruptInterface) -GCC_ASM_EXPORT(ArmGicV3DisableInterruptInterface) -GCC_ASM_EXPORT(ArmGicV3EndOfInterrupt) -GCC_ASM_EXPORT(ArmGicV3AcknowledgeInterrupt) -GCC_ASM_EXPORT(ArmGicV3SetPriorityMask) -GCC_ASM_EXPORT(ArmGicV3SetBinaryPointer) - //UINT32 //EFIAPI //ArmGicGetControlSystemRegisterEnable ( // VOID // ); -ASM_PFX(ArmGicV3GetControlSystemRegisterEnable): +ASM_FUNC(ArmGicV3GetControlSystemRegisterEnable) mrc p15, 0, r0, c12, c12, 5 // ICC_SRE bx lr @@ -42,7 +30,7 @@ ASM_PFX(ArmGicV3GetControlSystemRegisterEnable): //ArmGicSetControlSystemRegisterEnable ( // IN UINT32 ControlSystemRegisterEnable // ); -ASM_PFX(ArmGicV3SetControlSystemRegisterEnable): +ASM_FUNC(ArmGicV3SetControlSystemRegisterEnable) mcr p15, 0, r0, c12, c12, 5 // ICC_SRE isb bx lr @@ -51,7 +39,7 @@ ASM_PFX(ArmGicV3SetControlSystemRegisterEnable): //ArmGicV3EnableInterruptInterface ( // VOID // ); -ASM_PFX(ArmGicV3EnableInterruptInterface): +ASM_FUNC(ArmGicV3EnableInterruptInterface) mov r0, #1 mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1 bx lr @@ -60,7 +48,7 @@ ASM_PFX(ArmGicV3EnableInterruptInterface): //ArmGicV3DisableInterruptInterface ( // VOID // ); -ASM_PFX(ArmGicV3DisableInterruptInterface): +ASM_FUNC(ArmGicV3DisableInterruptInterface) mov r0, #0 mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1 bx lr @@ -69,7 +57,7 @@ ASM_PFX(ArmGicV3DisableInterruptInterface): //ArmGicV3EndOfInterrupt ( // IN UINTN InterruptId // ); -ASM_PFX(ArmGicV3EndOfInterrupt): +ASM_FUNC(ArmGicV3EndOfInterrupt) mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1 bx lr @@ -77,7 +65,7 @@ ASM_PFX(ArmGicV3EndOfInterrupt): //ArmGicV3AcknowledgeInterrupt ( // VOID // ); -ASM_PFX(ArmGicV3AcknowledgeInterrupt): +ASM_FUNC(ArmGicV3AcknowledgeInterrupt) mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1 bx lr @@ -85,7 +73,7 @@ ASM_PFX(ArmGicV3AcknowledgeInterrupt): //ArmGicV3SetPriorityMask ( // IN UINTN Priority // ); -ASM_PFX(ArmGicV3SetPriorityMask): +ASM_FUNC(ArmGicV3SetPriorityMask) mcr p15, 0, r0, c4, c6, 0 //ICC_PMR bx lr @@ -93,6 +81,6 @@ ASM_PFX(ArmGicV3SetPriorityMask): //ArmGicV3SetBinaryPointer ( // IN UINTN BinaryPoint // ); -ASM_PFX(ArmGicV3SetBinaryPointer): +ASM_FUNC(ArmGicV3SetBinaryPointer) mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1 bx lr -- 2.7.4