* [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe
@ 2016-08-31 17:59 Ard Biesheuvel
2016-08-31 17:59 ` [PATCH v2 1/6] ArmVirtPkg/PciHostBridgeDxe: don't set linux, pci-probe-only DT property Ard Biesheuvel
` (6 more replies)
0 siblings, 7 replies; 17+ messages in thread
From: Ard Biesheuvel @ 2016-08-31 17:59 UTC (permalink / raw)
To: edk2-devel, lersek; +Cc: leif.lindholm, Ard Biesheuvel
Now that Laszlo's virtio-gpu-pci series has removed the last remaining obstacle,
we can get rid of the special PciHostBridgeDxe implementation in ArmVirtPkg,
and move to the generic one. On AArch64, this will allow us to perform DMA above
4GB without bounce buffering, and use 64-bit MMIO BARs allocated above 4 GB.
Changes since v1:
- new patch #2 to move the IoTranslation discovery to FdtPciPcdProducerLib,
which is a cleaner approach since other drivers (i.e., ArmPciCpuIo2Dxe)
depend on it as well
- add support for ARM, i.e., disable the 64-bit range in that case, since we
cannot access 64-bit MMIO BARs if they are allocated there
- use statically allocated PCI_ROOT_BRIDGE[] array of size 1
- enable support for ISA and VGA I/O range decoding
- various other minor fixes based on Laszlo's review comments
- added ref links and Laszlo's acks where appropriate, i.e., where given and
where the version of the patch in this series does not deviate substantially
from the suggested version on which the preliminary ack was based
Patch #1 removes the linux,pci-probe-only override which does more harm than
good now that we switched to virtio-gpu-pci, which does not expose a raw
framebuffer.
Patch #2 extends FdtPciPcdProducerLib so that it also sets PcdPciIoTranslation,
which is required for the FdtPciHostBridgeLib implementation this series
introduces, but also for ArmPciCpuIo2Dxe, which produces EFI_CPU_IO2_PROTOCOL
on which the generic PciHostBridgeDxe depends as well.
Patch #3 implements PciHostBridgeLib for platforms exposing a PCI host bridge
using a pci-host-ecam-generic DT node. The initial version is based on the
ArmVirtPkg implementation of PciHostBridgeDxe, so it does not support 64-bit
MMIO BARs allocated above 4 GB, but it does support DMA above 4 GB without
bounce buffering.
Patch #4 switches to the generic PciHostBridgeDxe, with no change in
functionality other than support for DMA above 4 GB without bounce buffering.
Patch #5 adds support for allocating 64-bit MMIO BARs above 4 GB.
Patch #6 removes the now obsolete PciHostBridgeDxe from ArmVirtPkg.
Ard Biesheuvel (6):
ArmVirtPkg/PciHostBridgeDxe: don't set linux,pci-probe-only DT
property
ArmVirtPkg/FdtPciPcdProducerLib: add handling of PcdPciIoTranslation
ArmVirtPkg: implement FdtPciHostBridgeLib
ArmVirtPkg/ArmVirtQemu: switch to generic PciHostBridgeDxe
ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 support
ArmVirtPkg: remove now unused PciHostBridgeDxe
ArmVirtPkg/ArmVirtQemu.dsc | 10 +-
ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 3 +-
ArmVirtPkg/ArmVirtQemuKernel.dsc | 10 +-
ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 434 ++++
ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf | 57 +
ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.c | 108 +-
ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf | 2 +
ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c | 1496 --------------
ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.h | 499 -----
ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf | 64 -
ArmVirtPkg/PciHostBridgeDxe/PciRootBridgeIo.c | 2144 --------------------
11 files changed, 611 insertions(+), 4216 deletions(-)
create mode 100644 ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
create mode 100644 ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
delete mode 100644 ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c
delete mode 100644 ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.h
delete mode 100644 ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf
delete mode 100644 ArmVirtPkg/PciHostBridgeDxe/PciRootBridgeIo.c
--
2.7.4
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 1/6] ArmVirtPkg/PciHostBridgeDxe: don't set linux, pci-probe-only DT property
2016-08-31 17:59 [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe Ard Biesheuvel
@ 2016-08-31 17:59 ` Ard Biesheuvel
2016-08-31 17:59 ` [PATCH v2 2/6] ArmVirtPkg/FdtPciPcdProducerLib: add handling of PcdPciIoTranslation Ard Biesheuvel
` (5 subsequent siblings)
6 siblings, 0 replies; 17+ messages in thread
From: Ard Biesheuvel @ 2016-08-31 17:59 UTC (permalink / raw)
To: edk2-devel, lersek; +Cc: leif.lindholm, Ard Biesheuvel
Setting the linux,pci-probe-only was intended to align OSes booting via
DT with OSes booting via ACPI in the way they honor the PCI configuration
performed by the firmware. However, ACPI on arm64 does not currently honor
the firmware's PCI configuration, and the linux,pci-probe-only completely
prevents any PCI reconfiguration from occurring under the OS, including
what is needed to support PCI hotplug.
Since the primary use case was OS access to the GOP framebuffer (which
breaks when the framebuffer BAR is moved when the OS reconfigures the
PCI), we can undo this change now that ArmVirtQemu has moved to a GOP
implementation that does not expose a raw framebuffer in the first place.
This effectively reverts commit 8b816c624dd4 ("ArmVirtPkg/VirtFdtDxe: set
/chosen/linux,pci-probe-only to 1 in DTB")
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65
---
ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c | 38 --------------------
1 file changed, 38 deletions(-)
diff --git a/ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c b/ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c
index 5063782bb392..669c90355889 100644
--- a/ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c
+++ b/ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c
@@ -79,42 +79,6 @@ PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {
// Implementation
//
-STATIC
-VOID
-SetLinuxPciProbeOnlyProperty (
- IN FDT_CLIENT_PROTOCOL *FdtClient
- )
-{
- INT32 Node;
- UINT32 Tmp;
- EFI_STATUS Status;
-
- if (!FeaturePcdGet (PcdPureAcpiBoot)) {
- //
- // Set the /chosen/linux,pci-probe-only property to 1, so that the PCI
- // setup we will perform in the firmware is honored by the Linux OS,
- // rather than torn down and done from scratch. This is generally a more
- // sensible approach, and aligns with what ACPI based OSes do typically.
- //
- // In case we are exposing an emulated VGA PCI device to the guest, which
- // may subsequently get exposed via the Graphics Output protocol and
- // driven as an efifb by Linux, we need this setting to prevent the
- // framebuffer from becoming unresponsive.
- //
- Status = FdtClient->GetOrInsertChosenNode (FdtClient, &Node);
-
- if (!EFI_ERROR (Status)) {
- Tmp = SwapBytes32 (1);
- Status = FdtClient->SetNodeProperty (FdtClient, Node,
- "linux,pci-probe-only", &Tmp, sizeof (Tmp));
- }
- if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_WARN,
- "Failed to set /chosen/linux,pci-probe-only property\n"));
- }
- }
-}
-
//
// We expect the "ranges" property of "pci-host-ecam-generic" to consist of
// records like this.
@@ -293,8 +257,6 @@ ProcessPciHost (
//
ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase);
- SetLinuxPciProbeOnlyProperty (FdtClient);
-
DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "
"Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x%Lx\n", __FUNCTION__, ConfigBase,
ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, *IoTranslation, *MmioBase,
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 2/6] ArmVirtPkg/FdtPciPcdProducerLib: add handling of PcdPciIoTranslation
2016-08-31 17:59 [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe Ard Biesheuvel
2016-08-31 17:59 ` [PATCH v2 1/6] ArmVirtPkg/PciHostBridgeDxe: don't set linux, pci-probe-only DT property Ard Biesheuvel
@ 2016-08-31 17:59 ` Ard Biesheuvel
2016-09-02 11:19 ` Laszlo Ersek
2016-08-31 17:59 ` [PATCH v2 3/6] ArmVirtPkg: implement FdtPciHostBridgeLib Ard Biesheuvel
` (4 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Ard Biesheuvel @ 2016-08-31 17:59 UTC (permalink / raw)
To: edk2-devel, lersek; +Cc: leif.lindholm, Ard Biesheuvel
Add handling of the PcdPciIoTranslation PCD, so that modules that include
this library via NULL resolution are guaranteed that it will be set before
they reference it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65
---
ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.c | 108 ++++++++++++++++++--
ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf | 2 +
2 files changed, 100 insertions(+), 10 deletions(-)
diff --git a/ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.c b/ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.c
index cc60940d487c..862ee227fffa 100644
--- a/ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.c
+++ b/ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.c
@@ -22,6 +22,68 @@
#include <Protocol/FdtClient.h>
+//
+// We expect the "ranges" property of "pci-host-ecam-generic" to consist of
+// records like this.
+//
+#pragma pack (1)
+typedef struct {
+ UINT32 Type;
+ UINT64 ChildBase;
+ UINT64 CpuBase;
+ UINT64 Size;
+} DTB_PCI_HOST_RANGE_RECORD;
+#pragma pack ()
+
+#define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31
+#define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
+#define DTB_PCI_HOST_RANGE_ALIASED BIT29
+#define DTB_PCI_HOST_RANGE_MMIO32 BIT25
+#define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)
+#define DTB_PCI_HOST_RANGE_IO BIT24
+#define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
+
+STATIC
+RETURN_STATUS
+GetPciIoTranslation (
+ IN FDT_CLIENT_PROTOCOL *FdtClient,
+ IN INT32 Node,
+ OUT UINT64 *IoTranslation
+ )
+{
+ UINT32 RecordIdx;
+ CONST VOID *Prop;
+ UINT32 Len;
+ EFI_STATUS Status;
+ UINT64 IoBase;
+
+ //
+ // Iterate over "ranges".
+ //
+ Status = FdtClient->GetNodeProperty (FdtClient, Node, "ranges", &Prop, &Len);
+ if (EFI_ERROR (Status) || Len == 0 ||
+ Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) {
+ DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));
+ return RETURN_PROTOCOL_ERROR;
+ }
+
+ for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);
+ ++RecordIdx) {
+ CONST DTB_PCI_HOST_RANGE_RECORD *Record;
+ UINT32 Type;
+
+ Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;
+ Type = SwapBytes32 (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK;
+ if (Type == DTB_PCI_HOST_RANGE_IO) {
+ IoBase = SwapBytes64 (Record->ChildBase);
+ *IoTranslation = SwapBytes64 (Record->CpuBase) - IoBase;
+
+ return RETURN_SUCCESS;
+ }
+ }
+ return RETURN_NOT_FOUND;
+}
+
RETURN_STATUS
EFIAPI
FdtPciPcdProducerLibConstructor (
@@ -31,11 +93,21 @@ FdtPciPcdProducerLibConstructor (
UINT64 PciExpressBaseAddress;
FDT_CLIENT_PROTOCOL *FdtClient;
CONST UINT64 *Reg;
- UINT32 RegElemSize, RegSize;
+ UINT32 RegSize;
EFI_STATUS Status;
+ INT32 Node;
+ RETURN_STATUS RetStatus;
+ UINT64 IoTranslation;
PciExpressBaseAddress = PcdGet64 (PcdPciExpressBaseAddress);
if (PciExpressBaseAddress != MAX_UINT64) {
+ //
+ // Assume that the fact that PciExpressBaseAddress has been changed from
+ // its default value of MAX_UINT64 implies that this code has been
+ // executed already, in the context of another module. That means we can
+ // assume that PcdPciIoTranslation has been discovered from the DT node
+ // as well.
+ //
return EFI_SUCCESS;
}
@@ -43,17 +115,33 @@ FdtPciPcdProducerLibConstructor (
(VOID **)&FdtClient);
ASSERT_EFI_ERROR (Status);
- Status = FdtClient->FindCompatibleNodeReg (FdtClient,
- "pci-host-ecam-generic", (CONST VOID **)&Reg,
- &RegElemSize, &RegSize);
+ PciExpressBaseAddress = 0;
+ Status = FdtClient->FindCompatibleNode (FdtClient, "pci-host-ecam-generic",
+ &Node);
+
+ if (!EFI_ERROR (Status)) {
+ Status = FdtClient->GetNodeProperty (FdtClient, Node, "reg",
+ (CONST VOID **)&Reg, &RegSize);
+
+ if (!EFI_ERROR (Status) && RegSize == 2 * sizeof(UINT64)) {
+ PciExpressBaseAddress = SwapBytes64 (*Reg);
- if (EFI_ERROR (Status)) {
- PciExpressBaseAddress = 0;
- } else {
- ASSERT (RegElemSize == sizeof (UINT64));
- PciExpressBaseAddress = SwapBytes64 (*Reg);
+ PcdSetBool (PcdPciDisableBusEnumeration, FALSE);
- PcdSetBool (PcdPciDisableBusEnumeration, FALSE);
+ RetStatus = GetPciIoTranslation (FdtClient, Node, &IoTranslation);
+ if (!RETURN_ERROR (RetStatus)) {
+ PcdSet64 (PcdPciIoTranslation, IoTranslation);
+ } else {
+ //
+ // Support for I/O BARs is not mandatory, and so it does not make sense
+ // to abort in the general case. So leave it up to the actual driver to
+ // complain about this if it wants to, and just issue a warning here.
+ //
+ DEBUG ((EFI_D_WARN,
+ "%a: 'pci-host-ecam-generic' device encountered with no I/O range\n",
+ __FUNCTION__));
+ }
+ }
}
PcdSet64 (PcdPciExpressBaseAddress, PciExpressBaseAddress);
diff --git a/ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf b/ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
index 1ba71abea78a..cd138fa1aa6e 100644
--- a/ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
+++ b/ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
@@ -26,6 +26,7 @@ [Sources]
FdtPciPcdProducerLib.c
[Packages]
+ ArmPkg/ArmPkg.dec
ArmVirtPkg/ArmVirtPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
@@ -40,6 +41,7 @@ [Protocols]
gFdtClientProtocolGuid ## CONSUMES
[Pcd]
+ gArmTokenSpaceGuid.PcdPciIoTranslation ## PRODUCES
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## PRODUCES
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration ## PRODUCES
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 3/6] ArmVirtPkg: implement FdtPciHostBridgeLib
2016-08-31 17:59 [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe Ard Biesheuvel
2016-08-31 17:59 ` [PATCH v2 1/6] ArmVirtPkg/PciHostBridgeDxe: don't set linux, pci-probe-only DT property Ard Biesheuvel
2016-08-31 17:59 ` [PATCH v2 2/6] ArmVirtPkg/FdtPciPcdProducerLib: add handling of PcdPciIoTranslation Ard Biesheuvel
@ 2016-08-31 17:59 ` Ard Biesheuvel
2016-09-02 10:15 ` Laszlo Ersek
2016-08-31 17:59 ` [PATCH v2 4/6] ArmVirtPkg/ArmVirtQemu: switch to generic PciHostBridgeDxe Ard Biesheuvel
` (3 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Ard Biesheuvel @ 2016-08-31 17:59 UTC (permalink / raw)
To: edk2-devel, lersek; +Cc: leif.lindholm, Ard Biesheuvel
Implement PciHostBridgeLib for DT platforms that expose a PCI root bridge
via a pci-host-ecam-generic DT node. The DT parsing logic is copied from
the PciHostBridgeDxe implementation in ArmVirtPkg, with the one notable
difference that we don't set the various legacy PCI attributes for IDE
and VGA I/O ranges.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65
---
ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 400 ++++++++++++++++++++
ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf | 56 +++
2 files changed, 456 insertions(+)
diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
new file mode 100644
index 000000000000..c2aa4a339c19
--- /dev/null
+++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
@@ -0,0 +1,400 @@
+/** @file
+ PCI Host Bridge Library instance for pci-ecam-generic DT nodes
+
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+ IMPLIED.
+
+**/
+#include <PiDxe.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/FdtClient.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+
+#pragma pack(1)
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A08), // PCI Express
+ 0
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+ L"Mem", L"I/O", L"Bus"
+};
+
+//
+// We expect the "ranges" property of "pci-host-ecam-generic" to consist of
+// records like this.
+//
+#pragma pack (1)
+typedef struct {
+ UINT32 Type;
+ UINT64 ChildBase;
+ UINT64 CpuBase;
+ UINT64 Size;
+} DTB_PCI_HOST_RANGE_RECORD;
+#pragma pack ()
+
+#define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31
+#define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
+#define DTB_PCI_HOST_RANGE_ALIASED BIT29
+#define DTB_PCI_HOST_RANGE_MMIO32 BIT25
+#define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)
+#define DTB_PCI_HOST_RANGE_IO BIT24
+#define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
+
+STATIC
+EFI_STATUS
+ProcessPciHost (
+ OUT UINT64 *IoBase,
+ OUT UINT64 *IoSize,
+ OUT UINT64 *MmioBase,
+ OUT UINT64 *MmioSize,
+ OUT UINT32 *BusMin,
+ OUT UINT32 *BusMax
+ )
+{
+ FDT_CLIENT_PROTOCOL *FdtClient;
+ INT32 Node;
+ UINT64 ConfigBase, ConfigSize;
+ CONST VOID *Prop;
+ UINT32 Len;
+ UINT32 RecordIdx;
+ EFI_STATUS Status;
+ UINT64 IoTranslation;
+ UINT64 MmioTranslation;
+
+ //
+ // The following output arguments are initialized only in
+ // order to suppress '-Werror=maybe-uninitialized' warnings
+ // *incorrectly* emitted by some gcc versions.
+ //
+ *IoBase = 0;
+ *MmioBase = 0;
+ *BusMin = 0;
+ *BusMax = 0;
+
+ //
+ // *IoSize, *MmioSize and IoTranslation are initialized to zero because the
+ // logic below requires it. However, since they are also affected by the issue
+ // reported above, they are initialized early.
+ //
+ *IoSize = 0;
+ *MmioSize = 0;
+ IoTranslation = 0;
+
+ Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL,
+ (VOID **)&FdtClient);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = FdtClient->FindCompatibleNode (FdtClient, "pci-host-ecam-generic",
+ &Node);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_INFO,
+ "%a: No 'pci-host-ecam-generic' compatible DT node found\n",
+ __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ DEBUG_CODE (
+ INT32 Tmp;
+
+ //
+ // A DT can legally describe multiple PCI host bridges, but we are not
+ // equipped to deal with that. So assert that there is only one.
+ //
+ Status = FdtClient->FindNextCompatibleNode (FdtClient,
+ "pci-host-ecam-generic", Node, &Tmp);
+ ASSERT (Status == EFI_NOT_FOUND);
+ );
+
+ Status = FdtClient->GetNodeProperty (FdtClient, Node, "reg", &Prop, &Len);
+ if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT64)) {
+ DEBUG ((EFI_D_ERROR, "%a: 'reg' property not found or invalid\n",
+ __FUNCTION__));
+ return EFI_PROTOCOL_ERROR;
+ }
+
+ //
+ // Fetch the ECAM window.
+ //
+ ConfigBase = SwapBytes64 (((CONST UINT64 *)Prop)[0]);
+ ConfigSize = SwapBytes64 (((CONST UINT64 *)Prop)[1]);
+
+ //
+ // Fetch the bus range (note: inclusive).
+ //
+ Status = FdtClient->GetNodeProperty (FdtClient, Node, "bus-range", &Prop,
+ &Len);
+ if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT32)) {
+ DEBUG ((EFI_D_ERROR, "%a: 'bus-range' not found or invalid\n",
+ __FUNCTION__));
+ return EFI_PROTOCOL_ERROR;
+ }
+ *BusMin = SwapBytes32 (((CONST UINT32 *)Prop)[0]);
+ *BusMax = SwapBytes32 (((CONST UINT32 *)Prop)[1]);
+
+ //
+ // Sanity check: the config space must accommodate all 4K register bytes of
+ // all 8 functions of all 32 devices of all buses.
+ //
+ if (*BusMax < *BusMin || *BusMax - *BusMin == MAX_UINT32 ||
+ DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < *BusMax - *BusMin + 1) {
+ DEBUG ((EFI_D_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n",
+ __FUNCTION__));
+ return EFI_PROTOCOL_ERROR;
+ }
+
+ //
+ // Iterate over "ranges".
+ //
+ Status = FdtClient->GetNodeProperty (FdtClient, Node, "ranges", &Prop, &Len);
+ if (EFI_ERROR (Status) || Len == 0 ||
+ Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) {
+ DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));
+ return EFI_PROTOCOL_ERROR;
+ }
+
+ for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);
+ ++RecordIdx) {
+ CONST DTB_PCI_HOST_RANGE_RECORD *Record;
+
+ Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;
+ switch (SwapBytes32 (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) {
+ case DTB_PCI_HOST_RANGE_IO:
+ *IoBase = SwapBytes64 (Record->ChildBase);
+ *IoSize = SwapBytes64 (Record->Size);
+ IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;
+
+ ASSERT (PcdGet64 (PcdPciIoTranslation) == IoTranslation);
+ break;
+
+ case DTB_PCI_HOST_RANGE_MMIO32:
+ *MmioBase = SwapBytes64 (Record->ChildBase);
+ *MmioSize = SwapBytes64 (Record->Size);
+ MmioTranslation = SwapBytes64 (Record->CpuBase) - *MmioBase;
+
+ if (*MmioBase > MAX_UINT32 || *MmioSize > MAX_UINT32 ||
+ *MmioBase + *MmioSize > SIZE_4GB) {
+ DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));
+ return EFI_PROTOCOL_ERROR;
+ }
+
+ ASSERT (PcdGet64 (PcdPciMmio32Translation) == MmioTranslation);
+
+ if (MmioTranslation != 0) {
+ DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation "
+ "0x%Lx\n", __FUNCTION__, MmioTranslation));
+ return EFI_UNSUPPORTED;
+ }
+
+ break;
+ }
+ }
+ if (*IoSize == 0 || *MmioSize == 0) {
+ DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__,
+ (*IoSize == 0) ? "IO" : "MMIO32"));
+ return EFI_PROTOCOL_ERROR;
+ }
+
+ //
+ // The dynamic PCD PcdPciExpressBaseAddress should have already been set,
+ // and should match the value we found in the DT node.
+ //
+ ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase);
+
+ DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "
+ "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x0\n", __FUNCTION__, ConfigBase,
+ ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, IoTranslation, *MmioBase,
+ *MmioSize));
+ return EFI_SUCCESS;
+}
+
+STATIC PCI_ROOT_BRIDGE mRootBridge;
+
+/**
+ Return all the root bridge instances in an array.
+
+ @param Count Return the count of root bridge instances.
+
+ @return All the root bridge instances in an array.
+ The array should be passed into PciHostBridgeFreeRootBridges()
+ when it's not used.
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+ UINTN *Count
+ )
+{
+ UINT64 IoBase, IoSize;
+ UINT64 Mmio32Base, Mmio32Size;
+ UINT32 BusMin, BusMax;
+ EFI_STATUS Status;
+
+ if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {
+ DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));
+
+ *Count = 0;
+ return NULL;
+ }
+
+ Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size, &BusMin,
+ &BusMax);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "%a: failed to discover PCI host bridge: %r\n",
+ __FUNCTION__, Status));
+ *Count = 0;
+ return NULL;
+ }
+
+ *Count = 1;
+
+ mRootBridge.Segment = 0;
+ mRootBridge.Supports = EFI_PCI_ATTRIBUTE_ISA_IO_16 |
+ EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 |
+ EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
+ mRootBridge.Attributes = mRootBridge.Supports;
+
+ mRootBridge.DmaAbove4G = TRUE;
+ mRootBridge.NoExtendedConfigSpace = FALSE;
+ mRootBridge.ResourceAssigned = FALSE;
+
+ mRootBridge.AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;
+
+ mRootBridge.Bus.Base = BusMin;
+ mRootBridge.Bus.Limit = BusMax;
+ mRootBridge.Io.Base = IoBase;
+ mRootBridge.Io.Limit = IoBase + IoSize - 1;
+ mRootBridge.Mem.Base = Mmio32Base;
+ mRootBridge.Mem.Limit = Mmio32Base + Mmio32Size - 1;
+ mRootBridge.MemAbove4G.Base = MAX_UINT64;
+ mRootBridge.MemAbove4G.Limit = 0;
+
+ //
+ // No separate ranges for prefetchable and non-prefetchable BARs
+ //
+ mRootBridge.PMem.Base = MAX_UINT64;
+ mRootBridge.PMem.Limit = 0;
+ mRootBridge.PMemAbove4G.Base = MAX_UINT64;
+ mRootBridge.PMemAbove4G.Limit = 0;
+
+ mRootBridge.DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath;
+
+ return &mRootBridge;
+}
+
+/**
+ Free the root bridge instances array returned from
+ PciHostBridgeGetRootBridges().
+
+ @param Bridges The root bridge instances array.
+ @param Count The count of the array.
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+ PCI_ROOT_BRIDGE *Bridges,
+ UINTN Count
+ )
+{
+ ASSERT (Count == 1);
+}
+
+/**
+ Inform the platform that the resource conflict happens.
+
+ @param HostBridgeHandle Handle of the Host Bridge.
+ @param Configuration Pointer to PCI I/O and PCI memory resource
+ descriptors. The Configuration contains the resources
+ for all the root bridges. The resource for each root
+ bridge is terminated with END descriptor and an
+ additional END is appended indicating the end of the
+ entire resources. The resource descriptor field
+ values follow the description in
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ .SubmitResources().
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+ EFI_HANDLE HostBridgeHandle,
+ VOID *Configuration
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ UINTN RootBridgeIndex;
+ DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n"));
+
+ RootBridgeIndex = 0;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
+ for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (Descriptor->ResType <
+ (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
+ sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
+ )
+ );
+ DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen, Descriptor->AddrRangeMax
+ ));
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ DEBUG ((EFI_D_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
+ ((Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+ ) != 0) ? L" (Prefetchable)" : L""
+ ));
+ }
+ }
+ //
+ // Skip the END descriptor for root bridge
+ //
+ ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
+ }
+}
diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
new file mode 100644
index 000000000000..fc1d37fb3c23
--- /dev/null
+++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
@@ -0,0 +1,56 @@
+## @file
+# PCI Host Bridge Library instance for pci-ecam-generic DT nodes
+#
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = FdtPciHostBridgeLib
+ FILE_GUID = 59fcb139-2558-4cf0-8d7c-ebac499da727
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciHostBridgeLib
+
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+# VALID_ARCHITECTURES = AARCH64 ARM
+#
+
+[Sources]
+ FdtPciHostBridgeLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmVirtPkg/ArmVirtPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ DebugLib
+ DevicePathLib
+ MemoryAllocationLib
+ PciPcdProducerLib
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdPciMmio32Translation
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdPciIoTranslation
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+[Depex]
+ gFdtClientProtocolGuid
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 4/6] ArmVirtPkg/ArmVirtQemu: switch to generic PciHostBridgeDxe
2016-08-31 17:59 [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe Ard Biesheuvel
` (2 preceding siblings ...)
2016-08-31 17:59 ` [PATCH v2 3/6] ArmVirtPkg: implement FdtPciHostBridgeLib Ard Biesheuvel
@ 2016-08-31 17:59 ` Ard Biesheuvel
2016-08-31 17:59 ` [PATCH v2 5/6] ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 support Ard Biesheuvel
` (2 subsequent siblings)
6 siblings, 0 replies; 17+ messages in thread
From: Ard Biesheuvel @ 2016-08-31 17:59 UTC (permalink / raw)
To: edk2-devel, lersek; +Cc: leif.lindholm, Ard Biesheuvel
Wire up the FdtPciHostBridgeLib introduced in the previous patch
to the generic PciHostBridgeDxe implementation, and drop the special
ArmVirtPkg version. The former's dependency on gEfiCpuIo2ProtocolGuid
is satisfied by adding ArmPciCpuIo2Dxe.inf as well, and adding the PCD
gArmTokenSpaceGuid.PcdPciIoTranslation as a dynamic PCD.
In terms of functionality, the only effect this change should have is
that we will no longer use bounce buffers for DMA above 4 GB. Other
than that, no functional changes are intended.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65
---
ArmVirtPkg/ArmVirtQemu.dsc | 10 +++++++++-
ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 3 ++-
ArmVirtPkg/ArmVirtQemuKernel.dsc | 10 +++++++++-
3 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/ArmVirtPkg/ArmVirtQemu.dsc b/ArmVirtPkg/ArmVirtQemu.dsc
index f8b61402625a..c503ef243f9a 100644
--- a/ArmVirtPkg/ArmVirtQemu.dsc
+++ b/ArmVirtPkg/ArmVirtQemu.dsc
@@ -69,6 +69,8 @@ [LibraryClasses.common]
QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf
FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
PciPcdProducerLib|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
+ PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+ PciHostBridgeLib|ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
[LibraryClasses.common.UEFI_DRIVER]
UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
@@ -210,6 +212,8 @@ [PcdsDynamicDefault.common]
# PCD and PcdPciDisableBusEnumeration above have not been assigned yet
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xFFFFFFFFFFFFFFFF
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0x0
+
#
# Set video resolution for boot options and for text setup.
# PlatformDxe can set the former at runtime.
@@ -363,7 +367,11 @@ [Components.common]
#
# PCI support
#
- ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+ <LibraryClasses>
+ NULL|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
+ }
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {
<LibraryClasses>
NULL|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
diff --git a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
index 900fa54660aa..2571884b20ac 100644
--- a/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
+++ b/ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc
@@ -156,7 +156,8 @@ [FV.FvMain]
#
# PCI support
#
- INF ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
INF OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf
INF OvmfPkg/Virtio10Dxe/Virtio10.inf
diff --git a/ArmVirtPkg/ArmVirtQemuKernel.dsc b/ArmVirtPkg/ArmVirtQemuKernel.dsc
index ea722ddf8ea7..383d9b7d2c0b 100644
--- a/ArmVirtPkg/ArmVirtQemuKernel.dsc
+++ b/ArmVirtPkg/ArmVirtQemuKernel.dsc
@@ -71,6 +71,8 @@ [LibraryClasses.common]
QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf
FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
PciPcdProducerLib|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
+ PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+ PciHostBridgeLib|ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
[LibraryClasses.common.UEFI_DRIVER]
UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
@@ -203,6 +205,8 @@ [PcdsDynamicDefault.common]
# PCD and PcdPciDisableBusEnumeration above have not been assigned yet
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xFFFFFFFFFFFFFFFF
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0x0
+
#
# Set video resolution for boot options and for text setup.
# PlatformDxe can set the former at runtime.
@@ -349,7 +353,11 @@ [Components.common]
#
# PCI support
#
- ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf {
+ <LibraryClasses>
+ NULL|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
+ }
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {
<LibraryClasses>
NULL|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 5/6] ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 support
2016-08-31 17:59 [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe Ard Biesheuvel
` (3 preceding siblings ...)
2016-08-31 17:59 ` [PATCH v2 4/6] ArmVirtPkg/ArmVirtQemu: switch to generic PciHostBridgeDxe Ard Biesheuvel
@ 2016-08-31 17:59 ` Ard Biesheuvel
2016-09-02 10:44 ` Laszlo Ersek
2016-08-31 17:59 ` [PATCH v2 6/6] ArmVirtPkg: remove now unused PciHostBridgeDxe Ard Biesheuvel
2016-09-02 13:09 ` [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe Laszlo Ersek
6 siblings, 1 reply; 17+ messages in thread
From: Ard Biesheuvel @ 2016-08-31 17:59 UTC (permalink / raw)
To: edk2-devel, lersek; +Cc: leif.lindholm, Ard Biesheuvel
If the pci-host-ecam-generic DT node describes a 64-bit MMIO region,
account for it in the PCI_ROOT_BRIDGE description that we return to
the generic PciHostBridgeDxe implementation, which will be able to
allocate BARs from it without any further changes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65
---
ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 78 ++++++++++++++------
ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf | 1 +
2 files changed, 57 insertions(+), 22 deletions(-)
diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
index c2aa4a339c19..efccedcca14f 100644
--- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
+++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
@@ -87,8 +87,10 @@ EFI_STATUS
ProcessPciHost (
OUT UINT64 *IoBase,
OUT UINT64 *IoSize,
- OUT UINT64 *MmioBase,
- OUT UINT64 *MmioSize,
+ OUT UINT64 *Mmio32Base,
+ OUT UINT64 *Mmio32Size,
+ OUT UINT64 *Mmio64Base,
+ OUT UINT64 *Mmio64Size,
OUT UINT32 *BusMin,
OUT UINT32 *BusMax
)
@@ -101,7 +103,8 @@ ProcessPciHost (
UINT32 RecordIdx;
EFI_STATUS Status;
UINT64 IoTranslation;
- UINT64 MmioTranslation;
+ UINT64 Mmio32Translation;
+ UINT64 Mmio64Translation;
//
// The following output arguments are initialized only in
@@ -109,17 +112,19 @@ ProcessPciHost (
// *incorrectly* emitted by some gcc versions.
//
*IoBase = 0;
- *MmioBase = 0;
+ *Mmio32Base = 0;
+ *Mmio64Base = MAX_UINT64;
*BusMin = 0;
*BusMax = 0;
//
- // *IoSize, *MmioSize and IoTranslation are initialized to zero because the
+ // *IoSize, *Mmio##Size and IoTranslation are initialized to zero because the
// logic below requires it. However, since they are also affected by the issue
// reported above, they are initialized early.
//
*IoSize = 0;
- *MmioSize = 0;
+ *Mmio32Size = 0;
+ *Mmio64Size = 0;
IoTranslation = 0;
Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL,
@@ -209,28 +214,43 @@ ProcessPciHost (
break;
case DTB_PCI_HOST_RANGE_MMIO32:
- *MmioBase = SwapBytes64 (Record->ChildBase);
- *MmioSize = SwapBytes64 (Record->Size);
- MmioTranslation = SwapBytes64 (Record->CpuBase) - *MmioBase;
+ *Mmio32Base = SwapBytes64 (Record->ChildBase);
+ *Mmio32Size = SwapBytes64 (Record->Size);
+ Mmio32Translation = SwapBytes64 (Record->CpuBase) - *Mmio32Base;
- if (*MmioBase > MAX_UINT32 || *MmioSize > MAX_UINT32 ||
- *MmioBase + *MmioSize > SIZE_4GB) {
+ if (*Mmio32Base > MAX_UINT32 || *Mmio32Size > MAX_UINT32 ||
+ *Mmio32Base + *Mmio32Size > SIZE_4GB) {
DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));
return EFI_PROTOCOL_ERROR;
}
- ASSERT (PcdGet64 (PcdPciMmio32Translation) == MmioTranslation);
+ ASSERT (PcdGet64 (PcdPciMmio32Translation) == Mmio32Translation);
- if (MmioTranslation != 0) {
+ if (Mmio32Translation != 0) {
DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation "
- "0x%Lx\n", __FUNCTION__, MmioTranslation));
+ "0x%Lx\n", __FUNCTION__, Mmio32Translation));
+ return EFI_UNSUPPORTED;
+ }
+
+ break;
+
+ case DTB_PCI_HOST_RANGE_MMIO64:
+ *Mmio64Base = SwapBytes64 (Record->ChildBase);
+ *Mmio64Size = SwapBytes64 (Record->Size);
+ Mmio64Translation = SwapBytes64 (Record->CpuBase) - *Mmio64Base;
+
+ ASSERT (PcdGet64 (PcdPciMmio64Translation) == Mmio64Translation);
+
+ if (Mmio64Translation != 0) {
+ DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO64 translation "
+ "0x%Lx\n", __FUNCTION__, Mmio64Translation));
return EFI_UNSUPPORTED;
}
break;
}
}
- if (*IoSize == 0 || *MmioSize == 0) {
+ if (*IoSize == 0 || *Mmio32Size == 0) {
DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__,
(*IoSize == 0) ? "IO" : "MMIO32"));
return EFI_PROTOCOL_ERROR;
@@ -243,9 +263,9 @@ ProcessPciHost (
ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase);
DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "
- "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x0\n", __FUNCTION__, ConfigBase,
- ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, IoTranslation, *MmioBase,
- *MmioSize));
+ "Io[0x%Lx+0x%Lx)@0x%Lx Mem32[0x%Lx+0x%Lx)@0x0 Mem64[0x%Lx+0x%Lx)@0x0\n",
+ __FUNCTION__, ConfigBase, ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize,
+ IoTranslation, *Mmio32Base, *Mmio32Size, *Mmio64Base, *Mmio64Size));
return EFI_SUCCESS;
}
@@ -268,6 +288,7 @@ PciHostBridgeGetRootBridges (
{
UINT64 IoBase, IoSize;
UINT64 Mmio32Base, Mmio32Size;
+ UINT64 Mmio64Base, Mmio64Size;
UINT32 BusMin, BusMax;
EFI_STATUS Status;
@@ -278,8 +299,8 @@ PciHostBridgeGetRootBridges (
return NULL;
}
- Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size, &BusMin,
- &BusMax);
+ Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size,
+ &Mmio64Base, &Mmio64Size, &BusMin, &BusMax);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "%a: failed to discover PCI host bridge: %r\n",
__FUNCTION__, Status));
@@ -308,8 +329,21 @@ PciHostBridgeGetRootBridges (
mRootBridge.Io.Limit = IoBase + IoSize - 1;
mRootBridge.Mem.Base = Mmio32Base;
mRootBridge.Mem.Limit = Mmio32Base + Mmio32Size - 1;
- mRootBridge.MemAbove4G.Base = MAX_UINT64;
- mRootBridge.MemAbove4G.Limit = 0;
+
+ if (sizeof (UINTN) == sizeof (UINT64)) {
+ mRootBridge.MemAbove4G.Base = Mmio64Base;
+ mRootBridge.MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1;
+ mRootBridge.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
+ } else {
+ //
+ // UEFI mandates a 1:1 virtual-to-physical mapping, so on a 32-bit
+ // architecture such as ARM, we will not be able to access 64-bit MMIO
+ // BARs unless they are allocated below 4 GB. So ignore the range above
+ // 4 GB in this case.
+ //
+ mRootBridge.MemAbove4G.Base = MAX_UINT64;
+ mRootBridge.MemAbove4G.Limit = 0;
+ }
//
// No separate ranges for prefetchable and non-prefetchable BARs
diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
index fc1d37fb3c23..0995f4b7a156 100644
--- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
+++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
@@ -47,6 +47,7 @@ [LibraryClasses]
[FixedPcd]
gArmTokenSpaceGuid.PcdPciMmio32Translation
+ gArmTokenSpaceGuid.PcdPciMmio64Translation
[Pcd]
gArmTokenSpaceGuid.PcdPciIoTranslation
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 6/6] ArmVirtPkg: remove now unused PciHostBridgeDxe
2016-08-31 17:59 [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe Ard Biesheuvel
` (4 preceding siblings ...)
2016-08-31 17:59 ` [PATCH v2 5/6] ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 support Ard Biesheuvel
@ 2016-08-31 17:59 ` Ard Biesheuvel
2016-09-02 13:09 ` [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe Laszlo Ersek
6 siblings, 0 replies; 17+ messages in thread
From: Ard Biesheuvel @ 2016-08-31 17:59 UTC (permalink / raw)
To: edk2-devel, lersek; +Cc: leif.lindholm, Ard Biesheuvel
This code is now no longer used, so remove it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65
---
ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c | 1458 -------------
ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.h | 499 -----
ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf | 64 -
ArmVirtPkg/PciHostBridgeDxe/PciRootBridgeIo.c | 2144 --------------------
4 files changed, 4165 deletions(-)
diff --git a/ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c b/ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c
deleted file mode 100644
index 669c90355889..000000000000
--- a/ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c
+++ /dev/null
@@ -1,1458 +0,0 @@
-/** @file
- Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation
-
-Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are
-licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "PciHostBridge.h"
-
-//
-// Hard code: Root Bridge Number within the host bridge
-// Root Bridge's attribute
-// Root Bridge's device path
-// Root Bridge's resource aperture
-//
-UINTN RootBridgeNumber[1] = { 1 };
-
-UINT64 RootBridgeAttribute[1][1] = { { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM } };
-
-EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {
- {
- {
- {
- {
- ACPI_DEVICE_PATH,
- ACPI_DP,
- {
- (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
- (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
- }
- },
- EISA_PNP_ID(0x0A03),
- 0
- },
-
- {
- END_DEVICE_PATH_TYPE,
- END_ENTIRE_DEVICE_PATH_SUBTYPE,
- {
- END_DEVICE_PATH_LENGTH,
- 0
- }
- }
- }
- }
-};
-
-STATIC PCI_ROOT_BRIDGE_RESOURCE_APERTURE mResAperture[1][1];
-
-EFI_HANDLE mDriverImageHandle;
-
-PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {
- PCI_HOST_BRIDGE_SIGNATURE, // Signature
- NULL, // HostBridgeHandle
- 0, // RootBridgeNumber
- {NULL, NULL}, // Head
- FALSE, // ResourceSubiteed
- TRUE, // CanRestarted
- {
- NotifyPhase,
- GetNextRootBridge,
- GetAttributes,
- StartBusEnumeration,
- SetBusNumbers,
- SubmitResources,
- GetProposedResources,
- PreprocessController
- }
-};
-
-//
-// Implementation
-//
-
-//
-// We expect the "ranges" property of "pci-host-ecam-generic" to consist of
-// records like this.
-//
-#pragma pack (1)
-typedef struct {
- UINT32 Type;
- UINT64 ChildBase;
- UINT64 CpuBase;
- UINT64 Size;
-} DTB_PCI_HOST_RANGE_RECORD;
-#pragma pack ()
-
-#define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31
-#define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
-#define DTB_PCI_HOST_RANGE_ALIASED BIT29
-#define DTB_PCI_HOST_RANGE_MMIO32 BIT25
-#define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)
-#define DTB_PCI_HOST_RANGE_IO BIT24
-#define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
-
-STATIC
-EFI_STATUS
-ProcessPciHost (
- OUT UINT64 *IoBase,
- OUT UINT64 *IoSize,
- OUT UINT64 *IoTranslation,
- OUT UINT64 *MmioBase,
- OUT UINT64 *MmioSize,
- OUT UINT64 *MmioTranslation,
- OUT UINT32 *BusMin,
- OUT UINT32 *BusMax
- )
-{
- FDT_CLIENT_PROTOCOL *FdtClient;
- INT32 Node;
- UINT64 ConfigBase, ConfigSize;
- CONST VOID *Prop;
- UINT32 Len;
- UINT32 RecordIdx;
- EFI_STATUS Status;
-
- //
- // The following output arguments are initialized only in
- // order to suppress '-Werror=maybe-uninitialized' warnings
- // *incorrectly* emitted by some gcc versions.
- //
- *IoBase = 0;
- *IoTranslation = 0;
- *MmioBase = 0;
- *MmioTranslation = 0;
- *BusMin = 0;
- *BusMax = 0;
-
- //
- // *IoSize and *MmioSize are initialized to zero because the logic below
- // requires it. However, since they are also affected by the issue reported
- // above, they are initialized early.
- //
- *IoSize = 0;
- *MmioSize = 0;
-
- Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL,
- (VOID **)&FdtClient);
- ASSERT_EFI_ERROR (Status);
-
- Status = FdtClient->FindCompatibleNode (FdtClient, "pci-host-ecam-generic",
- &Node);
- if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_INFO,
- "%a: No 'pci-host-ecam-generic' compatible DT node found\n",
- __FUNCTION__));
- return EFI_NOT_FOUND;
- }
-
- DEBUG_CODE (
- INT32 Tmp;
-
- //
- // A DT can legally describe multiple PCI host bridges, but we are not
- // equipped to deal with that. So assert that there is only one.
- //
- Status = FdtClient->FindNextCompatibleNode (FdtClient,
- "pci-host-ecam-generic", Node, &Tmp);
- ASSERT (Status == EFI_NOT_FOUND);
- );
-
- Status = FdtClient->GetNodeProperty (FdtClient, Node, "reg", &Prop, &Len);
- if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT64)) {
- DEBUG ((EFI_D_ERROR, "%a: 'reg' property not found or invalid\n",
- __FUNCTION__));
- return EFI_PROTOCOL_ERROR;
- }
-
- //
- // Fetch the ECAM window.
- //
- ConfigBase = SwapBytes64 (((CONST UINT64 *)Prop)[0]);
- ConfigSize = SwapBytes64 (((CONST UINT64 *)Prop)[1]);
-
- //
- // Fetch the bus range (note: inclusive).
- //
- Status = FdtClient->GetNodeProperty (FdtClient, Node, "bus-range", &Prop,
- &Len);
- if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT32)) {
- DEBUG ((EFI_D_ERROR, "%a: 'bus-range' not found or invalid\n",
- __FUNCTION__));
- return EFI_PROTOCOL_ERROR;
- }
- *BusMin = SwapBytes32 (((CONST UINT32 *)Prop)[0]);
- *BusMax = SwapBytes32 (((CONST UINT32 *)Prop)[1]);
-
- //
- // Sanity check: the config space must accommodate all 4K register bytes of
- // all 8 functions of all 32 devices of all buses.
- //
- if (*BusMax < *BusMin || *BusMax - *BusMin == MAX_UINT32 ||
- DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < *BusMax - *BusMin + 1) {
- DEBUG ((EFI_D_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n",
- __FUNCTION__));
- return EFI_PROTOCOL_ERROR;
- }
-
- //
- // Iterate over "ranges".
- //
- Status = FdtClient->GetNodeProperty (FdtClient, Node, "ranges", &Prop, &Len);
- if (EFI_ERROR (Status) || Len == 0 ||
- Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) {
- DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));
- return EFI_PROTOCOL_ERROR;
- }
-
- for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);
- ++RecordIdx) {
- CONST DTB_PCI_HOST_RANGE_RECORD *Record;
-
- Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;
- switch (SwapBytes32 (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) {
- case DTB_PCI_HOST_RANGE_IO:
- *IoBase = SwapBytes64 (Record->ChildBase);
- *IoSize = SwapBytes64 (Record->Size);
- *IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;
- break;
-
- case DTB_PCI_HOST_RANGE_MMIO32:
- *MmioBase = SwapBytes64 (Record->ChildBase);
- *MmioSize = SwapBytes64 (Record->Size);
- *MmioTranslation = SwapBytes64 (Record->CpuBase) - *MmioBase;
-
- if (*MmioBase > MAX_UINT32 || *MmioSize > MAX_UINT32 ||
- *MmioBase + *MmioSize > SIZE_4GB) {
- DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));
- return EFI_PROTOCOL_ERROR;
- }
-
- if (*MmioTranslation != 0) {
- DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation "
- "0x%Lx\n", __FUNCTION__, *MmioTranslation));
- return EFI_UNSUPPORTED;
- }
-
- break;
- }
- }
- if (*IoSize == 0 || *MmioSize == 0) {
- DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__,
- (*IoSize == 0) ? "IO" : "MMIO32"));
- return EFI_PROTOCOL_ERROR;
- }
-
- //
- // The dynamic PCD PcdPciExpressBaseAddress should have already been set,
- // and should match the value we found in the DT node.
- //
- ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase);
-
- DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "
- "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x%Lx\n", __FUNCTION__, ConfigBase,
- ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, *IoTranslation, *MmioBase,
- *MmioSize, *MmioTranslation));
- return EFI_SUCCESS;
-}
-
-
-/**
- Entry point of this driver
-
- @param ImageHandle Handle of driver image
- @param SystemTable Point to EFI_SYSTEM_TABLE
-
- @retval EFI_ABORTED PCI host bridge not present
- @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource
- @retval EFI_DEVICE_ERROR Can not install the protocol instance
- @retval EFI_SUCCESS Success to initialize the Pci host bridge.
-**/
-EFI_STATUS
-EFIAPI
-InitializePciHostBridge (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- UINT64 MmioAttributes;
- EFI_STATUS Status;
- UINTN Loop1;
- UINTN Loop2;
- PCI_HOST_BRIDGE_INSTANCE *HostBridge;
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
- UINT64 IoBase, IoSize, IoTranslation;
- UINT64 MmioBase, MmioSize, MmioTranslation;
- UINT32 BusMin, BusMax;
-
- if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {
- DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));
- return EFI_ABORTED;
- }
-
- Status = ProcessPciHost (&IoBase, &IoSize, &IoTranslation, &MmioBase,
- &MmioSize, &MmioTranslation, &BusMin, &BusMax);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- mDriverImageHandle = ImageHandle;
-
- mResAperture[0][0].BusBase = BusMin;
- mResAperture[0][0].BusLimit = BusMax;
-
- mResAperture[0][0].MemBase = MmioBase;
- mResAperture[0][0].MemLimit = MmioBase + MmioSize - 1;
-
- mResAperture[0][0].IoBase = IoBase;
- mResAperture[0][0].IoLimit = IoBase + IoSize - 1;
- mResAperture[0][0].IoTranslation = IoTranslation;
-
- //
- // Add IO and MMIO memory space, so that resources can be allocated in the
- // EfiPciHostBridgeAllocateResources phase.
- //
- Status = gDS->AddIoSpace (
- EfiGcdIoTypeIo,
- IoBase,
- IoSize
- );
- ASSERT_EFI_ERROR (Status);
-
- MmioAttributes = EFI_MEMORY_UC;
-
- Status = gDS->AddMemorySpace (
- EfiGcdMemoryTypeMemoryMappedIo,
- MmioBase,
- MmioSize,
- MmioAttributes
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "%a: AddMemorySpace: %r\n", __FUNCTION__, Status));
- return Status;
- }
-
- Status = gDS->SetMemorySpaceAttributes (
- MmioBase,
- MmioSize,
- MmioAttributes
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "%a: SetMemorySpaceAttributes: %r\n", __FUNCTION__,
- Status));
- return Status;
- }
-
- //
- // Create Host Bridge Device Handle
- //
- for (Loop1 = 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) {
- HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate);
- if (HostBridge == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- HostBridge->RootBridgeNumber = RootBridgeNumber[Loop1];
- InitializeListHead (&HostBridge->Head);
-
- Status = gBS->InstallMultipleProtocolInterfaces (
- &HostBridge->HostBridgeHandle,
- &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
- NULL
- );
- if (EFI_ERROR (Status)) {
- FreePool (HostBridge);
- return EFI_DEVICE_ERROR;
- }
-
- //
- // Create Root Bridge Device Handle in this Host Bridge
- //
-
- for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {
- PrivateData = AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE));
- if (PrivateData == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
- PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];
-
- RootBridgeConstructor (
- &PrivateData->Io,
- HostBridge->HostBridgeHandle,
- RootBridgeAttribute[Loop1][Loop2],
- &mResAperture[Loop1][Loop2]
- );
-
- Status = gBS->InstallMultipleProtocolInterfaces(
- &PrivateData->Handle,
- &gEfiDevicePathProtocolGuid, PrivateData->DevicePath,
- &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,
- NULL
- );
- if (EFI_ERROR (Status)) {
- FreePool(PrivateData);
- return EFI_DEVICE_ERROR;
- }
-
- InsertTailList (&HostBridge->Head, &PrivateData->Link);
- }
- }
-
- return EFI_SUCCESS;
-}
-
-
-/**
- These are the notifications from the PCI bus driver that it is about to enter a certain
- phase of the PCI enumeration process.
-
- This member function can be used to notify the host bridge driver to perform specific actions,
- including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
- Eight notification points are defined at this time. See belows:
- EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
- structures. The PCI enumerator should issue this notification
- before starting a fresh enumeration process. Enumeration cannot
- be restarted after sending any other notification such as
- EfiPciHostBridgeBeginBusAllocation.
- EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
- required here. This notification can be used to perform any
- chipset-specific programming.
- EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
- specific action is required here. This notification can be used to
- perform any chipset-specific programming.
- EfiPciHostBridgeBeginResourceAllocation
- The resource allocation phase is about to begin. No specific
- action is required here. This notification can be used to perform
- any chipset-specific programming.
- EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
- root bridges. These resource settings are returned on the next call to
- GetProposedResources(). Before calling NotifyPhase() with a Phase of
- EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
- for gathering I/O and memory requests for
- all the PCI root bridges and submitting these requests using
- SubmitResources(). This function pads the resource amount
- to suit the root bridge hardware, takes care of dependencies between
- the PCI root bridges, and calls the Global Coherency Domain (GCD)
- with the allocation request. In the case of padding, the allocated range
- could be bigger than what was requested.
- EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
- resources (proposed resources) for all the PCI root bridges. After the
- hardware is programmed, reassigning resources will not be supported.
- The bus settings are not affected.
- EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
- root bridges and resets the I/O and memory apertures to their initial
- state. The bus settings are not affected. If the request to allocate
- resources fails, the PCI enumerator can use this notification to
- deallocate previous resources, adjust the requests, and retry
- allocation.
- EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
- required here. This notification can be used to perform any chipsetspecific
- programming.
-
- @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- @param[in] Phase The phase during enumeration
-
- @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
- is valid for a Phase of EfiPciHostBridgeAllocateResources if
- SubmitResources() has not been called for one or more
- PCI root bridges before this call
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
- for a Phase of EfiPciHostBridgeSetResources.
- @retval EFI_INVALID_PARAMETER Invalid phase parameter
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
- This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
- previously submitted resource requests cannot be fulfilled or
- were only partially fulfilled.
- @retval EFI_SUCCESS The notification was accepted without any errors.
-
-**/
-EFI_STATUS
-EFIAPI
-NotifyPhase(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
- )
-{
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
- PCI_RESOURCE_TYPE Index;
- LIST_ENTRY *List;
- EFI_PHYSICAL_ADDRESS BaseAddress;
- UINT64 AddrLen;
- UINTN BitsOfAlignment;
- EFI_STATUS Status;
- EFI_STATUS ReturnStatus;
-
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
-
- switch (Phase) {
-
- case EfiPciHostBridgeBeginEnumeration:
- if (HostBridgeInstance->CanRestarted) {
- //
- // Reset the Each Root Bridge
- //
- List = HostBridgeInstance->Head.ForwardLink;
-
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- for (Index = TypeIo; Index < TypeMax; Index++) {
- RootBridgeInstance->ResAllocNode[Index].Type = Index;
- RootBridgeInstance->ResAllocNode[Index].Base = 0;
- RootBridgeInstance->ResAllocNode[Index].Length = 0;
- RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
- }
-
- List = List->ForwardLink;
- }
-
- HostBridgeInstance->ResourceSubmited = FALSE;
- HostBridgeInstance->CanRestarted = TRUE;
- } else {
- //
- // Can not restart
- //
- return EFI_NOT_READY;
- }
- break;
-
- case EfiPciHostBridgeEndEnumeration:
- break;
-
- case EfiPciHostBridgeBeginBusAllocation:
- //
- // No specific action is required here, can perform any chipset specific programing
- //
- HostBridgeInstance->CanRestarted = FALSE;
- break;
-
- case EfiPciHostBridgeEndBusAllocation:
- //
- // No specific action is required here, can perform any chipset specific programing
- //
- //HostBridgeInstance->CanRestarted = FALSE;
- break;
-
- case EfiPciHostBridgeBeginResourceAllocation:
- //
- // No specific action is required here, can perform any chipset specific programing
- //
- //HostBridgeInstance->CanRestarted = FALSE;
- break;
-
- case EfiPciHostBridgeAllocateResources:
- ReturnStatus = EFI_SUCCESS;
- if (HostBridgeInstance->ResourceSubmited) {
- //
- // Take care of the resource dependencies between the root bridges
- //
- List = HostBridgeInstance->Head.ForwardLink;
-
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- for (Index = TypeIo; Index < TypeBus; Index++) {
- if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
-
- AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
-
- //
- // Get the number of '1' in Alignment.
- //
- BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);
-
- switch (Index) {
-
- case TypeIo:
- //
- // It is impossible for this chipset to align 0xFFFF for IO16
- // So clear it
- //
- if (BitsOfAlignment >= 16) {
- BitsOfAlignment = 0;
- }
-
- BaseAddress = mResAperture[0][0].IoLimit;
- Status = gDS->AllocateIoSpace (
- EfiGcdAllocateMaxAddressSearchTopDown,
- EfiGcdIoTypeIo,
- BitsOfAlignment,
- AddrLen,
- &BaseAddress,
- mDriverImageHandle,
- NULL
- );
-
- if (!EFI_ERROR (Status)) {
- RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;
- RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
- } else {
- ReturnStatus = Status;
- if (Status != EFI_OUT_OF_RESOURCES) {
- RootBridgeInstance->ResAllocNode[Index].Length = 0;
- }
- }
-
- break;
-
-
- case TypeMem32:
- //
- // It is impossible for this chipset to align 0xFFFFFFFF for Mem32
- // So clear it
- //
-
- if (BitsOfAlignment >= 32) {
- BitsOfAlignment = 0;
- }
-
- BaseAddress = mResAperture[0][0].MemLimit;
- Status = gDS->AllocateMemorySpace (
- EfiGcdAllocateMaxAddressSearchTopDown,
- EfiGcdMemoryTypeMemoryMappedIo,
- BitsOfAlignment,
- AddrLen,
- &BaseAddress,
- mDriverImageHandle,
- NULL
- );
-
- if (!EFI_ERROR (Status)) {
- // We were able to allocate the PCI memory
- RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;
- RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
-
- } else {
- // Not able to allocate enough PCI memory
- ReturnStatus = Status;
-
- if (Status != EFI_OUT_OF_RESOURCES) {
- RootBridgeInstance->ResAllocNode[Index].Length = 0;
- }
- ASSERT (FALSE);
- }
- break;
-
- case TypePMem32:
- case TypeMem64:
- case TypePMem64:
- ReturnStatus = EFI_ABORTED;
- break;
- default:
- ASSERT (FALSE);
- break;
- }; //end switch
- }
- }
-
- List = List->ForwardLink;
- }
-
- return ReturnStatus;
- } else {
- return EFI_NOT_READY;
- }
-
- case EfiPciHostBridgeSetResources:
- break;
-
- case EfiPciHostBridgeFreeResources:
- ReturnStatus = EFI_SUCCESS;
- List = HostBridgeInstance->Head.ForwardLink;
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- for (Index = TypeIo; Index < TypeBus; Index++) {
- if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {
- AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
- BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;
- switch (Index) {
-
- case TypeIo:
- Status = gDS->FreeIoSpace (BaseAddress, AddrLen);
- if (EFI_ERROR (Status)) {
- ReturnStatus = Status;
- }
- break;
-
- case TypeMem32:
- Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);
- if (EFI_ERROR (Status)) {
- ReturnStatus = Status;
- }
- break;
-
- case TypePMem32:
- break;
-
- case TypeMem64:
- break;
-
- case TypePMem64:
- break;
-
- default:
- ASSERT (FALSE);
- break;
-
- }; //end switch
- RootBridgeInstance->ResAllocNode[Index].Type = Index;
- RootBridgeInstance->ResAllocNode[Index].Base = 0;
- RootBridgeInstance->ResAllocNode[Index].Length = 0;
- RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
- }
- }
-
- List = List->ForwardLink;
- }
-
- HostBridgeInstance->ResourceSubmited = FALSE;
- HostBridgeInstance->CanRestarted = TRUE;
- return ReturnStatus;
-
- case EfiPciHostBridgeEndResourceAllocation:
- HostBridgeInstance->CanRestarted = FALSE;
- break;
-
- default:
- return EFI_INVALID_PARAMETER;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
-
- This function is called multiple times to retrieve the device handles of all the PCI root bridges that
- are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
- root bridges. On each call, the handle that was returned by the previous call is passed into the
- interface, and on output the interface returns the device handle of the next PCI root bridge. The
- caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
- for that root bridge. When there are no more PCI root bridges to report, the interface returns
- EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
- are returned by this function.
- For D945 implementation, there is only one root bridge in PCI host bridge.
-
- @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.
-
- @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
- specific Host bridge and return EFI_SUCCESS.
- @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was
- returned on a previous call to GetNextRootBridge().
-**/
-EFI_STATUS
-EFIAPI
-GetNextRootBridge(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN OUT EFI_HANDLE *RootBridgeHandle
- )
-{
- BOOLEAN NoRootBridge;
- LIST_ENTRY *List;
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
-
- NoRootBridge = TRUE;
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
-
- while (List != &HostBridgeInstance->Head) {
- NoRootBridge = FALSE;
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (*RootBridgeHandle == NULL) {
- //
- // Return the first Root Bridge Handle of the Host Bridge
- //
- *RootBridgeHandle = RootBridgeInstance->Handle;
- return EFI_SUCCESS;
- } else {
- if (*RootBridgeHandle == RootBridgeInstance->Handle) {
- //
- // Get next if have
- //
- List = List->ForwardLink;
- if (List!=&HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- *RootBridgeHandle = RootBridgeInstance->Handle;
- return EFI_SUCCESS;
- } else {
- return EFI_NOT_FOUND;
- }
- }
- }
-
- List = List->ForwardLink;
- } //end while
-
- if (NoRootBridge) {
- return EFI_NOT_FOUND;
- } else {
- return EFI_INVALID_PARAMETER;
- }
-}
-
-/**
- Returns the allocation attributes of a PCI root bridge.
-
- The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
- from one PCI root bridge to another. These attributes are different from the decode-related
- attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
- RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
- handles of all the root bridges that are associated with this host bridge must be obtained by calling
- GetNextRootBridge(). The attributes are static in the sense that they do not change during or
- after the enumeration process. The hardware may provide mechanisms to change the attributes on
- the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
- installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
- "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
- For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
- include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
- prefetchable memory.
- Attribute Description
- ------------------------------------ ----------------------------------------------------------------------
- EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate
- windows for nonprefetchable and prefetchable memory. A PCI bus
- driver needs to include requests for prefetchable memory in the
- nonprefetchable memory pool.
-
- EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory
- windows. If this bit is not set, the PCI bus driver needs to include
- requests for a 64-bit memory address in the corresponding 32-bit
- memory pool.
-
- @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type
- EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
- @param[out] Attributes The pointer to attribte of root bridge, it is output parameter
-
- @retval EFI_INVALID_PARAMETER Attribute pointer is NULL
- @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.
- @retval EFI_SUCCESS Success to get attribute of interested root bridge.
-
-**/
-EFI_STATUS
-EFIAPI
-GetAttributes(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT UINT64 *Attributes
- )
-{
- LIST_ENTRY *List;
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
-
- if (Attributes == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (RootBridgeHandle == RootBridgeInstance->Handle) {
- *Attributes = RootBridgeInstance->RootBridgeAttrib;
- return EFI_SUCCESS;
- }
- List = List->ForwardLink;
- }
-
- //
- // RootBridgeHandle is not an EFI_HANDLE
- // that was returned on a previous call to GetNextRootBridge()
- //
- return EFI_INVALID_PARAMETER;
-}
-
-/**
- Sets up the specified PCI root bridge for the bus enumeration process.
-
- This member function sets up the root bridge for bus enumeration and returns the PCI bus range
- over which the search should be performed in ACPI 2.0 resource descriptor format.
-
- @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
- @param[in] RootBridgeHandle The PCI Root Bridge to be set up.
- @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.
-
- @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
- @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.
- @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.
-
-**/
-EFI_STATUS
-EFIAPI
-StartBusEnumeration(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
- )
-{
- LIST_ENTRY *List;
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
- VOID *Buffer;
- UINT8 *Temp;
- UINT64 BusStart;
- UINT64 BusEnd;
-
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (RootBridgeHandle == RootBridgeInstance->Handle) {
- //
- // Set up the Root Bridge for Bus Enumeration
- //
- BusStart = RootBridgeInstance->BusBase;
- BusEnd = RootBridgeInstance->BusLimit;
- //
- // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR
- //
-
- Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
- if (Buffer == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- Temp = (UINT8 *)Buffer;
-
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len = 0x2B;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;
- ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1;
-
- Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
- ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
- ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
-
- *Configuration = Buffer;
- return EFI_SUCCESS;
- }
- List = List->ForwardLink;
- }
-
- return EFI_INVALID_PARAMETER;
-}
-
-/**
- Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
-
- This member function programs the specified PCI root bridge to decode the bus range that is
- specified by the input parameter Configuration.
- The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
-
- @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
- @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed
- @param[in] Configuration The pointer to the PCI bus resource descriptor
-
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
- @retval EFI_INVALID_PARAMETER Configuration is NULL.
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
- @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.
- @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than
- bus descriptors.
- @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.
- @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
- @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-SetBusNumbers(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
- )
-{
- LIST_ENTRY *List;
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
- UINT8 *Ptr;
- UINTN BusStart;
- UINTN BusEnd;
- UINTN BusLen;
-
- if (Configuration == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- Ptr = Configuration;
-
- //
- // Check the Configuration is valid
- //
- if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
- return EFI_INVALID_PARAMETER;
- }
-
- if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {
- return EFI_INVALID_PARAMETER;
- }
-
- Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
- if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {
- return EFI_INVALID_PARAMETER;
- }
-
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
- Ptr = Configuration;
-
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (RootBridgeHandle == RootBridgeInstance->Handle) {
- BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin;
- BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;
- BusEnd = BusStart + BusLen - 1;
-
- if (BusStart > BusEnd) {
- return EFI_INVALID_PARAMETER;
- }
-
- if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Update the Bus Range
- //
- RootBridgeInstance->ResAllocNode[TypeBus].Base = BusStart;
- RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;
- RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;
-
- //
- // Program the Root Bridge Hardware
- //
-
- return EFI_SUCCESS;
- }
-
- List = List->ForwardLink;
- }
-
- return EFI_INVALID_PARAMETER;
-}
-
-
-/**
- Submits the I/O and memory resource requirements for the specified PCI root bridge.
-
- This function is used to submit all the I/O and memory resources that are required by the specified
- PCI root bridge. The input parameter Configuration is used to specify the following:
- - The various types of resources that are required
- - The associated lengths in terms of ACPI 2.0 resource descriptor format
-
- @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
- @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.
- @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.
-
- @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
- @retval EFI_INVALID_PARAMETER Configuration is NULL.
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
- @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are
- not supported by this PCI root bridge. This error will happen if the caller
- did not combine resources according to Attributes that were returned by
- GetAllocAttributes().
- @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.
-
-**/
-EFI_STATUS
-EFIAPI
-SubmitResources(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
- )
-{
- LIST_ENTRY *List;
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
- UINT8 *Temp;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
- UINT64 AddrLen;
- UINT64 Alignment;
-
- //
- // Check the input parameter: Configuration
- //
- if (Configuration == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
- Temp = (UINT8 *)Configuration;
- while ( *Temp == 0x8A) {
- Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
- }
- if (*Temp != 0x79) {
- return EFI_INVALID_PARAMETER;
- }
-
- Temp = (UINT8 *)Configuration;
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (RootBridgeHandle == RootBridgeInstance->Handle) {
- for (;
- *Temp == 0x8A;
- Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR)
- ) {
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
-
- //
- // Check Address Length
- //
- if (Ptr->AddrLen == 0) {
- HostBridgeInstance->ResourceSubmited = TRUE;
- continue;
- }
- if (Ptr->AddrLen > 0xffffffff) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Check address range alignment
- //
- if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {
- return EFI_INVALID_PARAMETER;
- }
-
- switch (Ptr->ResType) {
-
- case 0:
-
- //
- // Check invalid Address Sapce Granularity
- //
- if (Ptr->AddrSpaceGranularity != 32) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // check the memory resource request is supported by PCI root bridge
- //
- if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&
- Ptr->SpecificFlag == 0x06) {
- return EFI_INVALID_PARAMETER;
- }
-
- AddrLen = Ptr->AddrLen;
- Alignment = Ptr->AddrRangeMax;
- if (Ptr->AddrSpaceGranularity == 32) {
- if (Ptr->SpecificFlag == 0x06) {
- //
- // Apply from GCD
- //
- RootBridgeInstance->ResAllocNode[TypePMem32].Status = ResSubmitted;
- } else {
- RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;
- RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment;
- RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested;
- HostBridgeInstance->ResourceSubmited = TRUE;
- }
- }
-
- if (Ptr->AddrSpaceGranularity == 64) {
- if (Ptr->SpecificFlag == 0x06) {
- RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;
- } else {
- RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;
- }
- }
- break;
-
- case 1:
- AddrLen = (UINTN) Ptr->AddrLen;
- Alignment = (UINTN) Ptr->AddrRangeMax;
- RootBridgeInstance->ResAllocNode[TypeIo].Length = AddrLen;
- RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;
- RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested;
- HostBridgeInstance->ResourceSubmited = TRUE;
- break;
-
- default:
- break;
- };
- }
-
- return EFI_SUCCESS;
- }
-
- List = List->ForwardLink;
- }
-
- return EFI_INVALID_PARAMETER;
-}
-
-/**
- Returns the proposed resource settings for the specified PCI root bridge.
-
- This member function returns the proposed resource settings for the specified PCI root bridge. The
- proposed resource settings are prepared when NotifyPhase() is called with a Phase of
- EfiPciHostBridgeAllocateResources. The output parameter Configuration
- specifies the following:
- - The various types of resources, excluding bus resources, that are allocated
- - The associated lengths in terms of ACPI 2.0 resource descriptor format
-
- @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
- @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
- @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.
-
- @retval EFI_SUCCESS The requested parameters were returned.
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-GetProposedResources(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
- )
-{
- LIST_ENTRY *List;
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
- UINTN Index;
- UINTN Number;
- VOID *Buffer;
- UINT8 *Temp;
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
- UINT64 ResStatus;
-
- Buffer = NULL;
- Number = 0;
- //
- // Get the Host Bridge Instance from the resource allocation protocol
- //
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
- //
- // Enumerate the root bridges in this host bridge
- //
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (RootBridgeHandle == RootBridgeInstance->Handle) {
- for (Index = 0; Index < TypeBus; Index ++) {
- if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
- Number ++;
- }
- }
-
- if (Number == 0) {
- EFI_ACPI_END_TAG_DESCRIPTOR *End;
-
- End = AllocateZeroPool (sizeof *End);
- if (End == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
- End->Desc = ACPI_END_TAG_DESCRIPTOR;
- *Configuration = End;
- return EFI_SUCCESS;
- }
-
- Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
- if (Buffer == NULL) {
- return EFI_OUT_OF_RESOURCES;
- }
-
- Temp = Buffer;
- for (Index = 0; Index < TypeBus; Index ++) {
- if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
- Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
- ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;
-
- switch (Index) {
-
- case TypeIo:
- //
- // Io
- //
- Ptr->Desc = 0x8A;
- Ptr->Len = 0x2B;
- Ptr->ResType = 1;
- Ptr->GenFlag = 0;
- Ptr->SpecificFlag = 0;
- Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
- Ptr->AddrRangeMax = 0;
- Ptr->AddrTranslationOffset = \
- (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
- Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
- break;
-
- case TypeMem32:
- //
- // Memory 32
- //
- Ptr->Desc = 0x8A;
- Ptr->Len = 0x2B;
- Ptr->ResType = 0;
- Ptr->GenFlag = 0;
- Ptr->SpecificFlag = 0;
- Ptr->AddrSpaceGranularity = 32;
- Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
- Ptr->AddrRangeMax = 0;
- Ptr->AddrTranslationOffset = \
- (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
- Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
- break;
-
- case TypePMem32:
- //
- // Prefetch memory 32
- //
- Ptr->Desc = 0x8A;
- Ptr->Len = 0x2B;
- Ptr->ResType = 0;
- Ptr->GenFlag = 0;
- Ptr->SpecificFlag = 6;
- Ptr->AddrSpaceGranularity = 32;
- Ptr->AddrRangeMin = 0;
- Ptr->AddrRangeMax = 0;
- Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
- Ptr->AddrLen = 0;
- break;
-
- case TypeMem64:
- //
- // Memory 64
- //
- Ptr->Desc = 0x8A;
- Ptr->Len = 0x2B;
- Ptr->ResType = 0;
- Ptr->GenFlag = 0;
- Ptr->SpecificFlag = 0;
- Ptr->AddrSpaceGranularity = 64;
- Ptr->AddrRangeMin = 0;
- Ptr->AddrRangeMax = 0;
- Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
- Ptr->AddrLen = 0;
- break;
-
- case TypePMem64:
- //
- // Prefetch memory 64
- //
- Ptr->Desc = 0x8A;
- Ptr->Len = 0x2B;
- Ptr->ResType = 0;
- Ptr->GenFlag = 0;
- Ptr->SpecificFlag = 6;
- Ptr->AddrSpaceGranularity = 64;
- Ptr->AddrRangeMin = 0;
- Ptr->AddrRangeMax = 0;
- Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
- Ptr->AddrLen = 0;
- break;
- };
-
- Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
- }
- }
-
- ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
- ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
-
- *Configuration = Buffer;
-
- return EFI_SUCCESS;
- }
-
- List = List->ForwardLink;
- }
-
- return EFI_INVALID_PARAMETER;
-}
-
-/**
- Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
- stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
- PCI controllers before enumeration.
-
- This function is called during the PCI enumeration process. No specific action is expected from this
- member function. It allows the host bridge driver to preinitialize individual PCI controllers before
- enumeration.
-
- @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
- @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in
- InstallProtocolInterface() in the UEFI 2.0 Specification.
- @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
- configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
- the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
- @param Phase The phase of the PCI device enumeration.
-
- @retval EFI_SUCCESS The requested parameters were returned.
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
- @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
- EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
- not enumerate this device, including its child devices if it is a PCI-to-PCI
- bridge.
-
-**/
-EFI_STATUS
-EFIAPI
-PreprocessController (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
- )
-{
- PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
- PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
- LIST_ENTRY *List;
-
- HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
- List = HostBridgeInstance->Head.ForwardLink;
-
- //
- // Enumerate the root bridges in this host bridge
- //
- while (List != &HostBridgeInstance->Head) {
- RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
- if (RootBridgeHandle == RootBridgeInstance->Handle) {
- break;
- }
- List = List->ForwardLink;
- }
- if (List == &HostBridgeInstance->Head) {
- return EFI_INVALID_PARAMETER;
- }
-
- if ((UINT32)Phase > EfiPciBeforeResourceCollection) {
- return EFI_INVALID_PARAMETER;
- }
-
- return EFI_SUCCESS;
-}
diff --git a/ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.h b/ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.h
deleted file mode 100644
index 647fe1a52a7d..000000000000
--- a/ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.h
+++ /dev/null
@@ -1,499 +0,0 @@
-/** @file
- The Header file of the Pci Host Bridge Driver
-
- Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials are
- licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _PCI_HOST_BRIDGE_H_
-#define _PCI_HOST_BRIDGE_H_
-
-#include <PiDxe.h>
-
-#include <IndustryStandard/Pci.h>
-#include <IndustryStandard/Acpi.h>
-
-#include <Protocol/PciHostBridgeResourceAllocation.h>
-#include <Protocol/PciRootBridgeIo.h>
-#include <Protocol/Metronome.h>
-#include <Protocol/DevicePath.h>
-#include <Protocol/FdtClient.h>
-
-
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/DxeServicesTableLib.h>
-#include <Library/DevicePathLib.h>
-#include <Library/IoLib.h>
-#include <Library/PciLib.h>
-#include <Library/PcdLib.h>
-
-//
-// Hard code the host bridge number in the platform.
-// In this chipset, there is only one host bridge.
-//
-#define HOST_BRIDGE_NUMBER 1
-
-#define MAX_PCI_DEVICE_NUMBER 31
-#define MAX_PCI_FUNCTION_NUMBER 7
-#define MAX_PCI_REG_ADDRESS (SIZE_4KB - 1)
-
-typedef enum {
- IoOperation,
- MemOperation,
- PciOperation
-} OPERATION_TYPE;
-
-#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')
-typedef struct {
- UINTN Signature;
- EFI_HANDLE HostBridgeHandle;
- UINTN RootBridgeNumber;
- LIST_ENTRY Head;
- BOOLEAN ResourceSubmited;
- BOOLEAN CanRestarted;
- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;
-} PCI_HOST_BRIDGE_INSTANCE;
-
-#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \
- CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
-
-//
-// HostBridge Resource Allocation interface
-//
-
-/**
- These are the notifications from the PCI bus driver that it is about to enter a certain
- phase of the PCI enumeration process.
-
- This member function can be used to notify the host bridge driver to perform specific actions,
- including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
- Eight notification points are defined at this time. See belows:
- EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
- structures. The PCI enumerator should issue this notification
- before starting a fresh enumeration process. Enumeration cannot
- be restarted after sending any other notification such as
- EfiPciHostBridgeBeginBusAllocation.
- EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
- required here. This notification can be used to perform any
- chipset-specific programming.
- EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
- specific action is required here. This notification can be used to
- perform any chipset-specific programming.
- EfiPciHostBridgeBeginResourceAllocation
- The resource allocation phase is about to begin. No specific
- action is required here. This notification can be used to perform
- any chipset-specific programming.
- EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
- root bridges. These resource settings are returned on the next call to
- GetProposedResources(). Before calling NotifyPhase() with a Phase of
- EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
- for gathering I/O and memory requests for
- all the PCI root bridges and submitting these requests using
- SubmitResources(). This function pads the resource amount
- to suit the root bridge hardware, takes care of dependencies between
- the PCI root bridges, and calls the Global Coherency Domain (GCD)
- with the allocation request. In the case of padding, the allocated range
- could be bigger than what was requested.
- EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
- resources (proposed resources) for all the PCI root bridges. After the
- hardware is programmed, reassigning resources will not be supported.
- The bus settings are not affected.
- EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
- root bridges and resets the I/O and memory apertures to their initial
- state. The bus settings are not affected. If the request to allocate
- resources fails, the PCI enumerator can use this notification to
- deallocate previous resources, adjust the requests, and retry
- allocation.
- EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
- required here. This notification can be used to perform any chipsetspecific
- programming.
-
- @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- @param[in] Phase The phase during enumeration
-
- @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
- is valid for a Phase of EfiPciHostBridgeAllocateResources if
- SubmitResources() has not been called for one or more
- PCI root bridges before this call
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
- for a Phase of EfiPciHostBridgeSetResources.
- @retval EFI_INVALID_PARAMETER Invalid phase parameter
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
- This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
- previously submitted resource requests cannot be fulfilled or
- were only partially fulfilled.
- @retval EFI_SUCCESS The notification was accepted without any errors.
-
-**/
-EFI_STATUS
-EFIAPI
-NotifyPhase(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
- );
-
-/**
- Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
-
- This function is called multiple times to retrieve the device handles of all the PCI root bridges that
- are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
- root bridges. On each call, the handle that was returned by the previous call is passed into the
- interface, and on output the interface returns the device handle of the next PCI root bridge. The
- caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
- for that root bridge. When there are no more PCI root bridges to report, the interface returns
- EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
- are returned by this function.
- For D945 implementation, there is only one root bridge in PCI host bridge.
-
- @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.
-
- @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
- specific Host bridge and return EFI_SUCCESS.
- @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was
- returned on a previous call to GetNextRootBridge().
-**/
-EFI_STATUS
-EFIAPI
-GetNextRootBridge(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN OUT EFI_HANDLE *RootBridgeHandle
- );
-
-/**
- Returns the allocation attributes of a PCI root bridge.
-
- The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
- from one PCI root bridge to another. These attributes are different from the decode-related
- attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
- RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
- handles of all the root bridges that are associated with this host bridge must be obtained by calling
- GetNextRootBridge(). The attributes are static in the sense that they do not change during or
- after the enumeration process. The hardware may provide mechanisms to change the attributes on
- the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
- installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
- "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
- For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
- include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
- prefetchable memory.
- Attribute Description
- ------------------------------------ ----------------------------------------------------------------------
- EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate
- windows for nonprefetchable and prefetchable memory. A PCI bus
- driver needs to include requests for prefetchable memory in the
- nonprefetchable memory pool.
-
- EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory
- windows. If this bit is not set, the PCI bus driver needs to include
- requests for a 64-bit memory address in the corresponding 32-bit
- memory pool.
-
- @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
- @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type
- EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
- @param[out] Attributes The pointer to attribte of root bridge, it is output parameter
-
- @retval EFI_INVALID_PARAMETER Attribute pointer is NULL
- @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.
- @retval EFI_SUCCESS Success to get attribute of interested root bridge.
-
-**/
-EFI_STATUS
-EFIAPI
-GetAttributes(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT UINT64 *Attributes
- );
-
-/**
- Sets up the specified PCI root bridge for the bus enumeration process.
-
- This member function sets up the root bridge for bus enumeration and returns the PCI bus range
- over which the search should be performed in ACPI 2.0 resource descriptor format.
-
- @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
- @param[in] RootBridgeHandle The PCI Root Bridge to be set up.
- @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.
-
- @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
- @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.
- @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.
-
-**/
-EFI_STATUS
-EFIAPI
-StartBusEnumeration(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
- );
-
-/**
- Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
-
- This member function programs the specified PCI root bridge to decode the bus range that is
- specified by the input parameter Configuration.
- The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
-
- @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
- @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed
- @param[in] Configuration The pointer to the PCI bus resource descriptor
-
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
- @retval EFI_INVALID_PARAMETER Configuration is NULL.
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
- @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.
- @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than
- bus descriptors.
- @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.
- @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
- @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.
-
-**/
-EFI_STATUS
-EFIAPI
-SetBusNumbers(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
- );
-
-/**
- Submits the I/O and memory resource requirements for the specified PCI root bridge.
-
- This function is used to submit all the I/O and memory resources that are required by the specified
- PCI root bridge. The input parameter Configuration is used to specify the following:
- - The various types of resources that are required
- - The associated lengths in terms of ACPI 2.0 resource descriptor format
-
- @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
- @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.
- @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.
-
- @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
- @retval EFI_INVALID_PARAMETER Configuration is NULL.
- @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
- @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are
- not supported by this PCI root bridge. This error will happen if the caller
- did not combine resources according to Attributes that were returned by
- GetAllocAttributes().
- @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.
- @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.
-
-**/
-EFI_STATUS
-EFIAPI
-SubmitResources(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN VOID *Configuration
- );
-
-/**
- Returns the proposed resource settings for the specified PCI root bridge.
-
- This member function returns the proposed resource settings for the specified PCI root bridge. The
- proposed resource settings are prepared when NotifyPhase() is called with a Phase of
- EfiPciHostBridgeAllocateResources. The output parameter Configuration
- specifies the following:
- - The various types of resources, excluding bus resources, that are allocated
- - The associated lengths in terms of ACPI 2.0 resource descriptor format
-
- @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
- @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
- @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.
-
- @retval EFI_SUCCESS The requested parameters were returned.
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-GetProposedResources(
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- OUT VOID **Configuration
- );
-
-/**
- Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
- stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
- PCI controllers before enumeration.
-
- This function is called during the PCI enumeration process. No specific action is expected from this
- member function. It allows the host bridge driver to preinitialize individual PCI controllers before
- enumeration.
-
- @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
- @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in
- InstallProtocolInterface() in the UEFI 2.0 Specification.
- @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
- configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
- the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
- @param Phase The phase of the PCI device enumeration.
-
- @retval EFI_SUCCESS The requested parameters were returned.
- @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
- @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
- EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
- @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
- not enumerate this device, including its child devices if it is a PCI-to-PCI
- bridge.
-
-**/
-EFI_STATUS
-EFIAPI
-PreprocessController (
- IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
- IN EFI_HANDLE RootBridgeHandle,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
- IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
- );
-
-
-//
-// Define resource status constant
-//
-#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
-#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
-
-
-//
-// Driver Instance Data Prototypes
-//
-
-typedef struct {
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
- UINTN NumberOfBytes;
- UINTN NumberOfPages;
- EFI_PHYSICAL_ADDRESS HostAddress;
- EFI_PHYSICAL_ADDRESS MappedHostAddress;
-} MAP_INFO;
-
-typedef struct {
- ACPI_HID_DEVICE_PATH AcpiDevicePath;
- EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
-} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
-
-typedef struct {
- UINT64 BusBase;
- UINT64 BusLimit;
-
- UINT64 MemBase;
- UINT64 MemLimit;
-
- UINT64 IoBase;
- UINT64 IoLimit;
- UINT64 IoTranslation;
-} PCI_ROOT_BRIDGE_RESOURCE_APERTURE;
-
-typedef enum {
- TypeIo = 0,
- TypeMem32,
- TypePMem32,
- TypeMem64,
- TypePMem64,
- TypeBus,
- TypeMax
-} PCI_RESOURCE_TYPE;
-
-typedef enum {
- ResNone = 0,
- ResSubmitted,
- ResRequested,
- ResAllocated,
- ResStatusMax
-} RES_STATUS;
-
-typedef struct {
- PCI_RESOURCE_TYPE Type;
- UINT64 Base;
- UINT64 Length;
- UINT64 Alignment;
- RES_STATUS Status;
-} PCI_RES_NODE;
-
-#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b')
-
-typedef struct {
- UINT32 Signature;
- LIST_ENTRY Link;
- EFI_HANDLE Handle;
- UINT64 RootBridgeAttrib;
- UINT64 Attributes;
- UINT64 Supports;
-
- //
- // Specific for this memory controller: Bus, I/O, Mem
- //
- PCI_RES_NODE ResAllocNode[6];
-
- //
- // Addressing for Memory and I/O and Bus arrange
- //
- UINT64 BusBase;
- UINT64 MemBase;
- UINT64 IoBase;
- UINT64 BusLimit;
- UINT64 MemLimit;
- UINT64 IoLimit;
- UINT64 IoTranslation;
-
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
-
-} PCI_ROOT_BRIDGE_INSTANCE;
-
-
-//
-// Driver Instance Data Macros
-//
-#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \
- CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
-
-
-#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \
- CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
-
-/**
-
- Construct the Pci Root Bridge Io protocol
-
- @param Protocol Point to protocol instance
- @param HostBridgeHandle Handle of host bridge
- @param Attri Attribute of host bridge
- @param ResAperture ResourceAperture for host bridge
-
- @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
-
-**/
-EFI_STATUS
-RootBridgeConstructor (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,
- IN EFI_HANDLE HostBridgeHandle,
- IN UINT64 Attri,
- IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture
- );
-
-#endif
diff --git a/ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf b/ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf
deleted file mode 100644
index 8c75eda3deb5..000000000000
--- a/ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf
+++ /dev/null
@@ -1,64 +0,0 @@
-## @file
-# The basic interfaces implementation to a single segment PCI Host Bridge driver.
-#
-# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PciHostBridge
- FILE_GUID = 9f609346-37cb-4eb7-801f-f55099373998
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
-
- ENTRY_POINT = InitializePciHostBridge
-
-[Packages]
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- ArmVirtPkg/ArmVirtPkg.dec
-
-[LibraryClasses]
- UefiDriverEntryPoint
- UefiBootServicesTableLib
- DxeServicesTableLib
- UefiLib
- MemoryAllocationLib
- BaseMemoryLib
- BaseLib
- DebugLib
- DevicePathLib
- IoLib
- PciLib
- PcdLib
-
-[Sources]
- PciHostBridge.c
- PciRootBridgeIo.c
- PciHostBridge.h
-
-[Protocols]
- gEfiPciHostBridgeResourceAllocationProtocolGuid ## PRODUCES
- gEfiPciRootBridgeIoProtocolGuid ## PRODUCES
- gEfiMetronomeArchProtocolGuid ## CONSUMES
- gEfiDevicePathProtocolGuid ## PRODUCES
- gFdtClientProtocolGuid ## CONSUMES
-
-[Pcd]
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
-
-[FeaturePcd]
- gArmVirtTokenSpaceGuid.PcdPureAcpiBoot
-
-[depex]
- gEfiMetronomeArchProtocolGuid AND
- gEfiCpuArchProtocolGuid AND
- gFdtClientProtocolGuid
diff --git a/ArmVirtPkg/PciHostBridgeDxe/PciRootBridgeIo.c b/ArmVirtPkg/PciHostBridgeDxe/PciRootBridgeIo.c
deleted file mode 100644
index c86788795038..000000000000
--- a/ArmVirtPkg/PciHostBridgeDxe/PciRootBridgeIo.c
+++ /dev/null
@@ -1,2144 +0,0 @@
-/** @file
- PCI Root Bridge Io Protocol implementation
-
-Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are
-licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "PciHostBridge.h"
-
-typedef struct {
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[TypeMax];
- EFI_ACPI_END_TAG_DESCRIPTOR EndDesp;
-} RESOURCE_CONFIGURATION;
-
-RESOURCE_CONFIGURATION Configuration = {
- {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},
- {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},
- {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},
- {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},
- {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},
- {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}},
- {0x79, 0}
-};
-
-//
-// Protocol Member Function Prototypes
-//
-
-/**
- Polls an address in memory mapped I/O space until an exit condition is met, or
- a timeout occurs.
-
- This function provides a standard way to poll a PCI memory location. A PCI memory read
- operation is performed at the PCI memory address specified by Address for the width specified
- by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
- read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
- Mask) is equal to Value.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] Address The base address of the memory operations. The caller is
- responsible for aligning Address if required.
- @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
- are ignored. The bits in the bytes below Width which are zero in
- Mask are ignored when polling the memory address.
- @param[in] Value The comparison value used for the polling exit criteria.
- @param[in] Delay The number of 100 ns units to poll. Note that timer available may
- be of poorer granularity.
- @param[out] Result Pointer to the last value read from the memory location.
-
- @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
- @retval EFI_INVALID_PARAMETER Width is invalid.
- @retval EFI_INVALID_PARAMETER Result is NULL.
- @retval EFI_TIMEOUT Delay expired before a match occurred.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPollMem (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINT64 Mask,
- IN UINT64 Value,
- IN UINT64 Delay,
- OUT UINT64 *Result
- );
-
-/**
- Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
- satisfied or after a defined duration.
-
- This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
- performed at the PCI I/O address specified by Address for the width specified by Width.
- The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
- repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
- to Value.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the I/O operations.
- @param[in] Address The base address of the I/O operations. The caller is responsible
- for aligning Address if required.
- @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
- are ignored. The bits in the bytes below Width which are zero in
- Mask are ignored when polling the I/O address.
- @param[in] Value The comparison value used for the polling exit criteria.
- @param[in] Delay The number of 100 ns units to poll. Note that timer available may
- be of poorer granularity.
- @param[out] Result Pointer to the last value read from the memory location.
-
- @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
- @retval EFI_INVALID_PARAMETER Width is invalid.
- @retval EFI_INVALID_PARAMETER Result is NULL.
- @retval EFI_TIMEOUT Delay expired before a match occurred.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPollIo (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINT64 Mask,
- IN UINT64 Value,
- IN UINT64 Delay,
- OUT UINT64 *Result
- );
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
-
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
- registers in the PCI root bridge memory space.
- The memory operations are carried out exactly as requested. The caller is responsible for satisfying
- any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operation.
- @param[in] Address The base address of the memory operation. The caller is
- responsible for aligning the Address if required.
- @param[in] Count The number of memory operations to perform. Bytes moved is
- Width size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoMemRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- OUT VOID *Buffer
- );
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
-
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
- registers in the PCI root bridge memory space.
- The memory operations are carried out exactly as requested. The caller is responsible for satisfying
- any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operation.
- @param[in] Address The base address of the memory operation. The caller is
- responsible for aligning the Address if required.
- @param[in] Count The number of memory operations to perform. Bytes moved is
- Width size * Count, starting at Address.
- @param[in] Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoMemWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- );
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] UserAddress The base address of the I/O operation. The caller is responsible for
- aligning the Address if required.
- @param[in] Count The number of I/O operations to perform. Bytes moved is Width
- size * Count, starting at Address.
- @param[out] UserBuffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoIoRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 UserAddress,
- IN UINTN Count,
- OUT VOID *UserBuffer
- );
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] UserAddress The base address of the I/O operation. The caller is responsible for
- aligning the Address if required.
- @param[in] Count The number of I/O operations to perform. Bytes moved is Width
- size * Count, starting at Address.
- @param[in] UserBuffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoIoWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 UserAddress,
- IN UINTN Count,
- IN VOID *UserBuffer
- );
-
-/**
- Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
- root bridge memory space.
-
- The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
- space to another region of PCI root bridge memory space. This is especially useful for video scroll
- operation on a memory mapped video buffer.
- The memory operations are carried out exactly as requested. The caller is responsible for satisfying
- any alignment and memory width restrictions that a PCI root bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] DestAddress The destination address of the memory operation. The caller is
- responsible for aligning the DestAddress if required.
- @param[in] SrcAddress The source address of the memory operation. The caller is
- responsible for aligning the SrcAddress if required.
- @param[in] Count The number of memory operations to perform. Bytes moved is
- Width size * Count, starting at DestAddress and SrcAddress.
-
- @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoCopyMem (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 DestAddress,
- IN UINT64 SrcAddress,
- IN UINTN Count
- );
-
-/**
- Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
-
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
- registers for a PCI controller.
- The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
- any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
- require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] Address The address within the PCI configuration space for the PCI controller.
- @param[in] Count The number of PCI configuration operations to perform. Bytes
- moved is Width size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPciRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- OUT VOID *Buffer
- );
-
-/**
- Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
-
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
- registers for a PCI controller.
- The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
- any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
- require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] Address The address within the PCI configuration space for the PCI controller.
- @param[in] Count The number of PCI configuration operations to perform. Bytes
- moved is Width size * Count, starting at Address.
- @param[in] Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPciWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- );
-
-/**
- Provides the PCI controller-specific addresses required to access system memory from a
- DMA bus master.
-
- The Map() function provides the PCI controller specific addresses needed to access system
- memory. This function is used to map system memory for PCI bus master DMA accesses.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Operation Indicates if the bus master is going to read or write to system memory.
- @param[in] HostAddress The system memory address to map to the PCI controller.
- @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
- @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
- to access the system memory's HostAddress.
- @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
-
- @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
- @retval EFI_INVALID_PARAMETER Operation is invalid.
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.
- @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
- @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
- @retval EFI_INVALID_PARAMETER Mapping is NULL.
- @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
- @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoMap (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
- IN VOID *HostAddress,
- IN OUT UINTN *NumberOfBytes,
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
- OUT VOID **Mapping
- );
-
-/**
- Completes the Map() operation and releases any corresponding resources.
-
- The Unmap() function completes the Map() operation and releases any corresponding resources.
- If the operation was an EfiPciOperationBusMasterWrite or
- EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
- Any resources used for the mapping are freed.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Mapping The mapping value returned from Map().
-
- @retval EFI_SUCCESS The range was unmapped.
- @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
- @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoUnmap (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN VOID *Mapping
- );
-
-/**
- Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
- EfiPciOperationBusMasterCommonBuffer64 mapping.
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param Type This parameter is not used and must be ignored.
- @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
- @param Pages The number of pages to allocate.
- @param HostAddress A pointer to store the base system memory address of the allocated range.
- @param Attributes The requested bit mask of attributes for the allocated range. Only
- the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
- and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
-
- @retval EFI_SUCCESS The requested memory pages were allocated.
- @retval EFI_INVALID_PARAMETER MemoryType is invalid.
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.
- @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
- @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoAllocateBuffer (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_ALLOCATE_TYPE Type,
- IN EFI_MEMORY_TYPE MemoryType,
- IN UINTN Pages,
- OUT VOID **HostAddress,
- IN UINT64 Attributes
- );
-
-/**
- Frees memory that was allocated with AllocateBuffer().
-
- The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param Pages The number of pages to free.
- @param HostAddress The base system memory address of the allocated range.
-
- @retval EFI_SUCCESS The requested memory pages were freed.
- @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
- was not allocated with AllocateBuffer().
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoFreeBuffer (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN UINTN Pages,
- OUT VOID *HostAddress
- );
-
-/**
- Flushes all PCI posted write transactions from a PCI host bridge to system memory.
-
- The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
- memory. Posted write transactions are generated by PCI bus masters when they perform write
- transactions to target addresses in system memory.
- This function does not flush posted write transactions from any PCI bridges. A PCI controller
- specific action must be taken to guarantee that the posted write transactions have been flushed from
- the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
- a PCI read transaction from the PCI controller prior to calling Flush().
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
- bridge to system memory.
- @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
- host bridge due to a hardware error.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoFlush (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
- );
-
-/**
- Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
- attributes that a PCI root bridge is currently using.
-
- The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
- and the mask of attributes that the PCI root bridge is currently using.
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param Supported A pointer to the mask of attributes that this PCI root bridge
- supports setting with SetAttributes().
- @param Attributes A pointer to the mask of attributes that this PCI root bridge is
- currently using.
-
- @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root
- bridge supports is returned in Supports. If Attributes is
- not NULL, then the attributes that the PCI root bridge is currently
- using is returned in Attributes.
- @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoGetAttributes (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- OUT UINT64 *Supported,
- OUT UINT64 *Attributes
- );
-
-/**
- Sets attributes for a resource range on a PCI root bridge.
-
- The SetAttributes() function sets the attributes specified in Attributes for the PCI root
- bridge on the resource range specified by ResourceBase and ResourceLength. Since the
- granularity of setting these attributes may vary from resource type to resource type, and from
- platform to platform, the actual resource range and the one passed in by the caller may differ. As a
- result, this function may set the attributes specified by Attributes on a larger resource range
- than the caller requested. The actual range is returned in ResourceBase and
- ResourceLength. The caller is responsible for verifying that the actual range for which the
- attributes were set is acceptable.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Attributes The mask of attributes to set. If the attribute bit
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
- MEMORY_DISABLE is set, then the resource range is specified by
- ResourceBase and ResourceLength. If
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
- MEMORY_DISABLE are not set, then ResourceBase and
- ResourceLength are ignored, and may be NULL.
- @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified
- by the attributes specified by Attributes.
- @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the
- attributes specified by Attributes.
-
- @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
- @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoSetAttributes (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN UINT64 Attributes,
- IN OUT UINT64 *ResourceBase,
- IN OUT UINT64 *ResourceLength
- );
-
-/**
- Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
- resource descriptors.
-
- There are only two resource descriptor types from the ACPI Specification that may be used to
- describe the current resources allocated to a PCI root bridge. These are the QWORD Address
- Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
- QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
- or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
- Address Space Descriptors followed by an End Tag.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the
- current configuration of this PCI root bridge. The storage for the
- ACPI 2.0 resource descriptors is allocated by this function. The
- caller must treat the return buffer as read-only data, and the buffer
- must not be freed by the caller.
-
- @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
- @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoConfiguration (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- OUT VOID **Resources
- );
-
-//
-// Memory Controller Pci Root Bridge Io Module Variables
-//
-EFI_METRONOME_ARCH_PROTOCOL *mMetronome;
-
-//
-// Lookup table for increment values based on transfer widths
-//
-UINT8 mInStride[] = {
- 1, // EfiPciWidthUint8
- 2, // EfiPciWidthUint16
- 4, // EfiPciWidthUint32
- 8, // EfiPciWidthUint64
- 0, // EfiPciWidthFifoUint8
- 0, // EfiPciWidthFifoUint16
- 0, // EfiPciWidthFifoUint32
- 0, // EfiPciWidthFifoUint64
- 1, // EfiPciWidthFillUint8
- 2, // EfiPciWidthFillUint16
- 4, // EfiPciWidthFillUint32
- 8 // EfiPciWidthFillUint64
-};
-
-//
-// Lookup table for increment values based on transfer widths
-//
-UINT8 mOutStride[] = {
- 1, // EfiPciWidthUint8
- 2, // EfiPciWidthUint16
- 4, // EfiPciWidthUint32
- 8, // EfiPciWidthUint64
- 1, // EfiPciWidthFifoUint8
- 2, // EfiPciWidthFifoUint16
- 4, // EfiPciWidthFifoUint32
- 8, // EfiPciWidthFifoUint64
- 0, // EfiPciWidthFillUint8
- 0, // EfiPciWidthFillUint16
- 0, // EfiPciWidthFillUint32
- 0 // EfiPciWidthFillUint64
-};
-
-/**
-
- Construct the Pci Root Bridge Io protocol
-
- @param Protocol Point to protocol instance
- @param HostBridgeHandle Handle of host bridge
- @param Attri Attribute of host bridge
- @param ResAperture ResourceAperture for host bridge
-
- @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
-
-**/
-EFI_STATUS
-RootBridgeConstructor (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,
- IN EFI_HANDLE HostBridgeHandle,
- IN UINT64 Attri,
- IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture
- )
-{
- EFI_STATUS Status;
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
- PCI_RESOURCE_TYPE Index;
-
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);
-
- //
- // The host to PCI bridge. The host memory addresses are direct mapped to PCI
- // addresses, so there's no need to translate them. IO addresses need
- // translation however.
- //
- PrivateData->MemBase = ResAperture->MemBase;
- PrivateData->IoBase = ResAperture->IoBase;
- PrivateData->IoTranslation = ResAperture->IoTranslation;
-
- //
- // The host bridge only supports 32bit addressing for memory
- // and standard IA32 16bit io
- //
- PrivateData->MemLimit = ResAperture->MemLimit;
- PrivateData->IoLimit = ResAperture->IoLimit;
-
- //
- // Bus Aperture for this Root Bridge (Possible Range)
- //
- PrivateData->BusBase = ResAperture->BusBase;
- PrivateData->BusLimit = ResAperture->BusLimit;
-
- //
- // Specific for this chipset
- //
- for (Index = TypeIo; Index < TypeMax; Index++) {
- PrivateData->ResAllocNode[Index].Type = Index;
- PrivateData->ResAllocNode[Index].Base = 0;
- PrivateData->ResAllocNode[Index].Length = 0;
- PrivateData->ResAllocNode[Index].Status = ResNone;
- }
-
- PrivateData->RootBridgeAttrib = Attri;
-
- PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \
- EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
- EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
- EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
- PrivateData->Attributes = PrivateData->Supports;
-
- Protocol->ParentHandle = HostBridgeHandle;
-
- Protocol->PollMem = RootBridgeIoPollMem;
- Protocol->PollIo = RootBridgeIoPollIo;
-
- Protocol->Mem.Read = RootBridgeIoMemRead;
- Protocol->Mem.Write = RootBridgeIoMemWrite;
-
- Protocol->Io.Read = RootBridgeIoIoRead;
- Protocol->Io.Write = RootBridgeIoIoWrite;
-
- Protocol->CopyMem = RootBridgeIoCopyMem;
-
- Protocol->Pci.Read = RootBridgeIoPciRead;
- Protocol->Pci.Write = RootBridgeIoPciWrite;
-
- Protocol->Map = RootBridgeIoMap;
- Protocol->Unmap = RootBridgeIoUnmap;
-
- Protocol->AllocateBuffer = RootBridgeIoAllocateBuffer;
- Protocol->FreeBuffer = RootBridgeIoFreeBuffer;
-
- Protocol->Flush = RootBridgeIoFlush;
-
- Protocol->GetAttributes = RootBridgeIoGetAttributes;
- Protocol->SetAttributes = RootBridgeIoSetAttributes;
-
- Protocol->Configuration = RootBridgeIoConfiguration;
-
- Protocol->SegmentNumber = 0;
-
- Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);
- ASSERT_EFI_ERROR (Status);
-
- return EFI_SUCCESS;
-}
-
-/**
- Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
-
- The I/O operations are carried out exactly as requested. The caller is responsible
- for satisfying any alignment and I/O width restrictions that a PI System on a
- platform might require. For example on some platforms, width requests of
- EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
- be handled by the driver.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] OperationType I/O operation type: IO/MMIO/PCI.
- @param[in] Width Signifies the width of the I/O or Memory operation.
- @param[in] Address The base address of the I/O operation.
- @param[in] Count The number of I/O operations to perform. The number of
- bytes moved is Width size * Count, starting at Address.
- @param[in] Buffer For read operations, the destination buffer to store the results.
- For write operations, the source buffer from which to write data.
-
- @retval EFI_SUCCESS The parameters for this request pass the checks.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
- @retval EFI_UNSUPPORTED The address range specified by Address, Width,
- and Count is not valid for this PI system.
-
-**/
-EFI_STATUS
-RootBridgeIoCheckParameter (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN OPERATION_TYPE OperationType,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;
- UINT32 Stride;
- UINT64 Base;
- UINT64 Limit;
-
- //
- // Check to see if Buffer is NULL
- //
- if (Buffer == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Check to see if Width is in the valid range
- //
- if ((UINT32)Width >= EfiPciWidthMaximum) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // For FIFO type, the target address won't increase during the access,
- // so treat Count as 1
- //
- if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
- Count = 1;
- }
-
- //
- // Check to see if Width is in the valid range for I/O Port operations
- //
- Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
- if ((OperationType != MemOperation) && (Width == EfiPciWidthUint64)) {
- ASSERT (FALSE);
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Check to see if Address is aligned
- //
- Stride = mInStride[Width];
- if ((Address & (UINT64)(Stride - 1)) != 0) {
- return EFI_UNSUPPORTED;
- }
-
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
-
- //
- // Check to see if any address associated with this transfer exceeds the maximum
- // allowed address. The maximum address implied by the parameters passed in is
- // Address + Size * Count. If the following condition is met, then the transfer
- // is not supported.
- //
- // Address + Size * Count > Limit + 1
- //
- // Since Limit can be the maximum integer value supported by the CPU and Count
- // can also be the maximum integer value supported by the CPU, this range
- // check must be adjusted to avoid all oveflow conditions.
- //
- if (OperationType == IoOperation) {
- Base = PrivateData->IoBase;
- Limit = PrivateData->IoLimit;
- } else if (OperationType == MemOperation) {
- Base = PrivateData->MemBase;
- Limit = PrivateData->MemLimit;
- } else {
- PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
- if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) {
- return EFI_INVALID_PARAMETER;
- }
-
- if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {
- return EFI_INVALID_PARAMETER;
- }
-
- if (PciRbAddr->ExtendedRegister != 0) {
- Address = PciRbAddr->ExtendedRegister;
- } else {
- Address = PciRbAddr->Register;
- }
- Base = 0;
- Limit = MAX_PCI_REG_ADDRESS;
- }
-
- if (Limit < Address) {
- return EFI_INVALID_PARAMETER;
- }
-
- if (Address < Base) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Base <= Address <= Limit
- //
- if (Address == 0 && Limit == MAX_UINT64) {
- //
- // 2^64 bytes are valid to transfer. With Stride == 1, that's simply
- // impossible to reach in Count; with Stride in {2, 4, 8}, we can divide
- // both 2^64 and Stride with 2.
- //
- if (Stride > 1 && Count > DivU64x32 (BIT63, Stride / 2)) {
- return EFI_UNSUPPORTED;
- }
- } else {
- //
- // (Limit - Address) does not wrap, and it is smaller than MAX_UINT64.
- //
- if (Count > DivU64x32 (Limit - Address + 1, Stride)) {
- return EFI_UNSUPPORTED;
- }
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Internal help function for read and write memory space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Write Switch value for Read or Write.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
- @param[in] Count The number of PCI configuration operations to perform. Bytes
- moved is Width size * Count, starting at Address.
- @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-RootBridgeIoMemRW (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN BOOLEAN Write,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN OUT VOID *Buffer
- )
-{
- EFI_STATUS Status;
- UINT8 InStride;
- UINT8 OutStride;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
- UINT8 *Uint8Buffer;
-
- Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
- for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
- if (Write) {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- MmioWrite8 ((UINTN)Address, *Uint8Buffer);
- break;
- case EfiPciWidthUint16:
- MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
- break;
- case EfiPciWidthUint32:
- MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
- break;
- case EfiPciWidthUint64:
- MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
- break;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- } else {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- *Uint8Buffer = MmioRead8 ((UINTN)Address);
- break;
- case EfiPciWidthUint16:
- *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
- break;
- case EfiPciWidthUint32:
- *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
- break;
- case EfiPciWidthUint64:
- *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
- break;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- }
- }
- return EFI_SUCCESS;
-}
-
-/**
- Internal help function for read and write IO space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Write Switch value for Read or Write.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
- @param[in] Count The number of PCI configuration operations to perform. Bytes
- moved is Width size * Count, starting at Address.
- @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-RootBridgeIoIoRW (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN BOOLEAN Write,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN OUT VOID *Buffer
- )
-{
- EFI_STATUS Status;
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
- UINT8 InStride;
- UINT8 OutStride;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
- UINT8 *Uint8Buffer;
-
- Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
- //
- // The addition below is performed in UINT64 modular arithmetic, in
- // accordance with the definition of PcdPciIoTranslation in
- // "ArmPlatformPkg.dec". Meaning, the addition below may in fact *decrease*
- // Address, implementing a negative offset translation.
- //
- Address += PrivateData->IoTranslation;
-
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
-
- for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
- if (Write) {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- MmioWrite8 ((UINTN)Address, *Uint8Buffer);
- break;
- case EfiPciWidthUint16:
- MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
- break;
- case EfiPciWidthUint32:
- MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
- break;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- } else {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- *Uint8Buffer = MmioRead8 ((UINTN)Address);
- break;
- case EfiPciWidthUint16:
- *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
- break;
- case EfiPciWidthUint32:
- *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
- break;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- }
- }
- return EFI_SUCCESS;
-}
-
-/**
- Internal help function for read and write PCI configuration space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Write Switch value for Read or Write.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
- @param[in] Count The number of PCI configuration operations to perform. Bytes
- moved is Width size * Count, starting at Address.
- @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-RootBridgeIoPciRW (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN BOOLEAN Write,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN OUT VOID *Buffer
- )
-{
- EFI_STATUS Status;
- UINT8 InStride;
- UINT8 OutStride;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
- UINT8 *Uint8Buffer;
- EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;
- UINTN PcieRegAddr;
-
- Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
-
- PcieRegAddr = (UINTN) PCI_LIB_ADDRESS (
- PciRbAddr->Bus,
- PciRbAddr->Device,
- PciRbAddr->Function,
- (PciRbAddr->ExtendedRegister != 0) ? \
- PciRbAddr->ExtendedRegister :
- PciRbAddr->Register
- );
-
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
- for (Uint8Buffer = Buffer; Count > 0; PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {
- if (Write) {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- PciWrite8 (PcieRegAddr, *Uint8Buffer);
- break;
- case EfiPciWidthUint16:
- PciWrite16 (PcieRegAddr, *((UINT16 *)Uint8Buffer));
- break;
- case EfiPciWidthUint32:
- PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer));
- break;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- } else {
- switch (OperationWidth) {
- case EfiPciWidthUint8:
- *Uint8Buffer = PciRead8 (PcieRegAddr);
- break;
- case EfiPciWidthUint16:
- *((UINT16 *)Uint8Buffer) = PciRead16 (PcieRegAddr);
- break;
- case EfiPciWidthUint32:
- *((UINT32 *)Uint8Buffer) = PciRead32 (PcieRegAddr);
- break;
- default:
- //
- // The RootBridgeIoCheckParameter call above will ensure that this
- // path is not taken.
- //
- ASSERT (FALSE);
- break;
- }
- }
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Polls an address in memory mapped I/O space until an exit condition is met, or
- a timeout occurs.
-
- This function provides a standard way to poll a PCI memory location. A PCI memory read
- operation is performed at the PCI memory address specified by Address for the width specified
- by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
- read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
- Mask) is equal to Value.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] Address The base address of the memory operations. The caller is
- responsible for aligning Address if required.
- @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
- are ignored. The bits in the bytes below Width which are zero in
- Mask are ignored when polling the memory address.
- @param[in] Value The comparison value used for the polling exit criteria.
- @param[in] Delay The number of 100 ns units to poll. Note that timer available may
- be of poorer granularity.
- @param[out] Result Pointer to the last value read from the memory location.
-
- @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
- @retval EFI_INVALID_PARAMETER Width is invalid.
- @retval EFI_INVALID_PARAMETER Result is NULL.
- @retval EFI_TIMEOUT Delay expired before a match occurred.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPollMem (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINT64 Mask,
- IN UINT64 Value,
- IN UINT64 Delay,
- OUT UINT64 *Result
- )
-{
- EFI_STATUS Status;
- UINT64 NumberOfTicks;
- UINT32 Remainder;
-
- if (Result == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- if ((UINT32)Width > EfiPciWidthUint64) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // No matter what, always do a single poll.
- //
- Status = This->Mem.Read (This, Width, Address, 1, Result);
- if (EFI_ERROR (Status)) {
- return Status;
- }
- if ((*Result & Mask) == Value) {
- return EFI_SUCCESS;
- }
-
- if (Delay == 0) {
- return EFI_SUCCESS;
-
- } else {
-
- //
- // Determine the proper # of metronome ticks to wait for polling the
- // location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
- // The "+1" to account for the possibility of the first tick being short
- // because we started in the middle of a tick.
- //
- // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
- // protocol definition is updated.
- //
- NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);
- if (Remainder != 0) {
- NumberOfTicks += 1;
- }
- NumberOfTicks += 1;
-
- while (NumberOfTicks != 0) {
-
- mMetronome->WaitForTick (mMetronome, 1);
-
- Status = This->Mem.Read (This, Width, Address, 1, Result);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- if ((*Result & Mask) == Value) {
- return EFI_SUCCESS;
- }
-
- NumberOfTicks -= 1;
- }
- }
- return EFI_TIMEOUT;
-}
-
-/**
- Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
- satisfied or after a defined duration.
-
- This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
- performed at the PCI I/O address specified by Address for the width specified by Width.
- The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
- repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
- to Value.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the I/O operations.
- @param[in] Address The base address of the I/O operations. The caller is responsible
- for aligning Address if required.
- @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
- are ignored. The bits in the bytes below Width which are zero in
- Mask are ignored when polling the I/O address.
- @param[in] Value The comparison value used for the polling exit criteria.
- @param[in] Delay The number of 100 ns units to poll. Note that timer available may
- be of poorer granularity.
- @param[out] Result Pointer to the last value read from the memory location.
-
- @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
- @retval EFI_INVALID_PARAMETER Width is invalid.
- @retval EFI_INVALID_PARAMETER Result is NULL.
- @retval EFI_TIMEOUT Delay expired before a match occurred.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPollIo (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINT64 Mask,
- IN UINT64 Value,
- IN UINT64 Delay,
- OUT UINT64 *Result
- )
-{
- EFI_STATUS Status;
- UINT64 NumberOfTicks;
- UINT32 Remainder;
-
- //
- // No matter what, always do a single poll.
- //
-
- if (Result == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- if ((UINT32)Width > EfiPciWidthUint64) {
- return EFI_INVALID_PARAMETER;
- }
-
- Status = This->Io.Read (This, Width, Address, 1, Result);
- if (EFI_ERROR (Status)) {
- return Status;
- }
- if ((*Result & Mask) == Value) {
- return EFI_SUCCESS;
- }
-
- if (Delay == 0) {
- return EFI_SUCCESS;
-
- } else {
-
- //
- // Determine the proper # of metronome ticks to wait for polling the
- // location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
- // The "+1" to account for the possibility of the first tick being short
- // because we started in the middle of a tick.
- //
- NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod, &Remainder);
- if (Remainder != 0) {
- NumberOfTicks += 1;
- }
- NumberOfTicks += 1;
-
- while (NumberOfTicks != 0) {
-
- mMetronome->WaitForTick (mMetronome, 1);
-
- Status = This->Io.Read (This, Width, Address, 1, Result);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- if ((*Result & Mask) == Value) {
- return EFI_SUCCESS;
- }
-
- NumberOfTicks -= 1;
- }
- }
- return EFI_TIMEOUT;
-}
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
-
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
- registers in the PCI root bridge memory space.
- The memory operations are carried out exactly as requested. The caller is responsible for satisfying
- any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operation.
- @param[in] Address The base address of the memory operation. The caller is
- responsible for aligning the Address if required.
- @param[in] Count The number of memory operations to perform. Bytes moved is
- Width size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoMemRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);
-}
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
-
- The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
- registers in the PCI root bridge memory space.
- The memory operations are carried out exactly as requested. The caller is responsible for satisfying
- any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operation.
- @param[in] Address The base address of the memory operation. The caller is
- responsible for aligning the Address if required.
- @param[in] Count The number of memory operations to perform. Bytes moved is
- Width size * Count, starting at Address.
- @param[in] Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoMemWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);
-}
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] Address The base address of the I/O operation. The caller is responsible for
- aligning the Address if required.
- @param[in] Count The number of I/O operations to perform. Bytes moved is Width
- size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoIoRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);
-}
-
-/**
- Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] Address The base address of the I/O operation. The caller is responsible for
- aligning the Address if required.
- @param[in] Count The number of I/O operations to perform. Bytes moved is Width
- size * Count, starting at Address.
- @param[in] Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoIoWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);
-}
-
-/**
- Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
- root bridge memory space.
-
- The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
- space to another region of PCI root bridge memory space. This is especially useful for video scroll
- operation on a memory mapped video buffer.
- The memory operations are carried out exactly as requested. The caller is responsible for satisfying
- any alignment and memory width restrictions that a PCI root bridge on a platform might require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] DestAddress The destination address of the memory operation. The caller is
- responsible for aligning the DestAddress if required.
- @param[in] SrcAddress The source address of the memory operation. The caller is
- responsible for aligning the SrcAddress if required.
- @param[in] Count The number of memory operations to perform. Bytes moved is
- Width size * Count, starting at DestAddress and SrcAddress.
-
- @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoCopyMem (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 DestAddress,
- IN UINT64 SrcAddress,
- IN UINTN Count
- )
-{
- EFI_STATUS Status;
- BOOLEAN Direction;
- UINTN Stride;
- UINTN Index;
- UINT64 Result;
-
- if ((UINT32)Width > EfiPciWidthUint64) {
- return EFI_INVALID_PARAMETER;
- }
-
- if (DestAddress == SrcAddress) {
- return EFI_SUCCESS;
- }
-
- Stride = (UINTN)(1 << Width);
-
- Direction = TRUE;
- if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {
- Direction = FALSE;
- SrcAddress = SrcAddress + (Count-1) * Stride;
- DestAddress = DestAddress + (Count-1) * Stride;
- }
-
- for (Index = 0;Index < Count;Index++) {
- Status = RootBridgeIoMemRead (
- This,
- Width,
- SrcAddress,
- 1,
- &Result
- );
- if (EFI_ERROR (Status)) {
- return Status;
- }
- Status = RootBridgeIoMemWrite (
- This,
- Width,
- DestAddress,
- 1,
- &Result
- );
- if (EFI_ERROR (Status)) {
- return Status;
- }
- if (Direction) {
- SrcAddress += Stride;
- DestAddress += Stride;
- } else {
- SrcAddress -= Stride;
- DestAddress -= Stride;
- }
- }
- return EFI_SUCCESS;
-}
-
-/**
- Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
-
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
- registers for a PCI controller.
- The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
- any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
- require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] Address The address within the PCI configuration space for the PCI controller.
- @param[in] Count The number of PCI configuration operations to perform. Bytes
- moved is Width size * Count, starting at Address.
- @param[out] Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPciRead (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);
-}
-
-/**
- Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
-
- The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
- registers for a PCI controller.
- The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
- any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
- require.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Width Signifies the width of the memory operations.
- @param[in] Address The address within the PCI configuration space for the PCI controller.
- @param[in] Count The number of PCI configuration operations to perform. Bytes
- moved is Width size * Count, starting at Address.
- @param[in] Buffer For read operations, the destination buffer to store the results. For
- write operations, the source buffer to write data from.
-
- @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
- @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
- @retval EFI_INVALID_PARAMETER Buffer is NULL.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoPciWrite (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Address,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
-}
-
-/**
- Provides the PCI controller-specific addresses required to access system memory from a
- DMA bus master.
-
- The Map() function provides the PCI controller specific addresses needed to access system
- memory. This function is used to map system memory for PCI bus master DMA accesses.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Operation Indicates if the bus master is going to read or write to system memory.
- @param[in] HostAddress The system memory address to map to the PCI controller.
- @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
- @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
- to access the system memory's HostAddress.
- @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
-
- @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
- @retval EFI_INVALID_PARAMETER Operation is invalid.
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.
- @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
- @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
- @retval EFI_INVALID_PARAMETER Mapping is NULL.
- @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
- @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
- @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoMap (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
- IN VOID *HostAddress,
- IN OUT UINTN *NumberOfBytes,
- OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
- OUT VOID **Mapping
- )
-{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS PhysicalAddress;
- MAP_INFO *MapInfo;
-
- if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Initialize the return values to their defaults
- //
- *Mapping = NULL;
-
- //
- // Make sure that Operation is valid
- //
- if ((UINT32)Operation >= EfiPciOperationMaximum) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Most PCAT like chipsets can not handle performing DMA above 4GB.
- // If any part of the DMA transfer being mapped is above 4GB, then
- // map the DMA transfer to a buffer below 4GB.
- //
- PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;
- if ((PhysicalAddress + *NumberOfBytes) > 0x100000000ULL) {
-
- //
- // Common Buffer operations can not be remapped. If the common buffer
- // if above 4GB, then it is not possible to generate a mapping, so return
- // an error.
- //
- if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) {
- return EFI_UNSUPPORTED;
- }
-
- //
- // Allocate a MAP_INFO structure to remember the mapping when Unmap() is
- // called later.
- //
- Status = gBS->AllocatePool (
- EfiBootServicesData,
- sizeof(MAP_INFO),
- (VOID **)&MapInfo
- );
- if (EFI_ERROR (Status)) {
- *NumberOfBytes = 0;
- return Status;
- }
-
- //
- // Return a pointer to the MAP_INFO structure in Mapping
- //
- *Mapping = MapInfo;
-
- //
- // Initialize the MAP_INFO structure
- //
- MapInfo->Operation = Operation;
- MapInfo->NumberOfBytes = *NumberOfBytes;
- MapInfo->NumberOfPages = EFI_SIZE_TO_PAGES(*NumberOfBytes);
- MapInfo->HostAddress = PhysicalAddress;
- MapInfo->MappedHostAddress = 0x00000000ffffffff;
-
- //
- // Allocate a buffer below 4GB to map the transfer to.
- //
- Status = gBS->AllocatePages (
- AllocateMaxAddress,
- EfiBootServicesData,
- MapInfo->NumberOfPages,
- &MapInfo->MappedHostAddress
- );
- if (EFI_ERROR (Status)) {
- gBS->FreePool (MapInfo);
- *NumberOfBytes = 0;
- return Status;
- }
-
- //
- // If this is a read operation from the Bus Master's point of view,
- // then copy the contents of the real buffer into the mapped buffer
- // so the Bus Master can read the contents of the real buffer.
- //
- if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) {
- CopyMem (
- (VOID *)(UINTN)MapInfo->MappedHostAddress,
- (VOID *)(UINTN)MapInfo->HostAddress,
- MapInfo->NumberOfBytes
- );
- }
-
- //
- // The DeviceAddress is the address of the maped buffer below 4GB
- //
- *DeviceAddress = MapInfo->MappedHostAddress;
- } else {
- //
- // The transfer is below 4GB, so the DeviceAddress is simply the HostAddress
- //
- *DeviceAddress = PhysicalAddress;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Completes the Map() operation and releases any corresponding resources.
-
- The Unmap() function completes the Map() operation and releases any corresponding resources.
- If the operation was an EfiPciOperationBusMasterWrite or
- EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
- Any resources used for the mapping are freed.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Mapping The mapping value returned from Map().
-
- @retval EFI_SUCCESS The range was unmapped.
- @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
- @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoUnmap (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN VOID *Mapping
- )
-{
- MAP_INFO *MapInfo;
-
- //
- // See if the Map() operation associated with this Unmap() required a mapping buffer.
- // If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.
- //
- if (Mapping != NULL) {
- //
- // Get the MAP_INFO structure from Mapping
- //
- MapInfo = (MAP_INFO *)Mapping;
-
- //
- // If this is a write operation from the Bus Master's point of view,
- // then copy the contents of the mapped buffer into the real buffer
- // so the processor can read the contents of the real buffer.
- //
- if (MapInfo->Operation == EfiPciOperationBusMasterWrite || MapInfo->Operation == EfiPciOperationBusMasterWrite64) {
- CopyMem (
- (VOID *)(UINTN)MapInfo->HostAddress,
- (VOID *)(UINTN)MapInfo->MappedHostAddress,
- MapInfo->NumberOfBytes
- );
- }
-
- //
- // Free the mapped buffer and the MAP_INFO structure.
- //
- gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);
- gBS->FreePool (Mapping);
- }
- return EFI_SUCCESS;
-}
-
-/**
- Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
- EfiPciOperationBusMasterCommonBuffer64 mapping.
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param Type This parameter is not used and must be ignored.
- @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
- @param Pages The number of pages to allocate.
- @param HostAddress A pointer to store the base system memory address of the allocated range.
- @param Attributes The requested bit mask of attributes for the allocated range. Only
- the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
- and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
-
- @retval EFI_SUCCESS The requested memory pages were allocated.
- @retval EFI_INVALID_PARAMETER MemoryType is invalid.
- @retval EFI_INVALID_PARAMETER HostAddress is NULL.
- @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
- @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoAllocateBuffer (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN EFI_ALLOCATE_TYPE Type,
- IN EFI_MEMORY_TYPE MemoryType,
- IN UINTN Pages,
- OUT VOID **HostAddress,
- IN UINT64 Attributes
- )
-{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS PhysicalAddress;
-
- //
- // Validate Attributes
- //
- if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {
- return EFI_UNSUPPORTED;
- }
-
- //
- // Check for invalid inputs
- //
- if (HostAddress == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
- //
- if (MemoryType != EfiBootServicesData && MemoryType != EfiRuntimeServicesData) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Limit allocations to memory below 4GB
- //
- PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(0xffffffff);
-
- Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages, &PhysicalAddress);
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- *HostAddress = (VOID *)(UINTN)PhysicalAddress;
-
- return EFI_SUCCESS;
-}
-
-/**
- Frees memory that was allocated with AllocateBuffer().
-
- The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param Pages The number of pages to free.
- @param HostAddress The base system memory address of the allocated range.
-
- @retval EFI_SUCCESS The requested memory pages were freed.
- @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
- was not allocated with AllocateBuffer().
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoFreeBuffer (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN UINTN Pages,
- OUT VOID *HostAddress
- )
-{
- return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);
-}
-
-/**
- Flushes all PCI posted write transactions from a PCI host bridge to system memory.
-
- The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
- memory. Posted write transactions are generated by PCI bus masters when they perform write
- transactions to target addresses in system memory.
- This function does not flush posted write transactions from any PCI bridges. A PCI controller
- specific action must be taken to guarantee that the posted write transactions have been flushed from
- the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
- a PCI read transaction from the PCI controller prior to calling Flush().
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-
- @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
- bridge to system memory.
- @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
- host bridge due to a hardware error.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoFlush (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
- )
-{
- //
- // not supported yet
- //
- return EFI_SUCCESS;
-}
-
-/**
- Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
- attributes that a PCI root bridge is currently using.
-
- The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
- and the mask of attributes that the PCI root bridge is currently using.
-
- @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param Supported A pointer to the mask of attributes that this PCI root bridge
- supports setting with SetAttributes().
- @param Attributes A pointer to the mask of attributes that this PCI root bridge is
- currently using.
-
- @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root
- bridge supports is returned in Supports. If Attributes is
- not NULL, then the attributes that the PCI root bridge is currently
- using is returned in Attributes.
- @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoGetAttributes (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- OUT UINT64 *Supported,
- OUT UINT64 *Attributes
- )
-{
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
-
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
-
- if (Attributes == NULL && Supported == NULL) {
- return EFI_INVALID_PARAMETER;
- }
-
- //
- // Set the return value for Supported and Attributes
- //
- if (Supported != NULL) {
- *Supported = PrivateData->Supports;
- }
-
- if (Attributes != NULL) {
- *Attributes = PrivateData->Attributes;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Sets attributes for a resource range on a PCI root bridge.
-
- The SetAttributes() function sets the attributes specified in Attributes for the PCI root
- bridge on the resource range specified by ResourceBase and ResourceLength. Since the
- granularity of setting these attributes may vary from resource type to resource type, and from
- platform to platform, the actual resource range and the one passed in by the caller may differ. As a
- result, this function may set the attributes specified by Attributes on a larger resource range
- than the caller requested. The actual range is returned in ResourceBase and
- ResourceLength. The caller is responsible for verifying that the actual range for which the
- attributes were set is acceptable.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[in] Attributes The mask of attributes to set. If the attribute bit
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
- MEMORY_DISABLE is set, then the resource range is specified by
- ResourceBase and ResourceLength. If
- MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
- MEMORY_DISABLE are not set, then ResourceBase and
- ResourceLength are ignored, and may be NULL.
- @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified
- by the attributes specified by Attributes.
- @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the
- attributes specified by Attributes.
-
- @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
- @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoSetAttributes (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- IN UINT64 Attributes,
- IN OUT UINT64 *ResourceBase,
- IN OUT UINT64 *ResourceLength
- )
-{
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
-
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
-
- if (Attributes != 0) {
- if ((Attributes & (~(PrivateData->Supports))) != 0) {
- return EFI_UNSUPPORTED;
- }
- }
-
- //
- // This is a generic driver for a PC-AT class system. It does not have any
- // chipset specific knowlegde, so none of the attributes can be set or
- // cleared. Any attempt to set attribute that are already set will succeed,
- // and any attempt to set an attribute that is not supported will fail.
- //
- if (Attributes & (~PrivateData->Attributes)) {
- return EFI_UNSUPPORTED;
- }
-
- return EFI_SUCCESS;
-}
-
-/**
- Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
- resource descriptors.
-
- There are only two resource descriptor types from the ACPI Specification that may be used to
- describe the current resources allocated to a PCI root bridge. These are the QWORD Address
- Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
- QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
- or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
- Address Space Descriptors followed by an End Tag.
-
- @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
- @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the
- current configuration of this PCI root bridge. The storage for the
- ACPI 2.0 resource descriptors is allocated by this function. The
- caller must treat the return buffer as read-only data, and the buffer
- must not be freed by the caller.
-
- @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
- @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
- @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
-
-**/
-EFI_STATUS
-EFIAPI
-RootBridgeIoConfiguration (
- IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
- OUT VOID **Resources
- )
-{
- PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
- UINTN Index;
-
- PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
-
- for (Index = 0; Index < TypeMax; Index++) {
- if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {
- Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
- Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;
- Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length;
- }
- }
-
- *Resources = &Configuration;
- return EFI_SUCCESS;
-}
-
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v2 3/6] ArmVirtPkg: implement FdtPciHostBridgeLib
2016-08-31 17:59 ` [PATCH v2 3/6] ArmVirtPkg: implement FdtPciHostBridgeLib Ard Biesheuvel
@ 2016-09-02 10:15 ` Laszlo Ersek
0 siblings, 0 replies; 17+ messages in thread
From: Laszlo Ersek @ 2016-09-02 10:15 UTC (permalink / raw)
To: Ard Biesheuvel, edk2-devel; +Cc: leif.lindholm
On 08/31/16 19:59, Ard Biesheuvel wrote:
> Implement PciHostBridgeLib for DT platforms that expose a PCI root bridge
> via a pci-host-ecam-generic DT node. The DT parsing logic is copied from
> the PciHostBridgeDxe implementation in ArmVirtPkg, with the one notable
> difference that we don't set the various legacy PCI attributes for IDE
> and VGA I/O ranges.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65
> ---
> ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 400 ++++++++++++++++++++
> ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf | 56 +++
> 2 files changed, 456 insertions(+)
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Thanks
Laszlo
> diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> new file mode 100644
> index 000000000000..c2aa4a339c19
> --- /dev/null
> +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> @@ -0,0 +1,400 @@
> +/** @file
> + PCI Host Bridge Library instance for pci-ecam-generic DT nodes
> +
> + Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> + IMPLIED.
> +
> +**/
> +#include <PiDxe.h>
> +#include <Library/PciHostBridgeLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +
> +#include <Protocol/FdtClient.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +#include <Protocol/PciHostBridgeResourceAllocation.h>
> +
> +#pragma pack(1)
> +typedef struct {
> + ACPI_HID_DEVICE_PATH AcpiDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
> +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
> +#pragma pack ()
> +
> +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
> + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
> + }
> + },
> + EISA_PNP_ID(0x0A08), // PCI Express
> + 0
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> +};
> +
> +GLOBAL_REMOVE_IF_UNREFERENCED
> +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
> + L"Mem", L"I/O", L"Bus"
> +};
> +
> +//
> +// We expect the "ranges" property of "pci-host-ecam-generic" to consist of
> +// records like this.
> +//
> +#pragma pack (1)
> +typedef struct {
> + UINT32 Type;
> + UINT64 ChildBase;
> + UINT64 CpuBase;
> + UINT64 Size;
> +} DTB_PCI_HOST_RANGE_RECORD;
> +#pragma pack ()
> +
> +#define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31
> +#define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
> +#define DTB_PCI_HOST_RANGE_ALIASED BIT29
> +#define DTB_PCI_HOST_RANGE_MMIO32 BIT25
> +#define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)
> +#define DTB_PCI_HOST_RANGE_IO BIT24
> +#define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
> +
> +STATIC
> +EFI_STATUS
> +ProcessPciHost (
> + OUT UINT64 *IoBase,
> + OUT UINT64 *IoSize,
> + OUT UINT64 *MmioBase,
> + OUT UINT64 *MmioSize,
> + OUT UINT32 *BusMin,
> + OUT UINT32 *BusMax
> + )
> +{
> + FDT_CLIENT_PROTOCOL *FdtClient;
> + INT32 Node;
> + UINT64 ConfigBase, ConfigSize;
> + CONST VOID *Prop;
> + UINT32 Len;
> + UINT32 RecordIdx;
> + EFI_STATUS Status;
> + UINT64 IoTranslation;
> + UINT64 MmioTranslation;
> +
> + //
> + // The following output arguments are initialized only in
> + // order to suppress '-Werror=maybe-uninitialized' warnings
> + // *incorrectly* emitted by some gcc versions.
> + //
> + *IoBase = 0;
> + *MmioBase = 0;
> + *BusMin = 0;
> + *BusMax = 0;
> +
> + //
> + // *IoSize, *MmioSize and IoTranslation are initialized to zero because the
> + // logic below requires it. However, since they are also affected by the issue
> + // reported above, they are initialized early.
> + //
> + *IoSize = 0;
> + *MmioSize = 0;
> + IoTranslation = 0;
> +
> + Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL,
> + (VOID **)&FdtClient);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = FdtClient->FindCompatibleNode (FdtClient, "pci-host-ecam-generic",
> + &Node);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((EFI_D_INFO,
> + "%a: No 'pci-host-ecam-generic' compatible DT node found\n",
> + __FUNCTION__));
> + return EFI_NOT_FOUND;
> + }
> +
> + DEBUG_CODE (
> + INT32 Tmp;
> +
> + //
> + // A DT can legally describe multiple PCI host bridges, but we are not
> + // equipped to deal with that. So assert that there is only one.
> + //
> + Status = FdtClient->FindNextCompatibleNode (FdtClient,
> + "pci-host-ecam-generic", Node, &Tmp);
> + ASSERT (Status == EFI_NOT_FOUND);
> + );
> +
> + Status = FdtClient->GetNodeProperty (FdtClient, Node, "reg", &Prop, &Len);
> + if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT64)) {
> + DEBUG ((EFI_D_ERROR, "%a: 'reg' property not found or invalid\n",
> + __FUNCTION__));
> + return EFI_PROTOCOL_ERROR;
> + }
> +
> + //
> + // Fetch the ECAM window.
> + //
> + ConfigBase = SwapBytes64 (((CONST UINT64 *)Prop)[0]);
> + ConfigSize = SwapBytes64 (((CONST UINT64 *)Prop)[1]);
> +
> + //
> + // Fetch the bus range (note: inclusive).
> + //
> + Status = FdtClient->GetNodeProperty (FdtClient, Node, "bus-range", &Prop,
> + &Len);
> + if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT32)) {
> + DEBUG ((EFI_D_ERROR, "%a: 'bus-range' not found or invalid\n",
> + __FUNCTION__));
> + return EFI_PROTOCOL_ERROR;
> + }
> + *BusMin = SwapBytes32 (((CONST UINT32 *)Prop)[0]);
> + *BusMax = SwapBytes32 (((CONST UINT32 *)Prop)[1]);
> +
> + //
> + // Sanity check: the config space must accommodate all 4K register bytes of
> + // all 8 functions of all 32 devices of all buses.
> + //
> + if (*BusMax < *BusMin || *BusMax - *BusMin == MAX_UINT32 ||
> + DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < *BusMax - *BusMin + 1) {
> + DEBUG ((EFI_D_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n",
> + __FUNCTION__));
> + return EFI_PROTOCOL_ERROR;
> + }
> +
> + //
> + // Iterate over "ranges".
> + //
> + Status = FdtClient->GetNodeProperty (FdtClient, Node, "ranges", &Prop, &Len);
> + if (EFI_ERROR (Status) || Len == 0 ||
> + Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) {
> + DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));
> + return EFI_PROTOCOL_ERROR;
> + }
> +
> + for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);
> + ++RecordIdx) {
> + CONST DTB_PCI_HOST_RANGE_RECORD *Record;
> +
> + Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;
> + switch (SwapBytes32 (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) {
> + case DTB_PCI_HOST_RANGE_IO:
> + *IoBase = SwapBytes64 (Record->ChildBase);
> + *IoSize = SwapBytes64 (Record->Size);
> + IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;
> +
> + ASSERT (PcdGet64 (PcdPciIoTranslation) == IoTranslation);
> + break;
> +
> + case DTB_PCI_HOST_RANGE_MMIO32:
> + *MmioBase = SwapBytes64 (Record->ChildBase);
> + *MmioSize = SwapBytes64 (Record->Size);
> + MmioTranslation = SwapBytes64 (Record->CpuBase) - *MmioBase;
> +
> + if (*MmioBase > MAX_UINT32 || *MmioSize > MAX_UINT32 ||
> + *MmioBase + *MmioSize > SIZE_4GB) {
> + DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));
> + return EFI_PROTOCOL_ERROR;
> + }
> +
> + ASSERT (PcdGet64 (PcdPciMmio32Translation) == MmioTranslation);
> +
> + if (MmioTranslation != 0) {
> + DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation "
> + "0x%Lx\n", __FUNCTION__, MmioTranslation));
> + return EFI_UNSUPPORTED;
> + }
> +
> + break;
> + }
> + }
> + if (*IoSize == 0 || *MmioSize == 0) {
> + DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__,
> + (*IoSize == 0) ? "IO" : "MMIO32"));
> + return EFI_PROTOCOL_ERROR;
> + }
> +
> + //
> + // The dynamic PCD PcdPciExpressBaseAddress should have already been set,
> + // and should match the value we found in the DT node.
> + //
> + ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase);
> +
> + DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "
> + "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x0\n", __FUNCTION__, ConfigBase,
> + ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, IoTranslation, *MmioBase,
> + *MmioSize));
> + return EFI_SUCCESS;
> +}
> +
> +STATIC PCI_ROOT_BRIDGE mRootBridge;
> +
> +/**
> + Return all the root bridge instances in an array.
> +
> + @param Count Return the count of root bridge instances.
> +
> + @return All the root bridge instances in an array.
> + The array should be passed into PciHostBridgeFreeRootBridges()
> + when it's not used.
> +**/
> +PCI_ROOT_BRIDGE *
> +EFIAPI
> +PciHostBridgeGetRootBridges (
> + UINTN *Count
> + )
> +{
> + UINT64 IoBase, IoSize;
> + UINT64 Mmio32Base, Mmio32Size;
> + UINT32 BusMin, BusMax;
> + EFI_STATUS Status;
> +
> + if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {
> + DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));
> +
> + *Count = 0;
> + return NULL;
> + }
> +
> + Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size, &BusMin,
> + &BusMax);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((EFI_D_ERROR, "%a: failed to discover PCI host bridge: %r\n",
> + __FUNCTION__, Status));
> + *Count = 0;
> + return NULL;
> + }
> +
> + *Count = 1;
> +
> + mRootBridge.Segment = 0;
> + mRootBridge.Supports = EFI_PCI_ATTRIBUTE_ISA_IO_16 |
> + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
> + EFI_PCI_ATTRIBUTE_VGA_IO_16 |
> + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
> + mRootBridge.Attributes = mRootBridge.Supports;
> +
> + mRootBridge.DmaAbove4G = TRUE;
> + mRootBridge.NoExtendedConfigSpace = FALSE;
> + mRootBridge.ResourceAssigned = FALSE;
> +
> + mRootBridge.AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;
> +
> + mRootBridge.Bus.Base = BusMin;
> + mRootBridge.Bus.Limit = BusMax;
> + mRootBridge.Io.Base = IoBase;
> + mRootBridge.Io.Limit = IoBase + IoSize - 1;
> + mRootBridge.Mem.Base = Mmio32Base;
> + mRootBridge.Mem.Limit = Mmio32Base + Mmio32Size - 1;
> + mRootBridge.MemAbove4G.Base = MAX_UINT64;
> + mRootBridge.MemAbove4G.Limit = 0;
> +
> + //
> + // No separate ranges for prefetchable and non-prefetchable BARs
> + //
> + mRootBridge.PMem.Base = MAX_UINT64;
> + mRootBridge.PMem.Limit = 0;
> + mRootBridge.PMemAbove4G.Base = MAX_UINT64;
> + mRootBridge.PMemAbove4G.Limit = 0;
> +
> + mRootBridge.DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath;
> +
> + return &mRootBridge;
> +}
> +
> +/**
> + Free the root bridge instances array returned from
> + PciHostBridgeGetRootBridges().
> +
> + @param Bridges The root bridge instances array.
> + @param Count The count of the array.
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeFreeRootBridges (
> + PCI_ROOT_BRIDGE *Bridges,
> + UINTN Count
> + )
> +{
> + ASSERT (Count == 1);
> +}
> +
> +/**
> + Inform the platform that the resource conflict happens.
> +
> + @param HostBridgeHandle Handle of the Host Bridge.
> + @param Configuration Pointer to PCI I/O and PCI memory resource
> + descriptors. The Configuration contains the resources
> + for all the root bridges. The resource for each root
> + bridge is terminated with END descriptor and an
> + additional END is appended indicating the end of the
> + entire resources. The resource descriptor field
> + values follow the description in
> + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
> + .SubmitResources().
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeResourceConflict (
> + EFI_HANDLE HostBridgeHandle,
> + VOID *Configuration
> + )
> +{
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
> + UINTN RootBridgeIndex;
> + DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n"));
> +
> + RootBridgeIndex = 0;
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
> + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
> + DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
> + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
> + ASSERT (Descriptor->ResType <
> + (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
> + sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
> + )
> + );
> + DEBUG ((EFI_D_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
> + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
> + Descriptor->AddrLen, Descriptor->AddrRangeMax
> + ));
> + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
> + DEBUG ((EFI_D_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
> + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
> + ((Descriptor->SpecificFlag &
> + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
> + ) != 0) ? L" (Prefetchable)" : L""
> + ));
> + }
> + }
> + //
> + // Skip the END descriptor for root bridge
> + //
> + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
> + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
> + );
> + }
> +}
> diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
> new file mode 100644
> index 000000000000..fc1d37fb3c23
> --- /dev/null
> +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
> @@ -0,0 +1,56 @@
> +## @file
> +# PCI Host Bridge Library instance for pci-ecam-generic DT nodes
> +#
> +# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
> +#
> +# This program and the accompanying materials are licensed and made available
> +# under the terms and conditions of the BSD License which accompanies this
> +# distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php.
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> +# IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = FdtPciHostBridgeLib
> + FILE_GUID = 59fcb139-2558-4cf0-8d7c-ebac499da727
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciHostBridgeLib
> +
> +#
> +# The following information is for reference only and not required by the build
> +# tools.
> +#
> +# VALID_ARCHITECTURES = AARCH64 ARM
> +#
> +
> +[Sources]
> + FdtPciHostBridgeLib.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmVirtPkg/ArmVirtPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> + DevicePathLib
> + MemoryAllocationLib
> + PciPcdProducerLib
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdPciMmio32Translation
> +
> +[Pcd]
> + gArmTokenSpaceGuid.PcdPciIoTranslation
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> +
> +[Depex]
> + gFdtClientProtocolGuid
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 5/6] ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 support
2016-08-31 17:59 ` [PATCH v2 5/6] ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 support Ard Biesheuvel
@ 2016-09-02 10:44 ` Laszlo Ersek
0 siblings, 0 replies; 17+ messages in thread
From: Laszlo Ersek @ 2016-09-02 10:44 UTC (permalink / raw)
To: Ard Biesheuvel, edk2-devel; +Cc: leif.lindholm
On 08/31/16 19:59, Ard Biesheuvel wrote:
> @@ -308,8 +329,21 @@ PciHostBridgeGetRootBridges (
> mRootBridge.Io.Limit = IoBase + IoSize - 1;
> mRootBridge.Mem.Base = Mmio32Base;
> mRootBridge.Mem.Limit = Mmio32Base + Mmio32Size - 1;
> - mRootBridge.MemAbove4G.Base = MAX_UINT64;
> - mRootBridge.MemAbove4G.Limit = 0;
> +
> + if (sizeof (UINTN) == sizeof (UINT64)) {
> + mRootBridge.MemAbove4G.Base = Mmio64Base;
> + mRootBridge.MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1;
> + mRootBridge.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
> + } else {
> + //
> + // UEFI mandates a 1:1 virtual-to-physical mapping, so on a 32-bit
> + // architecture such as ARM, we will not be able to access 64-bit MMIO
> + // BARs unless they are allocated below 4 GB. So ignore the range above
> + // 4 GB in this case.
> + //
> + mRootBridge.MemAbove4G.Base = MAX_UINT64;
> + mRootBridge.MemAbove4G.Limit = 0;
> + }
>
> //
> // No separate ranges for prefetchable and non-prefetchable BARs
Please further restrict the one assignment
mRootBridge.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
(while keeping it in its current location) with the following condition:
if (Mmio64Size > 0) {
mRootBridge.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
}
We should only set this bit if there's actually a 64-bit MMIO aperture.
With that,
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
(No need to repost the series just because of this; you can implement the above on commit.)
Thanks!
Laszlo
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 2/6] ArmVirtPkg/FdtPciPcdProducerLib: add handling of PcdPciIoTranslation
2016-08-31 17:59 ` [PATCH v2 2/6] ArmVirtPkg/FdtPciPcdProducerLib: add handling of PcdPciIoTranslation Ard Biesheuvel
@ 2016-09-02 11:19 ` Laszlo Ersek
0 siblings, 0 replies; 17+ messages in thread
From: Laszlo Ersek @ 2016-09-02 11:19 UTC (permalink / raw)
To: Ard Biesheuvel, edk2-devel; +Cc: leif.lindholm
On 08/31/16 19:59, Ard Biesheuvel wrote:
> + if (!EFI_ERROR (Status) && RegSize == 2 * sizeof(UINT64)) {
Before you commit this patch, please insert a space character between
"sizeof" and "(".
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Please hold on for a little while before committing the series, I'd like
to test it quickly.
Thanks!
Laszlo
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe
2016-08-31 17:59 [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe Ard Biesheuvel
` (5 preceding siblings ...)
2016-08-31 17:59 ` [PATCH v2 6/6] ArmVirtPkg: remove now unused PciHostBridgeDxe Ard Biesheuvel
@ 2016-09-02 13:09 ` Laszlo Ersek
2016-09-02 13:17 ` Laszlo Ersek
2016-09-02 14:58 ` Ard Biesheuvel
6 siblings, 2 replies; 17+ messages in thread
From: Laszlo Ersek @ 2016-09-02 13:09 UTC (permalink / raw)
To: Ard Biesheuvel, edk2-devel; +Cc: leif.lindholm
On 08/31/16 19:59, Ard Biesheuvel wrote:
> Now that Laszlo's virtio-gpu-pci series has removed the last remaining obstacle,
> we can get rid of the special PciHostBridgeDxe implementation in ArmVirtPkg,
> and move to the generic one. On AArch64, this will allow us to perform DMA above
> 4GB without bounce buffering, and use 64-bit MMIO BARs allocated above 4 GB.
>
> Changes since v1:
> - new patch #2 to move the IoTranslation discovery to FdtPciPcdProducerLib,
> which is a cleaner approach since other drivers (i.e., ArmPciCpuIo2Dxe)
> depend on it as well
> - add support for ARM, i.e., disable the 64-bit range in that case, since we
> cannot access 64-bit MMIO BARs if they are allocated there
> - use statically allocated PCI_ROOT_BRIDGE[] array of size 1
> - enable support for ISA and VGA I/O range decoding
> - various other minor fixes based on Laszlo's review comments
> - added ref links and Laszlo's acks where appropriate, i.e., where given and
> where the version of the patch in this series does not deviate substantially
> from the suggested version on which the preliminary ack was based
>
> Patch #1 removes the linux,pci-probe-only override which does more harm than
> good now that we switched to virtio-gpu-pci, which does not expose a raw
> framebuffer.
>
> Patch #2 extends FdtPciPcdProducerLib so that it also sets PcdPciIoTranslation,
> which is required for the FdtPciHostBridgeLib implementation this series
> introduces, but also for ArmPciCpuIo2Dxe, which produces EFI_CPU_IO2_PROTOCOL
> on which the generic PciHostBridgeDxe depends as well.
>
> Patch #3 implements PciHostBridgeLib for platforms exposing a PCI host bridge
> using a pci-host-ecam-generic DT node. The initial version is based on the
> ArmVirtPkg implementation of PciHostBridgeDxe, so it does not support 64-bit
> MMIO BARs allocated above 4 GB, but it does support DMA above 4 GB without
> bounce buffering.
>
> Patch #4 switches to the generic PciHostBridgeDxe, with no change in
> functionality other than support for DMA above 4 GB without bounce buffering.
>
> Patch #5 adds support for allocating 64-bit MMIO BARs above 4 GB.
>
> Patch #6 removes the now obsolete PciHostBridgeDxe from ArmVirtPkg.
>
>
> Ard Biesheuvel (6):
> ArmVirtPkg/PciHostBridgeDxe: don't set linux,pci-probe-only DT
> property
> ArmVirtPkg/FdtPciPcdProducerLib: add handling of PcdPciIoTranslation
> ArmVirtPkg: implement FdtPciHostBridgeLib
> ArmVirtPkg/ArmVirtQemu: switch to generic PciHostBridgeDxe
> ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 support
> ArmVirtPkg: remove now unused PciHostBridgeDxe
>
> ArmVirtPkg/ArmVirtQemu.dsc | 10 +-
> ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 3 +-
> ArmVirtPkg/ArmVirtQemuKernel.dsc | 10 +-
> ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 434 ++++
> ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf | 57 +
> ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.c | 108 +-
> ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf | 2 +
> ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c | 1496 --------------
> ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.h | 499 -----
> ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf | 64 -
> ArmVirtPkg/PciHostBridgeDxe/PciRootBridgeIo.c | 2144 --------------------
> 11 files changed, 611 insertions(+), 4216 deletions(-)
> create mode 100644 ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> create mode 100644 ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
> delete mode 100644 ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c
> delete mode 100644 ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.h
> delete mode 100644 ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf
> delete mode 100644 ArmVirtPkg/PciHostBridgeDxe/PciRootBridgeIo.c
>
Test results:
(1) aarch64 TCG on an x86_64 host, using standard VGA (-device VGA) and USB 3 keyboard (-device nec-usb-xhci -device usb-kbd). I tested the display browser, the UEFI shell, and the GRUB menu. Didn't boot an actual OS. (Ain't nobody got time for that using TCG :))
I also checked the ArmVirtQemu debug log, it looks very nice; there was even a 64-bit Mem64 BAR that got allocated high.
(2) aarch64 KVM, using virtio-gpu-pci and USB 2 keyboard and tablet. I actually booted a Fedora 24 guest with this, and in the guest, everything works just fine (display, keyboard, mouse/tablet). Most of the firmware log looks good too.
(2a) However, the USB 2 keyboard is broken while in the firmware (in spite of it working well in the guest OS).
-device ich9-usb-ehci1,multifunction=on,id=ehci,addr=05.0 \
-device ich9-usb-uhci1,multifunction=on,masterbus=ehci.0,firstport=0,addr=05.1 \
-device ich9-usb-uhci2,multifunction=on,masterbus=ehci.0,firstport=2,addr=05.2 \
-device ich9-usb-uhci3,multifunction=on,masterbus=ehci.0,firstport=4,addr=05.3 \
-device usb-kbd,bus=ehci.0 \
-device usb-tablet,bus=ehci.0 \
My QEMU has your commit 5d636e21c44e ("hw/arm/virt: mark the PCIe host controller as DMA coherent in the DT"), but I guess the EHCI driver in edk2 doesn't comply with the "guest drivers should use cacheable accesses as well when running under KVM" part. :(
The following snippet repeats in the log:
EhcClearLegacySupport: called to clear legacy support
processing error - resetting ehci HC
EhcInitHC: failed to enable period schedule
EhcDriverBindingStart: failed to init host controller
EhcCreateUsb2Hc: capability length 32
Interestingly, if I back out your series, then USB2 works in the firmware. I don't understand this, given that my build includes commit 3ef3209d3028 ("ArmVirtPkg: remove PcdKludgeMapPciMmioAsCached") from the master branch!
(2b) Your series does not break virtio-{scsi,blk}-pci though, I verified that.
(3) Another issue I noticed in testing is that the following line from patch #3 ("ArmVirtPkg: implement FdtPciHostBridgeLib"):
+ EISA_PNP_ID(0x0A08), // PCI Express
which I initially thought would be okay actually breaks "OvmfPkg/Library/QemuBootOrderLib". The TranslatePciOfwNodes() function translates OFW devpaths into textual UEFI devpath fragments that start with PciRoot(), not PcieRoot(), and after your patch, these prefixes will no longer match the UEFI devpaths of the actual PCI devices.
So, for this I'll have to go back on my initial approval, and ask you to keep this as 0x0A03. Yes, I know it won't match QEMU's ACPI payload perfectly, but the same is the case with the Q35 x86_64 machine type -- search "hw/i386/acpi-build.c" for the string "PNP0A08" -- and in practice it causes no problems at all.
(4) This is for the longer term, but now that we have 64-bit MMIO aperture, we should include OvmfPkg/IncompatiblePciDeviceSupportDxe in ArmVirtQemu (please see commit 855743f71774). The circumstances described in the commit message now apply to ArmVirtQemu as well, if at least virtio-net-pci is used -- that device has an oprom, and by default that is reason enough for PciBusDxe to degrade the 64-bit MMIO BAR to 32-bit. Including "OvmfPkg/IncompatiblePciDeviceSupportDxe" will prevent this.
I think (3) can be fixed up easily without a repost, and (4) can be addressed with a separate patch, later.
However, I'm completely dumbfounded about (2a). Please do not tell me that we'll have to implement a virtio-input driver... :( I think there must be a mysterious caching difference between "MdeModulePkg/Bus/Pci/PciHostBridgeDxe" and "ArmVirtPkg/PciHostBridgeDxe", even after having removed the "kludge" from the latter!
Maybe it has to do with the IO aperture. The USB1 companion controllers on the EHCI controller have one IO BAR each:
PciBus: Resource Map for Root Bridge PcieRoot(0x0)
Type = Io16; Base = 0x0; Length = 0x1000; Alignment = 0xFFF
[...]
Base = 0x80; Length = 0x20; Alignment = 0x1F; Owner = PCI [00|05|03:20]
Base = 0xA0; Length = 0x20; Alignment = 0x1F; Owner = PCI [00|05|02:20]
Base = 0xC0; Length = 0x20; Alignment = 0x1F; Owner = PCI [00|05|01:20]
[...]
and with your patches applied, accesses to these are now delegated to ArmPciCpuIo2Dxe. Maybe that makes a difference? I'm just guessing. (Again, the virtio-xxxx-pci devices, even forcing them to use IO BARs, with ",disable-modern=on", continue to work fine.)
Since you authored QEMU commit 5d636e21c44e, I reckon (hope!) you have some background on the USB thing... What's your take?
Thanks
Laszlo
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe
2016-09-02 13:09 ` [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe Laszlo Ersek
@ 2016-09-02 13:17 ` Laszlo Ersek
2016-09-02 14:58 ` Ard Biesheuvel
1 sibling, 0 replies; 17+ messages in thread
From: Laszlo Ersek @ 2016-09-02 13:17 UTC (permalink / raw)
To: Ard Biesheuvel, edk2-devel; +Cc: leif.lindholm
On 09/02/16 15:09, Laszlo Ersek wrote:
> (4) This is for the longer term, but now that we have 64-bit MMIO
> aperture, we should include OvmfPkg/IncompatiblePciDeviceSupportDxe
> in ArmVirtQemu (please see commit 855743f71774). The circumstances
> described in the commit message now apply to ArmVirtQemu as well, if
> at least virtio-net-pci is used -- that device has an oprom, and by
> default that is reason enough for PciBusDxe to degrade the 64-bit
> MMIO BAR to 32-bit. Including
> "OvmfPkg/IncompatiblePciDeviceSupportDxe" will prevent this.
BTW, for this, our FdtPciPcdProducerLib should also produce
PcdPciMmio64Size, and it will have to be plugged into
IncompatiblePciDeviceSupportDxe.
Anyway, it definitely qualifies as "far future".
Thanks
Laszlo
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe
2016-09-02 13:09 ` [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe Laszlo Ersek
2016-09-02 13:17 ` Laszlo Ersek
@ 2016-09-02 14:58 ` Ard Biesheuvel
2016-09-02 15:27 ` Laszlo Ersek
1 sibling, 1 reply; 17+ messages in thread
From: Ard Biesheuvel @ 2016-09-02 14:58 UTC (permalink / raw)
To: Laszlo Ersek; +Cc: edk2-devel, leif.lindholm
(on the road atm, will reply in full later)
> On 2 sep. 2016, at 14:09, Laszlo Ersek <lersek@redhat.com> wrote:
>
>> On 08/31/16 19:59, Ard Biesheuvel wrote:
>> Now that Laszlo's virtio-gpu-pci series has removed the last remaining obstacle,
>> we can get rid of the special PciHostBridgeDxe implementation in ArmVirtPkg,
>> and move to the generic one. On AArch64, this will allow us to perform DMA above
>> 4GB without bounce buffering, and use 64-bit MMIO BARs allocated above 4 GB.
>>
>> Changes since v1:
>> - new patch #2 to move the IoTranslation discovery to FdtPciPcdProducerLib,
>> which is a cleaner approach since other drivers (i.e., ArmPciCpuIo2Dxe)
>> depend on it as well
>> - add support for ARM, i.e., disable the 64-bit range in that case, since we
>> cannot access 64-bit MMIO BARs if they are allocated there
>> - use statically allocated PCI_ROOT_BRIDGE[] array of size 1
>> - enable support for ISA and VGA I/O range decoding
>> - various other minor fixes based on Laszlo's review comments
>> - added ref links and Laszlo's acks where appropriate, i.e., where given and
>> where the version of the patch in this series does not deviate substantially
>> from the suggested version on which the preliminary ack was based
>>
>> Patch #1 removes the linux,pci-probe-only override which does more harm than
>> good now that we switched to virtio-gpu-pci, which does not expose a raw
>> framebuffer.
>>
>> Patch #2 extends FdtPciPcdProducerLib so that it also sets PcdPciIoTranslation,
>> which is required for the FdtPciHostBridgeLib implementation this series
>> introduces, but also for ArmPciCpuIo2Dxe, which produces EFI_CPU_IO2_PROTOCOL
>> on which the generic PciHostBridgeDxe depends as well.
>>
>> Patch #3 implements PciHostBridgeLib for platforms exposing a PCI host bridge
>> using a pci-host-ecam-generic DT node. The initial version is based on the
>> ArmVirtPkg implementation of PciHostBridgeDxe, so it does not support 64-bit
>> MMIO BARs allocated above 4 GB, but it does support DMA above 4 GB without
>> bounce buffering.
>>
>> Patch #4 switches to the generic PciHostBridgeDxe, with no change in
>> functionality other than support for DMA above 4 GB without bounce buffering.
>>
>> Patch #5 adds support for allocating 64-bit MMIO BARs above 4 GB.
>>
>> Patch #6 removes the now obsolete PciHostBridgeDxe from ArmVirtPkg.
>>
>>
>> Ard Biesheuvel (6):
>> ArmVirtPkg/PciHostBridgeDxe: don't set linux,pci-probe-only DT
>> property
>> ArmVirtPkg/FdtPciPcdProducerLib: add handling of PcdPciIoTranslation
>> ArmVirtPkg: implement FdtPciHostBridgeLib
>> ArmVirtPkg/ArmVirtQemu: switch to generic PciHostBridgeDxe
>> ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 support
>> ArmVirtPkg: remove now unused PciHostBridgeDxe
>>
>> ArmVirtPkg/ArmVirtQemu.dsc | 10 +-
>> ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 3 +-
>> ArmVirtPkg/ArmVirtQemuKernel.dsc | 10 +-
>> ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 434 ++++
>> ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf | 57 +
>> ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.c | 108 +-
>> ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf | 2 +
>> ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c | 1496 --------------
>> ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.h | 499 -----
>> ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf | 64 -
>> ArmVirtPkg/PciHostBridgeDxe/PciRootBridgeIo.c | 2144 --------------------
>> 11 files changed, 611 insertions(+), 4216 deletions(-)
>> create mode 100644 ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
>> create mode 100644 ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
>> delete mode 100644 ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c
>> delete mode 100644 ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.h
>> delete mode 100644 ArmVirtPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf
>> delete mode 100644 ArmVirtPkg/PciHostBridgeDxe/PciRootBridgeIo.c
>
> Test results:
>
> (1) aarch64 TCG on an x86_64 host, using standard VGA (-device VGA) and USB 3 keyboard (-device nec-usb-xhci -device usb-kbd). I tested the display browser, the UEFI shell, and the GRUB menu. Didn't boot an actual OS. (Ain't nobody got time for that using TCG :))
>
> I also checked the ArmVirtQemu debug log, it looks very nice; there was even a 64-bit Mem64 BAR that got allocated high.
>
> (2) aarch64 KVM, using virtio-gpu-pci and USB 2 keyboard and tablet. I actually booted a Fedora 24 guest with this, and in the guest, everything works just fine (display, keyboard, mouse/tablet). Most of the firmware log looks good too.
>
> (2a) However, the USB 2 keyboard is broken while in the firmware (in spite of it working well in the guest OS).
>
> -device ich9-usb-ehci1,multifunction=on,id=ehci,addr=05.0 \
> -device ich9-usb-uhci1,multifunction=on,masterbus=ehci.0,firstport=0,addr=05.1 \
> -device ich9-usb-uhci2,multifunction=on,masterbus=ehci.0,firstport=2,addr=05.2 \
> -device ich9-usb-uhci3,multifunction=on,masterbus=ehci.0,firstport=4,addr=05.3 \
> -device usb-kbd,bus=ehci.0 \
> -device usb-tablet,bus=ehci.0 \
>
> My QEMU has your commit 5d636e21c44e ("hw/arm/virt: mark the PCIe host controller as DMA coherent in the DT"), but I guess the EHCI driver in edk2 doesn't comply with the "guest drivers should use cacheable accesses as well when running under KVM" part. :(
>
> The following snippet repeats in the log:
>
> EhcClearLegacySupport: called to clear legacy support
> processing error - resetting ehci HC
> EhcInitHC: failed to enable period schedule
> EhcDriverBindingStart: failed to init host controller
> EhcCreateUsb2Hc: capability length 32
>
> Interestingly, if I back out your series, then USB2 works in the firmware. I don't understand this, given that my build includes commit 3ef3209d3028 ("ArmVirtPkg: remove PcdKludgeMapPciMmioAsCached") from the master branch!
>
Does it work when you limit DMA to < 4 GB?
> (2b) Your series does not break virtio-{scsi,blk}-pci though, I verified that.
>
> (3) Another issue I noticed in testing is that the following line from patch #3 ("ArmVirtPkg: implement FdtPciHostBridgeLib"):
>
> + EISA_PNP_ID(0x0A08), // PCI Express
>
> which I initially thought would be okay actually breaks "OvmfPkg/Library/QemuBootOrderLib". The TranslatePciOfwNodes() function translates OFW devpaths into textual UEFI devpath fragments that start with PciRoot(), not PcieRoot(), and after your patch, these prefixes will no longer match the UEFI devpaths of the actual PCI devices.
>
> So, for this I'll have to go back on my initial approval, and ask you to keep this as 0x0A03. Yes, I know it won't match QEMU's ACPI payload perfectly, but the same is the case with the Q35 x86_64 machine type -- search "hw/i386/acpi-build.c" for the string "PNP0A08" -- and in practice it causes no problems at all.
>
> (4) This is for the longer term, but now that we have 64-bit MMIO aperture, we should include OvmfPkg/IncompatiblePciDeviceSupportDxe in ArmVirtQemu (please see commit 855743f71774). The circumstances described in the commit message now apply to ArmVirtQemu as well, if at least virtio-net-pci is used -- that device has an oprom, and by default that is reason enough for PciBusDxe to degrade the 64-bit MMIO BAR to 32-bit. Including "OvmfPkg/IncompatiblePciDeviceSupportDxe" will prevent this.
>
>
> I think (3) can be fixed up easily without a repost, and (4) can be addressed with a separate patch, later.
>
> However, I'm completely dumbfounded about (2a). Please do not tell me that we'll have to implement a virtio-input driver... :( I think there must be a mysterious caching difference between "MdeModulePkg/Bus/Pci/PciHostBridgeDxe" and "ArmVirtPkg/PciHostBridgeDxe", even after having removed the "kludge" from the latter!
>
> Maybe it has to do with the IO aperture. The USB1 companion controllers on the EHCI controller have one IO BAR each:
>
> PciBus: Resource Map for Root Bridge PcieRoot(0x0)
> Type = Io16; Base = 0x0; Length = 0x1000; Alignment = 0xFFF
> [...]
> Base = 0x80; Length = 0x20; Alignment = 0x1F; Owner = PCI [00|05|03:20]
> Base = 0xA0; Length = 0x20; Alignment = 0x1F; Owner = PCI [00|05|02:20]
> Base = 0xC0; Length = 0x20; Alignment = 0x1F; Owner = PCI [00|05|01:20]
> [...]
>
> and with your patches applied, accesses to these are now delegated to ArmPciCpuIo2Dxe. Maybe that makes a difference? I'm just guessing. (Again, the virtio-xxxx-pci devices, even forcing them to use IO BARs, with ",disable-modern=on", continue to work fine.)
>
> Since you authored QEMU commit 5d636e21c44e, I reckon (hope!) you have some background on the USB thing... What's your take?
>
> Thanks
> Laszlo
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe
2016-09-02 14:58 ` Ard Biesheuvel
@ 2016-09-02 15:27 ` Laszlo Ersek
2016-09-02 16:13 ` Laszlo Ersek
0 siblings, 1 reply; 17+ messages in thread
From: Laszlo Ersek @ 2016-09-02 15:27 UTC (permalink / raw)
To: Ard Biesheuvel; +Cc: edk2-devel, leif.lindholm
On 09/02/16 16:58, Ard Biesheuvel wrote:
> (on the road atm, will reply in full later)
>
>> On 2 sep. 2016, at 14:09, Laszlo Ersek <lersek@redhat.com> wrote:
>> (2) aarch64 KVM, using virtio-gpu-pci and USB 2 keyboard and
>> tablet. I actually booted a Fedora 24 guest with this, and in the
>> guest, everything works just fine (display, keyboard,
>> mouse/tablet). Most of the firmware log looks good too.
>>
>> (2a) However, the USB 2 keyboard is broken while in the firmware
>> (in spite of it working well in the guest OS).
>>
>> -device ich9-usb-ehci1,multifunction=on,id=ehci,addr=05.0 \
>> -device ich9-usb-uhci1,multifunction=on,masterbus=ehci.0,firstport=0,addr=05.1 \
>> -device ich9-usb-uhci2,multifunction=on,masterbus=ehci.0,firstport=2,addr=05.2 \
>> -device ich9-usb-uhci3,multifunction=on,masterbus=ehci.0,firstport=4,addr=05.3 \
>> -device usb-kbd,bus=ehci.0 \
>> -device usb-tablet,bus=ehci.0 \
>>
>> My QEMU has your commit 5d636e21c44e ("hw/arm/virt: mark the PCIe
>> host controller as DMA coherent in the DT"), but I guess the EHCI
>> driver in edk2 doesn't comply with the "guest drivers should use
>> cacheable accesses as well when running under KVM" part. :(
>>
>> The following snippet repeats in the log:
>>
>> EhcClearLegacySupport: called to clear legacy support
>> processing error - resetting ehci HC
>> EhcInitHC: failed to enable period schedule
>> EhcDriverBindingStart: failed to init host controller
>> EhcCreateUsb2Hc: capability length 32
>>
>> Interestingly, if I back out your series, then USB2 works in the
>> firmware. I don't understand this, given that my build includes
>> commit 3ef3209d3028 ("ArmVirtPkg: remove
>> PcdKludgeMapPciMmioAsCached") from the master branch!
>>
>
> Does it work when you limit DMA to < 4 GB?
You are one wicked genius, man; the following change
> diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> index efccedcca14f..1f0f87cac8a9 100644
> --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
> @@ -317,7 +317,7 @@ PciHostBridgeGetRootBridges (
> EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
> mRootBridge.Attributes = mRootBridge.Supports;
>
> - mRootBridge.DmaAbove4G = TRUE;
> + mRootBridge.DmaAbove4G = FALSE;
> mRootBridge.NoExtendedConfigSpace = FALSE;
> mRootBridge.ResourceAssigned = FALSE;
>
does make it work! Excellent!
Explain please. :) (Although, I'll look into PciHostBridgeDxe in a moment too. :))
Thank you!
Laszlo
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe
2016-09-02 15:27 ` Laszlo Ersek
@ 2016-09-02 16:13 ` Laszlo Ersek
2016-09-02 16:26 ` Ard Biesheuvel
0 siblings, 1 reply; 17+ messages in thread
From: Laszlo Ersek @ 2016-09-02 16:13 UTC (permalink / raw)
To: Ard Biesheuvel; +Cc: edk2-devel, leif.lindholm
On 09/02/16 17:27, Laszlo Ersek wrote:
> On 09/02/16 16:58, Ard Biesheuvel wrote:
>> (on the road atm, will reply in full later)
>>
>>> On 2 sep. 2016, at 14:09, Laszlo Ersek <lersek@redhat.com> wrote:
>
>>> (2) aarch64 KVM, using virtio-gpu-pci and USB 2 keyboard and
>>> tablet. I actually booted a Fedora 24 guest with this, and in the
>>> guest, everything works just fine (display, keyboard,
>>> mouse/tablet). Most of the firmware log looks good too.
>>>
>>> (2a) However, the USB 2 keyboard is broken while in the firmware
>>> (in spite of it working well in the guest OS).
>>>
>>> -device ich9-usb-ehci1,multifunction=on,id=ehci,addr=05.0 \
>>> -device ich9-usb-uhci1,multifunction=on,masterbus=ehci.0,firstport=0,addr=05.1 \
>>> -device ich9-usb-uhci2,multifunction=on,masterbus=ehci.0,firstport=2,addr=05.2 \
>>> -device ich9-usb-uhci3,multifunction=on,masterbus=ehci.0,firstport=4,addr=05.3 \
>>> -device usb-kbd,bus=ehci.0 \
>>> -device usb-tablet,bus=ehci.0 \
>>>
>>> My QEMU has your commit 5d636e21c44e ("hw/arm/virt: mark the PCIe
>>> host controller as DMA coherent in the DT"), but I guess the EHCI
>>> driver in edk2 doesn't comply with the "guest drivers should use
>>> cacheable accesses as well when running under KVM" part. :(
>>>
>>> The following snippet repeats in the log:
>>>
>>> EhcClearLegacySupport: called to clear legacy support
>>> processing error - resetting ehci HC
>>> EhcInitHC: failed to enable period schedule
>>> EhcDriverBindingStart: failed to init host controller
>>> EhcCreateUsb2Hc: capability length 32
>>>
>>> Interestingly, if I back out your series, then USB2 works in the
>>> firmware. I don't understand this, given that my build includes
>>> commit 3ef3209d3028 ("ArmVirtPkg: remove
>>> PcdKludgeMapPciMmioAsCached") from the master branch!
>>>
>>
>> Does it work when you limit DMA to < 4 GB?
>
> You are one wicked genius, man; the following change
>
>> diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
>> index efccedcca14f..1f0f87cac8a9 100644
>> --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
>> +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
>> @@ -317,7 +317,7 @@ PciHostBridgeGetRootBridges (
>> EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
>> mRootBridge.Attributes = mRootBridge.Supports;
>>
>> - mRootBridge.DmaAbove4G = TRUE;
>> + mRootBridge.DmaAbove4G = FALSE;
>> mRootBridge.NoExtendedConfigSpace = FALSE;
>> mRootBridge.ResourceAssigned = FALSE;
>>
>
> does make it work! Excellent!
>
> Explain please. :) (Although, I'll look into PciHostBridgeDxe in a moment too. :))
Well okay, I reviewed the RootBridgeIoMap() and RootBridgeIoUnmap()
functions in "MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c".
They implement bounce buffering when DmaAbove4G is set to FALSE, and
when the original RAM buffer, to be DMA'd from or to by the PCI device,
would end outside of 32-bit space.
For common buffer operations (when device and CPU collaborate on memory
repeatedly, without intervening Map() and Unmap() calls), Map() and
Unmap() cannot implement bounce buffering, so the initial buffer must be
allocated low enough. This is what RootBridgeIoAllocateBuffer() does,
and yes it considers DmaAbove4G as well.
EhciDxe uses these functions quite a bit. And, my test VM has 4G of
memory, with a base at 0x4000_0000 (1GB); the base is fixed of course,
from "-M virt". So, I guess, some buffers that EhciDxe allocated itself,
for DMA'ing from/to the device, and some buffers that it allocated with
AllocateBuffer(), for common operations with the device, ended up in the
4GB..5GB range. Due to DmaAbove4G = TRUE, those host addresses got
passed to the PCI device (the USB 2 host controller) verbatim, but that
device can only access host RAM in the 32-bit address range?....
Hm, let me check the QEMU code (hw/usb/hcd-ehci.c)...
Alright, I've found it. According to the EHCI specification
("ehci-specification-for-usb.pdf", link found under
<https://en.wikipedia.org/wiki/Extensible_Host_Controller_Interface#References>),
revision 1.0, section "2.2.4 HCCPARAMS -- Capability Parameters", bit #0
(value 1) in the HCCPARAMS capability register stands for:
64-bit Addressing Capability. This field documents the addressing
range capability of this implementation. The value of this field
determines whether software should use the data structures defined
in Section 3 (32-bit) or those defined in Appendix B (64-bit).
Values for this field have the following interpretation:
0b data structures using 32-bit address memory pointers
1b data structures using 64-bit address memory pointers
Furthermore, the HCCPARAMS register lives at address "Base + (08h)".
Now, looking at the QEMU code, we have usb_ehci_init()
[hw/usb/hcd-ehci.c] performing the following assignment:
s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
(And, the "cache whole frame" reference, for bit #7, is consistent with
the documentation of that bit in the spec: "When bit [7] is a
one, then host software assumes the host controller may cache an
isochronous data structure for an entire frame.")
So, bingo. Please flip DmaAbove4G to FALSE in patch #3, and please drop
the "DMA above 4 GB" paragraph from the commit message of patch #4.
Thanks!
Laszlo
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe
2016-09-02 16:13 ` Laszlo Ersek
@ 2016-09-02 16:26 ` Ard Biesheuvel
2016-09-02 17:21 ` Laszlo Ersek
0 siblings, 1 reply; 17+ messages in thread
From: Ard Biesheuvel @ 2016-09-02 16:26 UTC (permalink / raw)
To: Laszlo Ersek; +Cc: edk2-devel@lists.01.org, Leif Lindholm
On 2 September 2016 at 17:13, Laszlo Ersek <lersek@redhat.com> wrote:
> On 09/02/16 17:27, Laszlo Ersek wrote:
>> On 09/02/16 16:58, Ard Biesheuvel wrote:
>>> (on the road atm, will reply in full later)
>>>
>>>> On 2 sep. 2016, at 14:09, Laszlo Ersek <lersek@redhat.com> wrote:
>>
>>>> (2) aarch64 KVM, using virtio-gpu-pci and USB 2 keyboard and
>>>> tablet. I actually booted a Fedora 24 guest with this, and in the
>>>> guest, everything works just fine (display, keyboard,
>>>> mouse/tablet). Most of the firmware log looks good too.
>>>>
>>>> (2a) However, the USB 2 keyboard is broken while in the firmware
>>>> (in spite of it working well in the guest OS).
>>>>
>>>> -device ich9-usb-ehci1,multifunction=on,id=ehci,addr=05.0 \
>>>> -device ich9-usb-uhci1,multifunction=on,masterbus=ehci.0,firstport=0,addr=05.1 \
>>>> -device ich9-usb-uhci2,multifunction=on,masterbus=ehci.0,firstport=2,addr=05.2 \
>>>> -device ich9-usb-uhci3,multifunction=on,masterbus=ehci.0,firstport=4,addr=05.3 \
>>>> -device usb-kbd,bus=ehci.0 \
>>>> -device usb-tablet,bus=ehci.0 \
>>>>
>>>> My QEMU has your commit 5d636e21c44e ("hw/arm/virt: mark the PCIe
>>>> host controller as DMA coherent in the DT"), but I guess the EHCI
>>>> driver in edk2 doesn't comply with the "guest drivers should use
>>>> cacheable accesses as well when running under KVM" part. :(
>>>>
>>>> The following snippet repeats in the log:
>>>>
>>>> EhcClearLegacySupport: called to clear legacy support
>>>> processing error - resetting ehci HC
>>>> EhcInitHC: failed to enable period schedule
>>>> EhcDriverBindingStart: failed to init host controller
>>>> EhcCreateUsb2Hc: capability length 32
>>>>
>>>> Interestingly, if I back out your series, then USB2 works in the
>>>> firmware. I don't understand this, given that my build includes
>>>> commit 3ef3209d3028 ("ArmVirtPkg: remove
>>>> PcdKludgeMapPciMmioAsCached") from the master branch!
>>>>
>>>
>>> Does it work when you limit DMA to < 4 GB?
>>
>> You are one wicked genius, man; the following change
>>
>>> diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
>>> index efccedcca14f..1f0f87cac8a9 100644
>>> --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
>>> +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
>>> @@ -317,7 +317,7 @@ PciHostBridgeGetRootBridges (
>>> EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
>>> mRootBridge.Attributes = mRootBridge.Supports;
>>>
>>> - mRootBridge.DmaAbove4G = TRUE;
>>> + mRootBridge.DmaAbove4G = FALSE;
>>> mRootBridge.NoExtendedConfigSpace = FALSE;
>>> mRootBridge.ResourceAssigned = FALSE;
>>>
>>
>> does make it work! Excellent!
>>
>> Explain please. :) (Although, I'll look into PciHostBridgeDxe in a moment too. :))
>
Thanks. You seem to have a good handle on things already, though :-)
> Well okay, I reviewed the RootBridgeIoMap() and RootBridgeIoUnmap()
> functions in "MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c".
> They implement bounce buffering when DmaAbove4G is set to FALSE, and
> when the original RAM buffer, to be DMA'd from or to by the PCI device,
> would end outside of 32-bit space.
>
> For common buffer operations (when device and CPU collaborate on memory
> repeatedly, without intervening Map() and Unmap() calls), Map() and
> Unmap() cannot implement bounce buffering, so the initial buffer must be
> allocated low enough. This is what RootBridgeIoAllocateBuffer() does,
> and yes it considers DmaAbove4G as well.
>
> EhciDxe uses these functions quite a bit. And, my test VM has 4G of
> memory, with a base at 0x4000_0000 (1GB); the base is fixed of course,
> from "-M virt". So, I guess, some buffers that EhciDxe allocated itself,
> for DMA'ing from/to the device, and some buffers that it allocated with
> AllocateBuffer(), for common operations with the device, ended up in the
> 4GB..5GB range. Due to DmaAbove4G = TRUE, those host addresses got
> passed to the PCI device (the USB 2 host controller) verbatim, but that
> device can only access host RAM in the 32-bit address range?....
>
> Hm, let me check the QEMU code (hw/usb/hcd-ehci.c)...
>
> Alright, I've found it. According to the EHCI specification
> ("ehci-specification-for-usb.pdf", link found under
> <https://en.wikipedia.org/wiki/Extensible_Host_Controller_Interface#References>),
> revision 1.0, section "2.2.4 HCCPARAMS -- Capability Parameters", bit #0
> (value 1) in the HCCPARAMS capability register stands for:
>
>
> 64-bit Addressing Capability. This field documents the addressing
> range capability of this implementation. The value of this field
> determines whether software should use the data structures defined
> in Section 3 (32-bit) or those defined in Appendix B (64-bit).
> Values for this field have the following interpretation:
>
> 0b data structures using 32-bit address memory pointers
> 1b data structures using 64-bit address memory pointers
>
> Furthermore, the HCCPARAMS register lives at address "Base + (08h)".
>
> Now, looking at the QEMU code, we have usb_ehci_init()
> [hw/usb/hcd-ehci.c] performing the following assignment:
>
> s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
>
> (And, the "cache whole frame" reference, for bit #7, is consistent with
> the documentation of that bit in the spec: "When bit [7] is a
> one, then host software assumes the host controller may cache an
> isochronous data structure for an entire frame.")
>
> So, bingo. Please flip DmaAbove4G to FALSE in patch #3, and please drop
> the "DMA above 4 GB" paragraph from the commit message of patch #4.
>
Actually, I suspect this is a bug in PciHostBridgeDxe. It ignores the
absence of the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute, which
should be set by the driver if it knows the device is capable of
64-bit DMA.
Could you please try the below?
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index b2d76d67afa2..b53b9a834816 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -1308,7 +1308,8 @@ RootBridgeIoAllocateBuffer (
RootBridge = ROOT_BRIDGE_FROM_THIS (This);
AllocateType = AllocateAnyPages;
- if (!RootBridge->DmaAbove4G) {
+ if (!RootBridge->DmaAbove4G ||
+ (Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0) {
//
// Limit allocations to memory below 4GB
//
Thanks,
Ard.
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe
2016-09-02 16:26 ` Ard Biesheuvel
@ 2016-09-02 17:21 ` Laszlo Ersek
0 siblings, 0 replies; 17+ messages in thread
From: Laszlo Ersek @ 2016-09-02 17:21 UTC (permalink / raw)
To: Ard Biesheuvel; +Cc: edk2-devel@lists.01.org, Leif Lindholm
On 09/02/16 18:26, Ard Biesheuvel wrote:
> On 2 September 2016 at 17:13, Laszlo Ersek <lersek@redhat.com> wrote:
>> On 09/02/16 17:27, Laszlo Ersek wrote:
>>> On 09/02/16 16:58, Ard Biesheuvel wrote:
>>>> (on the road atm, will reply in full later)
>>>>
>>>>> On 2 sep. 2016, at 14:09, Laszlo Ersek <lersek@redhat.com> wrote:
>>>
>>>>> (2) aarch64 KVM, using virtio-gpu-pci and USB 2 keyboard and
>>>>> tablet. I actually booted a Fedora 24 guest with this, and in the
>>>>> guest, everything works just fine (display, keyboard,
>>>>> mouse/tablet). Most of the firmware log looks good too.
>>>>>
>>>>> (2a) However, the USB 2 keyboard is broken while in the firmware
>>>>> (in spite of it working well in the guest OS).
>>>>>
>>>>> -device ich9-usb-ehci1,multifunction=on,id=ehci,addr=05.0 \
>>>>> -device ich9-usb-uhci1,multifunction=on,masterbus=ehci.0,firstport=0,addr=05.1 \
>>>>> -device ich9-usb-uhci2,multifunction=on,masterbus=ehci.0,firstport=2,addr=05.2 \
>>>>> -device ich9-usb-uhci3,multifunction=on,masterbus=ehci.0,firstport=4,addr=05.3 \
>>>>> -device usb-kbd,bus=ehci.0 \
>>>>> -device usb-tablet,bus=ehci.0 \
>>>>>
>>>>> My QEMU has your commit 5d636e21c44e ("hw/arm/virt: mark the PCIe
>>>>> host controller as DMA coherent in the DT"), but I guess the EHCI
>>>>> driver in edk2 doesn't comply with the "guest drivers should use
>>>>> cacheable accesses as well when running under KVM" part. :(
>>>>>
>>>>> The following snippet repeats in the log:
>>>>>
>>>>> EhcClearLegacySupport: called to clear legacy support
>>>>> processing error - resetting ehci HC
>>>>> EhcInitHC: failed to enable period schedule
>>>>> EhcDriverBindingStart: failed to init host controller
>>>>> EhcCreateUsb2Hc: capability length 32
>>>>>
>>>>> Interestingly, if I back out your series, then USB2 works in the
>>>>> firmware. I don't understand this, given that my build includes
>>>>> commit 3ef3209d3028 ("ArmVirtPkg: remove
>>>>> PcdKludgeMapPciMmioAsCached") from the master branch!
>>>>>
>>>>
>>>> Does it work when you limit DMA to < 4 GB?
>>>
>>> You are one wicked genius, man; the following change
>>>
>>>> diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
>>>> index efccedcca14f..1f0f87cac8a9 100644
>>>> --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
>>>> +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c
>>>> @@ -317,7 +317,7 @@ PciHostBridgeGetRootBridges (
>>>> EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
>>>> mRootBridge.Attributes = mRootBridge.Supports;
>>>>
>>>> - mRootBridge.DmaAbove4G = TRUE;
>>>> + mRootBridge.DmaAbove4G = FALSE;
>>>> mRootBridge.NoExtendedConfigSpace = FALSE;
>>>> mRootBridge.ResourceAssigned = FALSE;
>>>>
>>>
>>> does make it work! Excellent!
>>>
>>> Explain please. :) (Although, I'll look into PciHostBridgeDxe in a moment too. :))
>>
>
> Thanks. You seem to have a good handle on things already, though :-)
>
>> Well okay, I reviewed the RootBridgeIoMap() and RootBridgeIoUnmap()
>> functions in "MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c".
>> They implement bounce buffering when DmaAbove4G is set to FALSE, and
>> when the original RAM buffer, to be DMA'd from or to by the PCI device,
>> would end outside of 32-bit space.
>>
>> For common buffer operations (when device and CPU collaborate on memory
>> repeatedly, without intervening Map() and Unmap() calls), Map() and
>> Unmap() cannot implement bounce buffering, so the initial buffer must be
>> allocated low enough. This is what RootBridgeIoAllocateBuffer() does,
>> and yes it considers DmaAbove4G as well.
>>
>> EhciDxe uses these functions quite a bit. And, my test VM has 4G of
>> memory, with a base at 0x4000_0000 (1GB); the base is fixed of course,
>> from "-M virt". So, I guess, some buffers that EhciDxe allocated itself,
>> for DMA'ing from/to the device, and some buffers that it allocated with
>> AllocateBuffer(), for common operations with the device, ended up in the
>> 4GB..5GB range. Due to DmaAbove4G = TRUE, those host addresses got
>> passed to the PCI device (the USB 2 host controller) verbatim, but that
>> device can only access host RAM in the 32-bit address range?....
>>
>> Hm, let me check the QEMU code (hw/usb/hcd-ehci.c)...
>>
>> Alright, I've found it. According to the EHCI specification
>> ("ehci-specification-for-usb.pdf", link found under
>> <https://en.wikipedia.org/wiki/Extensible_Host_Controller_Interface#References>),
>> revision 1.0, section "2.2.4 HCCPARAMS -- Capability Parameters", bit #0
>> (value 1) in the HCCPARAMS capability register stands for:
>>
>>
>> 64-bit Addressing Capability. This field documents the addressing
>> range capability of this implementation. The value of this field
>> determines whether software should use the data structures defined
>> in Section 3 (32-bit) or those defined in Appendix B (64-bit).
>> Values for this field have the following interpretation:
>>
>> 0b data structures using 32-bit address memory pointers
>> 1b data structures using 64-bit address memory pointers
>>
>> Furthermore, the HCCPARAMS register lives at address "Base + (08h)".
>>
>> Now, looking at the QEMU code, we have usb_ehci_init()
>> [hw/usb/hcd-ehci.c] performing the following assignment:
>>
>> s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
>>
>> (And, the "cache whole frame" reference, for bit #7, is consistent with
>> the documentation of that bit in the spec: "When bit [7] is a
>> one, then host software assumes the host controller may cache an
>> isochronous data structure for an entire frame.")
>>
>> So, bingo. Please flip DmaAbove4G to FALSE in patch #3, and please drop
>> the "DMA above 4 GB" paragraph from the commit message of patch #4.
>>
>
> Actually, I suspect this is a bug in PciHostBridgeDxe. It ignores the
> absence of the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute, which
> should be set by the driver if it knows the device is capable of
> 64-bit DMA.
>
> Could you please try the below?
>
>
> diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
> b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
> index b2d76d67afa2..b53b9a834816 100644
> --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
> +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
> @@ -1308,7 +1308,8 @@ RootBridgeIoAllocateBuffer (
> RootBridge = ROOT_BRIDGE_FROM_THIS (This);
>
> AllocateType = AllocateAnyPages;
> - if (!RootBridge->DmaAbove4G) {
> + if (!RootBridge->DmaAbove4G ||
> + (Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0) {
> //
> // Limit allocations to memory below 4GB
> //
>
> Thanks,
> Ard.
>
Before trying it, I'll say that I don't like it, for two reasons :)
(1) This will affect AllocateBuffer(), yes, but it doesn't affect Map()
and Unmap(). In fact I don't understand how the spec allows those
functions to communicate this kind of information between PciIo and
PciRootBridgeIo: while for AllocateBuffer(), the PciIo implementation
can check the device itself, and pass
EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE to PciRootBridgeIo, I don't see the
same possibility, in the spec, for Map(). There is no Attributes
parameter there. So how will PciRootBridgeIo know?
In more direct terms, you can't extend the DmaAbove4G check in
RootBridgeIoMap() in a similar fashion. (Is this a spec bug actually?)
(2) I tried to track down where EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE
would come from, in edk2. The only location that passes it is
PciIoAllocateBuffer() in "MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c" (i.e.,
the implementation of the similarly named PciIo protocol member).
The condition for passing this attribute to
PciRootBridgeIo.AllocateBuffer() is that
EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE (note: a different constant!) be
set in PciIo.Attributes -- i.e., on the PciIo device itself. Makes
sense, right?
So, what sets EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE on the device?
- PciSetDeviceAttribute() in
"MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c" sets the bit in
PCI_IO_DEVICE.Supports (not .Attributes!) unconditionally,
- in DetermineDeviceAttribute()
[MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c], the attribute
is again set unconditionally (only in PCI_IO_DEVICE.Supports),
accompanied by the comment "Assume the PCI Root Bridge supports DAC",
- ModifyRootBridgeAttributes() in
"MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c" seems to exclude this bit from
the set of bits that can be toggled.
So, I think unless a UEFI_DRIVER that consumes PciIo actively calls
PciIo.Attributes() with OperationSet / OperationEnable for
EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE, this code will never make a
difference.
UEFI_DRIVERs are actually expected to massage the PciIo attributes as
they see fit, for example EFI_PCI_IO_ATTRIBUTE_IO is frequently set for
IO BAR decoding. However, I couldn't find any driver in the tree that
would set EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE.
*Maybe*, I guess, EhciDxe could look at the HCCPARAMS register discussed
above, and then set EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE? I've got no
clue.
Anyway, after this wall of text, I should reenable >4GB DMA, and
actually test your patch... Yep, while it might be justified per se, it
definitely does not suffice for making things work. The USB 2 keyboard
remains broken with it.
Thanks
Laszlo
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2016-09-02 17:22 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-08-31 17:59 [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe Ard Biesheuvel
2016-08-31 17:59 ` [PATCH v2 1/6] ArmVirtPkg/PciHostBridgeDxe: don't set linux, pci-probe-only DT property Ard Biesheuvel
2016-08-31 17:59 ` [PATCH v2 2/6] ArmVirtPkg/FdtPciPcdProducerLib: add handling of PcdPciIoTranslation Ard Biesheuvel
2016-09-02 11:19 ` Laszlo Ersek
2016-08-31 17:59 ` [PATCH v2 3/6] ArmVirtPkg: implement FdtPciHostBridgeLib Ard Biesheuvel
2016-09-02 10:15 ` Laszlo Ersek
2016-08-31 17:59 ` [PATCH v2 4/6] ArmVirtPkg/ArmVirtQemu: switch to generic PciHostBridgeDxe Ard Biesheuvel
2016-08-31 17:59 ` [PATCH v2 5/6] ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 support Ard Biesheuvel
2016-09-02 10:44 ` Laszlo Ersek
2016-08-31 17:59 ` [PATCH v2 6/6] ArmVirtPkg: remove now unused PciHostBridgeDxe Ard Biesheuvel
2016-09-02 13:09 ` [PATCH v2 0/6] ArmVirtQemu: move to generic PciHostBridgeDxe Laszlo Ersek
2016-09-02 13:17 ` Laszlo Ersek
2016-09-02 14:58 ` Ard Biesheuvel
2016-09-02 15:27 ` Laszlo Ersek
2016-09-02 16:13 ` Laszlo Ersek
2016-09-02 16:26 ` Ard Biesheuvel
2016-09-02 17:21 ` Laszlo Ersek
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