From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x230.google.com (mail-wm0-x230.google.com [IPv6:2a00:1450:400c:c09::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DEEE61A1E79 for ; Fri, 2 Sep 2016 11:16:16 -0700 (PDT) Received: by mail-wm0-x230.google.com with SMTP id w207so13580170wmw.1 for ; Fri, 02 Sep 2016 11:16:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1HVTU66NVtbO9N47JsaJXrhLa7rEE2AovUgUcVmLkb4=; b=jTCvEf6EE7co3SuiIpk/20FMmk0JkjAIaaZ4wd0oMXkgroZrjs22iERswi7HK7N84t 43m2QLer9TMmFhUonsm5SP0EulvG5M0oOfukURGa4JIbMDVqUOvRbwoxSZKXLoiQg9ip 4yCkw0D320mcXItfyJlVsYtwwbHj3LXGv7oe8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1HVTU66NVtbO9N47JsaJXrhLa7rEE2AovUgUcVmLkb4=; b=J41fikJVv0pTLg2FEqeZ3UHwK6zG5AWjZDqiEa7/1Tq7cAyaaw1bkBIrRAb0c1Mx5s Ol7O5OG3tDeVPCapFVy6Z54e1Cy1TzCZLmYa26CNM/0f42pJ7pCgaA+r37ZtWEuFdiHh VHQ5bp48ab4/rCW+WpB7Myo2En4O1I4b0oo3gVooOgFHKSw0lRJwiambPTG20HAe92cL rHSqAwLJH3Qp0QIH8aaymI+D5USYKtAiwQ+Uf3Hzp19HNmP+E4TU4VC1BvBBbwVP3zLt 4fvk65eWamQ/aDi1R4X2HHuskG1AMluuWvdXvfzpH7lMyLPpOtpwTpbz2lh9vbVxxZKB vgYg== X-Gm-Message-State: AE9vXwMKarEhr6TTdvod1QMmt1YUK1gxwbe4ErX7NxZbTy/2VPVflA/UosszNbhKZuiL0Mrb X-Received: by 10.194.117.33 with SMTP id kb1mr10762987wjb.79.1472840175477; Fri, 02 Sep 2016 11:16:15 -0700 (PDT) Received: from localhost.localdomain ([160.165.63.90]) by smtp.gmail.com with ESMTPSA id id1sm11559152wjb.21.2016.09.02.11.16.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Sep 2016 11:16:14 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: lersek@redhat.com, Ard Biesheuvel Date: Fri, 2 Sep 2016 19:15:58 +0100 Message-Id: <1472840159-28957-6-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1472840159-28957-1-git-send-email-ard.biesheuvel@linaro.org> References: <1472840159-28957-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH v3 5/6] ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Sep 2016 18:16:17 -0000 If the pci-host-ecam-generic DT node describes a 64-bit MMIO region, account for it in the PCI_ROOT_BRIDGE description that we return to the generic PciHostBridgeDxe implementation, which will be able to allocate BARs from it without any further changes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Laszlo Ersek Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65 --- ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 80 ++++++++++++++------ ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf | 1 + 2 files changed, 59 insertions(+), 22 deletions(-) diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c index 7fe81ee09d87..bb3742386c63 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c @@ -87,8 +87,10 @@ EFI_STATUS ProcessPciHost ( OUT UINT64 *IoBase, OUT UINT64 *IoSize, - OUT UINT64 *MmioBase, - OUT UINT64 *MmioSize, + OUT UINT64 *Mmio32Base, + OUT UINT64 *Mmio32Size, + OUT UINT64 *Mmio64Base, + OUT UINT64 *Mmio64Size, OUT UINT32 *BusMin, OUT UINT32 *BusMax ) @@ -101,7 +103,8 @@ ProcessPciHost ( UINT32 RecordIdx; EFI_STATUS Status; UINT64 IoTranslation; - UINT64 MmioTranslation; + UINT64 Mmio32Translation; + UINT64 Mmio64Translation; // // The following output arguments are initialized only in @@ -109,17 +112,19 @@ ProcessPciHost ( // *incorrectly* emitted by some gcc versions. // *IoBase = 0; - *MmioBase = 0; + *Mmio32Base = 0; + *Mmio64Base = MAX_UINT64; *BusMin = 0; *BusMax = 0; // - // *IoSize, *MmioSize and IoTranslation are initialized to zero because the + // *IoSize, *Mmio##Size and IoTranslation are initialized to zero because the // logic below requires it. However, since they are also affected by the issue // reported above, they are initialized early. // *IoSize = 0; - *MmioSize = 0; + *Mmio32Size = 0; + *Mmio64Size = 0; IoTranslation = 0; Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL, @@ -209,28 +214,43 @@ ProcessPciHost ( break; case DTB_PCI_HOST_RANGE_MMIO32: - *MmioBase = SwapBytes64 (Record->ChildBase); - *MmioSize = SwapBytes64 (Record->Size); - MmioTranslation = SwapBytes64 (Record->CpuBase) - *MmioBase; + *Mmio32Base = SwapBytes64 (Record->ChildBase); + *Mmio32Size = SwapBytes64 (Record->Size); + Mmio32Translation = SwapBytes64 (Record->CpuBase) - *Mmio32Base; - if (*MmioBase > MAX_UINT32 || *MmioSize > MAX_UINT32 || - *MmioBase + *MmioSize > SIZE_4GB) { + if (*Mmio32Base > MAX_UINT32 || *Mmio32Size > MAX_UINT32 || + *Mmio32Base + *Mmio32Size > SIZE_4GB) { DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__)); return EFI_PROTOCOL_ERROR; } - ASSERT (PcdGet64 (PcdPciMmio32Translation) == MmioTranslation); + ASSERT (PcdGet64 (PcdPciMmio32Translation) == Mmio32Translation); - if (MmioTranslation != 0) { + if (Mmio32Translation != 0) { DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation " - "0x%Lx\n", __FUNCTION__, MmioTranslation)); + "0x%Lx\n", __FUNCTION__, Mmio32Translation)); + return EFI_UNSUPPORTED; + } + + break; + + case DTB_PCI_HOST_RANGE_MMIO64: + *Mmio64Base = SwapBytes64 (Record->ChildBase); + *Mmio64Size = SwapBytes64 (Record->Size); + Mmio64Translation = SwapBytes64 (Record->CpuBase) - *Mmio64Base; + + ASSERT (PcdGet64 (PcdPciMmio64Translation) == Mmio64Translation); + + if (Mmio64Translation != 0) { + DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO64 translation " + "0x%Lx\n", __FUNCTION__, Mmio64Translation)); return EFI_UNSUPPORTED; } break; } } - if (*IoSize == 0 || *MmioSize == 0) { + if (*IoSize == 0 || *Mmio32Size == 0) { DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__, (*IoSize == 0) ? "IO" : "MMIO32")); return EFI_PROTOCOL_ERROR; @@ -243,9 +263,9 @@ ProcessPciHost ( ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase); DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] " - "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x0\n", __FUNCTION__, ConfigBase, - ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, IoTranslation, *MmioBase, - *MmioSize)); + "Io[0x%Lx+0x%Lx)@0x%Lx Mem32[0x%Lx+0x%Lx)@0x0 Mem64[0x%Lx+0x%Lx)@0x0\n", + __FUNCTION__, ConfigBase, ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, + IoTranslation, *Mmio32Base, *Mmio32Size, *Mmio64Base, *Mmio64Size)); return EFI_SUCCESS; } @@ -268,6 +288,7 @@ PciHostBridgeGetRootBridges ( { UINT64 IoBase, IoSize; UINT64 Mmio32Base, Mmio32Size; + UINT64 Mmio64Base, Mmio64Size; UINT32 BusMin, BusMax; EFI_STATUS Status; @@ -278,8 +299,8 @@ PciHostBridgeGetRootBridges ( return NULL; } - Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size, &BusMin, - &BusMax); + Status = ProcessPciHost (&IoBase, &IoSize, &Mmio32Base, &Mmio32Size, + &Mmio64Base, &Mmio64Size, &BusMin, &BusMax); if (EFI_ERROR (Status)) { DEBUG ((EFI_D_ERROR, "%a: failed to discover PCI host bridge: %r\n", __FUNCTION__, Status)); @@ -308,8 +329,23 @@ PciHostBridgeGetRootBridges ( mRootBridge.Io.Limit = IoBase + IoSize - 1; mRootBridge.Mem.Base = Mmio32Base; mRootBridge.Mem.Limit = Mmio32Base + Mmio32Size - 1; - mRootBridge.MemAbove4G.Base = MAX_UINT64; - mRootBridge.MemAbove4G.Limit = 0; + + if (sizeof (UINTN) == sizeof (UINT64)) { + mRootBridge.MemAbove4G.Base = Mmio64Base; + mRootBridge.MemAbove4G.Limit = Mmio64Base + Mmio64Size - 1; + if (Mmio64Size > 0) { + mRootBridge.AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE; + } + } else { + // + // UEFI mandates a 1:1 virtual-to-physical mapping, so on a 32-bit + // architecture such as ARM, we will not be able to access 64-bit MMIO + // BARs unless they are allocated below 4 GB. So ignore the range above + // 4 GB in this case. + // + mRootBridge.MemAbove4G.Base = MAX_UINT64; + mRootBridge.MemAbove4G.Limit = 0; + } // // No separate ranges for prefetchable and non-prefetchable BARs diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf index fc1d37fb3c23..0995f4b7a156 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf @@ -47,6 +47,7 @@ [LibraryClasses] [FixedPcd] gArmTokenSpaceGuid.PcdPciMmio32Translation + gArmTokenSpaceGuid.PcdPciMmio64Translation [Pcd] gArmTokenSpaceGuid.PcdPciIoTranslation -- 2.7.4