From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22c.google.com (mail-wm0-x22c.google.com [IPv6:2a00:1450:400c:c09::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 95D6B1A1E66 for ; Mon, 5 Sep 2016 02:17:54 -0700 (PDT) Received: by mail-wm0-x22c.google.com with SMTP id w12so3948267wmf.0 for ; Mon, 05 Sep 2016 02:17:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4F0WYUDA5VWB0asa9qmUkozyH3XJmiJSo+OpIYj5v78=; b=jGOevDM4OsGDIDCqrqQuDGYKUL2He9R8SjhQsyV9A4WK+GKeu73a1bo/IydTX/LNDd +vJcOgAhCDWudkTsfFF9KkxfGOoja6uf9lks4PCEPIVZ37lIQFGpONUC7RFpnpW51Fkf Phb7J38ICgvJ5+VS+073vScKzVNtIRmXCQFf4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4F0WYUDA5VWB0asa9qmUkozyH3XJmiJSo+OpIYj5v78=; b=PUS1lgrlbxdTbjUINUw8vRNqFe4Gl5jToP38yzCUwMXnJ7KMgfhp5dL81hP/G/35ZS NofpRewsyw0s7z/Jw94ajZKDWInyZ76z659u2KQOdNMDd3eV1/fRIPw0aiyCaTuQ0VTY FIJb7q71wSHXGQJNc2hiGa0tOtLA5nvJsiYt+KmZUy2ecnTVzAOFphGu69vvd0dRie1F mdB5dRAqG3XqHSKMoKotBKX300Y21/qOiLmSB0U6m+VIzAVxxAX0++hvPL054e5UsgTK qqbV5YV34SaZQSlxUOuBJRaxtg1o9JsxinE1jrPefvWhHWzkryQQNZCThaZy6W85qyZe fOgg== X-Gm-Message-State: AE9vXwM8yOOKzCr3Kgiv0ulvVMXpWVD3ZBlO1d3WZXU1EZr6of8lXMoeO2ehw1KTjqmbBaPm X-Received: by 10.28.145.137 with SMTP id t131mr15107438wmd.110.1473067073152; Mon, 05 Sep 2016 02:17:53 -0700 (PDT) Received: from localhost.localdomain ([197.130.133.164]) by smtp.gmail.com with ESMTPSA id m133sm10157457wmg.0.2016.09.05.02.17.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Sep 2016 02:17:52 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, feng.tian@intel.com, star.zeng@intel.com, liming.gao@intel.com Cc: lersek@redhat.com, leif.lindholm@linaro.org, Ard Biesheuvel Date: Mon, 5 Sep 2016 10:17:27 +0100 Message-Id: <1473067049-16252-6-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473067049-16252-1-git-send-email-ard.biesheuvel@linaro.org> References: <1473067049-16252-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH 5/7] MdeModulePkg/XhciDxe: enable 64-bit PCI DMA X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Sep 2016 09:17:55 -0000 PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the controller supports 64-bit DMA addressing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 22 +++++++++++++++++++- MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h | 2 ++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c index 4798bea86061..cdff1c3b8849 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c @@ -125,7 +125,7 @@ XhcGetCapability ( Xhc = XHC_FROM_THIS (This); *MaxSpeed = EFI_USB_SPEED_SUPER; *PortNumber = (UINT8) (Xhc->HcSParams1.Data.MaxPorts); - *Is64BitCapable = (UINT8) (Xhc->HcCParams.Data.Ac64); + *Is64BitCapable = (UINT8) Xhc->Support64BitDma; DEBUG ((EFI_D_INFO, "XhcGetCapability: %d ports, 64 bit %d\n", *PortNumber, *Is64BitCapable)); gBS->RestoreTPL (OldTpl); @@ -2020,6 +2020,26 @@ XhcDriverBindingStart ( return EFI_OUT_OF_RESOURCES; } + // + // Enable 64-bit DMA support in the PCI layer if this controller + // supports it. + // + if ((Xhc->HcCParams.Data.Ac64) != 0) { + Status = PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationEnable, + EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE, + NULL + ); + if (!EFI_ERROR (Status)) { + Xhc->Support64BitDma = TRUE; + } else { + DEBUG ((EFI_D_WARN, + "XhcDriverBindingStart: failed to enable 64-bit DMA on 64-bit capable controller @ %p (%r)\n", + Controller, Status)); + } + } + XhcSetBiosOwnership (Xhc); XhcResetHC (Xhc, XHC_RESET_TIMEOUT); diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h index 7999151b3fde..0f53bb0eff7c 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h @@ -256,6 +256,8 @@ struct _USB_XHCI_INSTANCE { // The array supports up to 255 devices, entry 0 is reserved and should not be used. // USB_DEV_CONTEXT UsbDevContext[256]; + + BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device }; -- 2.7.4