From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x234.google.com (mail-wm0-x234.google.com [IPv6:2a00:1450:400c:c09::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7B12C1A1E27 for ; Mon, 5 Sep 2016 02:17:56 -0700 (PDT) Received: by mail-wm0-x234.google.com with SMTP id w12so3948466wmf.0 for ; Mon, 05 Sep 2016 02:17:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gwymjsq8OQcP0hhpbpOj+oQLG+xXofgo+1RHHPAZQ1w=; b=VJW3+uHApdzfBxm2Shs1wE0X6136NE2+KG7702jcaFiV9qcQACdZaaodlKAfjaWU8e eKdjCgTFgVYtqu2XK2yDctX2TBpGPdJZaIi0DTnubn38ZY+/MKEyut7dad7w7PYdh/Dp W+jhQiErWU+/txT9x3BEV8/ete4J2uxa1ZORk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gwymjsq8OQcP0hhpbpOj+oQLG+xXofgo+1RHHPAZQ1w=; b=fXq5SIBFLShomWAOMQ5ex67KxIhtBQc16/gfmgLeNhD7MDbbeUCvMouP3HM6eNPXsY uGhjZkQw/5idNss0ZQRs3oqicRQgiUwyC/B8U8H5mQV1CSuFB7jJrUHoY12vPbtXN2Ih Z8omxYhW5DtpGOT00mVV50rDpaKd6LdKs3SViqaN8qsfyvLsXIJQd7UPtwwQwt5IXwFu VQ+r5m9vqAh39ny2VsI9/T9denj35CUdK5JaTZSba1sk5TM86OsUOM9ieA8fqWuYr0kb wOQc+fYWaNGE7HpxYqb4RPNUlV3yaCnCM9dS3udDSNxExmFCx43cW/1kHTibjNBg5LNk UlTw== X-Gm-Message-State: AE9vXwPkE9w5io5UKLfipeYwsatgLAEImM42XXZ9/eSGHxxBetooqofC7JhM5kLBHa808ZJL X-Received: by 10.28.55.67 with SMTP id e64mr15014070wma.107.1473067075099; Mon, 05 Sep 2016 02:17:55 -0700 (PDT) Received: from localhost.localdomain ([197.130.133.164]) by smtp.gmail.com with ESMTPSA id m133sm10157457wmg.0.2016.09.05.02.17.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Sep 2016 02:17:54 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, feng.tian@intel.com, star.zeng@intel.com, liming.gao@intel.com Cc: lersek@redhat.com, leif.lindholm@linaro.org, Ard Biesheuvel Date: Mon, 5 Sep 2016 10:17:28 +0100 Message-Id: <1473067049-16252-7-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473067049-16252-1-git-send-email-ard.biesheuvel@linaro.org> References: <1473067049-16252-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH 6/7] MdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to devices that support it X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Sep 2016 09:17:56 -0000 Currently, the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute is completely ignored by the PCI host bridge driver, which means that, on an implementation that supports DMA above 4 GB, allocations above 4 GB may be provided to devices that have not expressed support for it. So in addition to checking 'RootBridge->DmaAbove4G' to establish whether the root bridge itself supports DMA above 4 GB, we must also take into account the operation type (EfiPciOperationBusMaster{Read|Write|CommBuffer}64), and the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute, when mapping and allocating DMA memory, respectively. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index b2d76d67afa2..8af131b0af37 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -1073,10 +1073,15 @@ RootBridgeIoMap ( RootBridge = ROOT_BRIDGE_FROM_THIS (This); PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress; - if (!RootBridge->DmaAbove4G && ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB)) { + if ((!RootBridge->DmaAbove4G || + (Operation != EfiPciOperationBusMasterRead64 && + Operation != EfiPciOperationBusMasterWrite64 && + Operation != EfiPciOperationBusMasterCommonBuffer64)) && + ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB)) { + // - // If the root bridge can not handle performing DMA above 4GB but - // any part of the DMA transfer being mapped is above 4GB, then + // If the root bridge or the device cannot handle performing DMA above + // 4GB but any part of the DMA transfer being mapped is above 4GB, then // map the DMA transfer to a buffer below 4GB. // @@ -1308,7 +1313,8 @@ RootBridgeIoAllocateBuffer ( RootBridge = ROOT_BRIDGE_FROM_THIS (This); AllocateType = AllocateAnyPages; - if (!RootBridge->DmaAbove4G) { + if (!RootBridge->DmaAbove4G || + (Attributes & EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) == 0) { // // Limit allocations to memory below 4GB // -- 2.7.4