[PATCH v1 2/5] UefiCpuPkg/SmmCpuFeaturesLib: Abstact processor features

[Joseph Shifflett <joseph.shifflett@hpe.com>]

Create new functions to abstract how XD/NX is detected, enabled, and
disabled.  Also, create a new function to determine if Branch Trace
Storage is supported.  Existing code is specific to Intel processors.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Joseph Shifflett <joseph.shifflett@hpe.com>
---
 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 78 ++++++++++++++++++++
 1 file changed, 78 insertions(+)

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
index 1754f2df5f57..f7d1223ddf55 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
@@ -2,6 +2,7 @@
 The CPU specific programming for PiSmmCpuDxeSmm module.
 
 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
 which accompanies this distribution.  The full text of the license may be found at
@@ -20,6 +21,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include <Library/MemoryAllocationLib.h>
 #include <Library/DebugLib.h>
 #include <Register/Cpuid.h>
+#include <Register/Msr.h>
 #include <Register/SmramSaveStateMap.h>
 
 //
@@ -673,3 +675,79 @@ SmmCpuFeaturesAllocatePageTableMemory (
   return NULL;
 }
 
+/**
+  This API provides a method to determine if XD/NX support has been forced off in
+  the non-SMM execution environment.  It will enable XD/NX support while in SMM
+
+  @retval TRUE   XD/NX was disabled when runningn in the non-SMM execution environment
+  @retval FALSE  XD/NX was enabled when runningn in the non-SMM execution environment
+
+**/
+BOOLEAN
+EFIAPI
+SmmCpuFeaturesCheckAndEnableXdSupport (
+  VOID
+  )
+{
+  BOOLEAN                        XdDisableFlag;
+  MSR_IA32_MISC_ENABLE_REGISTER  MiscEnableMsr;
+
+  XdDisableFlag = FALSE;
+
+  MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
+  if (MiscEnableMsr.Bits.XD == 1) {
+    XdDisableFlag = TRUE;
+    MiscEnableMsr.Bits.XD = 0;
+    AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, MiscEnableMsr.Uint64);
+  }
+  return XdDisableFlag;
+}
+
+/**
+  This API provides a method to disable XD/NX support before exiting SMM
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesDisableXdSupport (
+  VOID
+  )
+{
+  MSR_IA32_MISC_ENABLE_REGISTER  MiscEnableMsr;
+
+  MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
+  MiscEnableMsr.Bits.XD = 1;
+  AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, MiscEnableMsr.Uint64);
+}
+
+/**
+  This API determines if Branch Trace Storage Support is currently available
+
+  @retval TRUE   BTS is available
+  @retval FALSE  BTS is disabled
+
+**/
+BOOLEAN
+EFIAPI
+SmmCpuFeaturesConfirmBranchTraceStorageSupport (
+  VOID
+  )
+{
+  MSR_IA32_MISC_ENABLE_REGISTER  MiscEnableMsr;
+
+  //
+  // Per IA32 manuals:
+  // When CPUID.1:EDX[21] is set, the following BTS facilities are available:
+  // 1. The BTS_UNAVAILABLE flag in the IA32_MISC_ENABLE MSR indicates the
+  //    availability of the BTS facilities, including the ability to set the BTS and
+  //    BTINT bits in the MSR_DEBUGCTLA MSR.
+  // 2. The IA32_DS_AREA MSR can be programmed to point to the DS save area.
+  //
+  MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
+  if (MiscEnableMsr.Bits.BTS == 1) {
+    //
+    // BTS facilities is not supported if MSR_IA32_MISC_ENABLE.BTS bit is set.
+    //
+    return FALSE;
+  }
+  return TRUE;
+}
-- 
2.7.4