From: Joseph Shifflett <joseph.shifflett@hpe.com>
To: edk2-devel@lists.01.org
Subject: [PATCH v1 5/5] UefiCpuPkg/PiSmmCpuDxeSmm: Abstact processor features
Date: Wed, 7 Sep 2016 23:30:15 -0500 [thread overview]
Message-ID: <1473309015-26017-6-git-send-email-joseph.shifflett@hpe.com> (raw)
In-Reply-To: <1473309015-26017-1-git-send-email-joseph.shifflett@hpe.com>
Use newly created functions that abstract how XD/NX is detected,
enabled, and disabled. Also, use a new function to determine if
Branch Trace Storage is supported. Existing code is specific
to Intel processors.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Joseph Shifflett <joseph.shifflett@hpe.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 13 +++----------
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 18 ++----------------
2 files changed, 5 insertions(+), 26 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 12466ef5de1f..d116ffd39c20 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -2,6 +2,7 @@
SMM MP service implementation
Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -1023,7 +1024,6 @@ SmiRendezvous (
UINTN Index;
UINTN Cr2;
BOOLEAN XdDisableFlag;
- MSR_IA32_MISC_ENABLE_REGISTER MiscEnableMsr;
//
// Save Cr2 because Page Fault exception in SMM may override its value
@@ -1087,12 +1087,7 @@ SmiRendezvous (
//
XdDisableFlag = FALSE;
if (mXdSupported) {
- MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
- if (MiscEnableMsr.Bits.XD == 1) {
- XdDisableFlag = TRUE;
- MiscEnableMsr.Bits.XD = 0;
- AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, MiscEnableMsr.Uint64);
- }
+ XdDisableFlag = SmmCpuFeaturesCheckAndEnableXdSupport ();
ActivateXd ();
}
@@ -1182,9 +1177,7 @@ SmiRendezvous (
// Restore XD
//
if (XdDisableFlag) {
- MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
- MiscEnableMsr.Bits.XD = 1;
- AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, MiscEnableMsr.Uint64);
+ SmmCpuFeaturesDisableXdSupport ();
}
}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index 329574ebb24e..47793b27f2f1 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -2,6 +2,7 @@
Enable SMM profile.
Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -933,7 +934,6 @@ CheckFeatureSupported (
{
UINT32 RegEax;
UINT32 RegEdx;
- MSR_IA32_MISC_ENABLE_REGISTER MiscEnableMsr;
if (mXdSupported) {
AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
@@ -956,21 +956,7 @@ CheckFeatureSupported (
if (mBtsSupported) {
AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
if ((RegEdx & CPUID1_EDX_BTS_AVAILABLE) != 0) {
- //
- // Per IA32 manuals:
- // When CPUID.1:EDX[21] is set, the following BTS facilities are available:
- // 1. The BTS_UNAVAILABLE flag in the IA32_MISC_ENABLE MSR indicates the
- // availability of the BTS facilities, including the ability to set the BTS and
- // BTINT bits in the MSR_DEBUGCTLA MSR.
- // 2. The IA32_DS_AREA MSR can be programmed to point to the DS save area.
- //
- MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
- if (MiscEnableMsr.Bits.BTS == 1) {
- //
- // BTS facilities is not supported if MSR_IA32_MISC_ENABLE.BTS bit is set.
- //
- mBtsSupported = FALSE;
- }
+ mBtsSupported = SmmCpuFeaturesConfirmBranchTraceStorageSupport ();
}
}
}
--
2.7.4
next prev parent reply other threads:[~2016-09-08 4:30 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-08 4:30 [PATCH v1 0/5] Abstract the detect/enable/disable of several x86 features Joseph Shifflett
2016-09-08 4:30 ` [PATCH v1 1/5] UefiCpuPkg: SmmCpuFeaturesLib.h: Abstact processor features Joseph Shifflett
2016-09-08 8:10 ` Laszlo Ersek
2016-09-08 4:30 ` [PATCH v1 2/5] UefiCpuPkg/SmmCpuFeaturesLib: " Joseph Shifflett
2016-09-08 4:30 ` [PATCH v1 3/5] QuarkSocPkg/SmmCpuFeaturesLib: " Joseph Shifflett
2016-09-08 4:30 ` [PATCH v1 4/5] OvmfPkg/SmmCpuFeaturesLib: " Joseph Shifflett
2016-09-08 8:38 ` Laszlo Ersek
2016-09-08 4:30 ` Joseph Shifflett [this message]
2016-09-08 8:27 ` [PATCH v1 0/5] Abstract the detect/enable/disable of several x86 features Fan, Jeff
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1473309015-26017-6-git-send-email-joseph.shifflett@hpe.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox