From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C59FA1A1F1A for ; Wed, 7 Sep 2016 21:30:17 -0700 (PDT) Received: from arm-build-server.us.rdlabs.hpecorp.net (arm-build-server.us.rdlabs.hpecorp.net [16.84.24.54]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id 97CCA60 for ; Thu, 8 Sep 2016 04:30:16 +0000 (UTC) From: Joseph Shifflett To: edk2-devel@lists.01.org Date: Wed, 7 Sep 2016 23:30:15 -0500 Message-Id: <1473309015-26017-6-git-send-email-joseph.shifflett@hpe.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473309015-26017-1-git-send-email-joseph.shifflett@hpe.com> References: <1473309015-26017-1-git-send-email-joseph.shifflett@hpe.com> Subject: [PATCH v1 5/5] UefiCpuPkg/PiSmmCpuDxeSmm: Abstact processor features X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Sep 2016 04:30:18 -0000 Use newly created functions that abstract how XD/NX is detected, enabled, and disabled. Also, use a new function to determine if Branch Trace Storage is supported. Existing code is specific to Intel processors. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Joseph Shifflett --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 13 +++---------- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 18 ++---------------- 2 files changed, 5 insertions(+), 26 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index 12466ef5de1f..d116ffd39c20 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -2,6 +2,7 @@ SMM MP service implementation Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+(C) Copyright 2016 Hewlett Packard Enterprise Development LP
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -1023,7 +1024,6 @@ SmiRendezvous ( UINTN Index; UINTN Cr2; BOOLEAN XdDisableFlag; - MSR_IA32_MISC_ENABLE_REGISTER MiscEnableMsr; // // Save Cr2 because Page Fault exception in SMM may override its value @@ -1087,12 +1087,7 @@ SmiRendezvous ( // XdDisableFlag = FALSE; if (mXdSupported) { - MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE); - if (MiscEnableMsr.Bits.XD == 1) { - XdDisableFlag = TRUE; - MiscEnableMsr.Bits.XD = 0; - AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, MiscEnableMsr.Uint64); - } + XdDisableFlag = SmmCpuFeaturesCheckAndEnableXdSupport (); ActivateXd (); } @@ -1182,9 +1177,7 @@ SmiRendezvous ( // Restore XD // if (XdDisableFlag) { - MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE); - MiscEnableMsr.Bits.XD = 1; - AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, MiscEnableMsr.Uint64); + SmmCpuFeaturesDisableXdSupport (); } } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c index 329574ebb24e..47793b27f2f1 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -2,6 +2,7 @@ Enable SMM profile. Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+(C) Copyright 2016 Hewlett Packard Enterprise Development LP
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -933,7 +934,6 @@ CheckFeatureSupported ( { UINT32 RegEax; UINT32 RegEdx; - MSR_IA32_MISC_ENABLE_REGISTER MiscEnableMsr; if (mXdSupported) { AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); @@ -956,21 +956,7 @@ CheckFeatureSupported ( if (mBtsSupported) { AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx); if ((RegEdx & CPUID1_EDX_BTS_AVAILABLE) != 0) { - // - // Per IA32 manuals: - // When CPUID.1:EDX[21] is set, the following BTS facilities are available: - // 1. The BTS_UNAVAILABLE flag in the IA32_MISC_ENABLE MSR indicates the - // availability of the BTS facilities, including the ability to set the BTS and - // BTINT bits in the MSR_DEBUGCTLA MSR. - // 2. The IA32_DS_AREA MSR can be programmed to point to the DS save area. - // - MiscEnableMsr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE); - if (MiscEnableMsr.Bits.BTS == 1) { - // - // BTS facilities is not supported if MSR_IA32_MISC_ENABLE.BTS bit is set. - // - mBtsSupported = FALSE; - } + mBtsSupported = SmmCpuFeaturesConfirmBranchTraceStorageSupport (); } } } -- 2.7.4