From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: edk2-devel@lists.01.org, leif.lindholm@linaro.org
Cc: eugene@hp.com, Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: [PATCH 2/2] Platforms/ARM/FVP: limit VA range to 36 bits
Date: Fri, 9 Sep 2016 09:15:39 +0100 [thread overview]
Message-ID: <1473408939-18044-2-git-send-email-ard.biesheuvel@linaro.org> (raw)
In-Reply-To: <1473408939-18044-1-git-send-email-ard.biesheuvel@linaro.org>
The FVP model has up to 8 GB of memory (on the Base model), where the
top 6GB starts at 0x8_8000_0000, and all other memory regions of interest
live below that. This means we can cover the whole VA space with 36-bits
worth of VA.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
index 3d8e0cfbb57e..60df45dca276 100644
--- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
+++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
@@ -175,6 +175,9 @@
# Set tick frequency value to 100Mhz
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|100000000
+ # the entire FVP address space can be covered by 36 bit VAs
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36
+
[PcdsDynamicDefault.common]
#
# The size of a dynamic PCD of the (VOID*) type can not be increased at run
--
2.7.4
next prev parent reply other threads:[~2016-09-09 8:15 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-09 8:15 [PATCH 1/2] Platforms/AMD/Styx: limit VA space to 40 bits Ard Biesheuvel
2016-09-09 8:15 ` Ard Biesheuvel [this message]
2016-09-13 10:43 ` [PATCH 2/2] Platforms/ARM/FVP: limit VA range to 36 bits Leif Lindholm
2016-09-13 10:43 ` [PATCH 1/2] Platforms/AMD/Styx: limit VA space to 40 bits Leif Lindholm
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