* [PATCH 1/2] Platforms/AMD/Styx: limit VA space to 40 bits
@ 2016-09-09 8:15 Ard Biesheuvel
2016-09-09 8:15 ` [PATCH 2/2] Platforms/ARM/FVP: limit VA range to 36 bits Ard Biesheuvel
2016-09-13 10:43 ` [PATCH 1/2] Platforms/AMD/Styx: limit VA space to 40 bits Leif Lindholm
0 siblings, 2 replies; 4+ messages in thread
From: Ard Biesheuvel @ 2016-09-09 8:15 UTC (permalink / raw)
To: edk2-devel, leif.lindholm; +Cc: eugene, Ard Biesheuvel
We can cover the entire MMIO range and 512 GB of memory starting at
0x80_0000_0000 using 40 bits of VA space, both in the page tables and
in the GCD memory map.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 5 +++++
Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 5 +++++
2 files changed, 10 insertions(+)
diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc
index 8a100e0d9a3c..0a987cc3b118 100644
--- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc
+++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc
@@ -375,6 +375,11 @@ DEFINE DO_KCS = 0
# Size of the region used by UEFI in permanent memory (Reserved 64MB)
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
+ # 40 bits of VA space is sufficient to support up to 512 GB of RAM in the
+ # range 0x80_0000_0000 - 0xFF_FFFF_FFFF (all platform and PCI MMIO is below
+ # that)
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+
#
# ARM PrimeCell
#
diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
index 38c3309dcff1..72ceb8b6994e 100644
--- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
+++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
@@ -382,6 +382,11 @@ DEFINE DO_KCS = 1
# Size of the region used by UEFI in permanent memory (Reserved 64MB)
gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
+ # 40 bits of VA space is sufficient to support up to 512 GB of RAM in the
+ # range 0x80_0000_0000 - 0xFF_FFFF_FFFF (all platform and PCI MMIO is below
+ # that)
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
+
#
# ARM PrimeCell
#
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] Platforms/ARM/FVP: limit VA range to 36 bits
2016-09-09 8:15 [PATCH 1/2] Platforms/AMD/Styx: limit VA space to 40 bits Ard Biesheuvel
@ 2016-09-09 8:15 ` Ard Biesheuvel
2016-09-13 10:43 ` Leif Lindholm
2016-09-13 10:43 ` [PATCH 1/2] Platforms/AMD/Styx: limit VA space to 40 bits Leif Lindholm
1 sibling, 1 reply; 4+ messages in thread
From: Ard Biesheuvel @ 2016-09-09 8:15 UTC (permalink / raw)
To: edk2-devel, leif.lindholm; +Cc: eugene, Ard Biesheuvel
The FVP model has up to 8 GB of memory (on the Base model), where the
top 6GB starts at 0x8_8000_0000, and all other memory regions of interest
live below that. This means we can cover the whole VA space with 36-bits
worth of VA.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
index 3d8e0cfbb57e..60df45dca276 100644
--- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
+++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
@@ -175,6 +175,9 @@
# Set tick frequency value to 100Mhz
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|100000000
+ # the entire FVP address space can be covered by 36 bit VAs
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36
+
[PcdsDynamicDefault.common]
#
# The size of a dynamic PCD of the (VOID*) type can not be increased at run
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] Platforms/AMD/Styx: limit VA space to 40 bits
2016-09-09 8:15 [PATCH 1/2] Platforms/AMD/Styx: limit VA space to 40 bits Ard Biesheuvel
2016-09-09 8:15 ` [PATCH 2/2] Platforms/ARM/FVP: limit VA range to 36 bits Ard Biesheuvel
@ 2016-09-13 10:43 ` Leif Lindholm
1 sibling, 0 replies; 4+ messages in thread
From: Leif Lindholm @ 2016-09-13 10:43 UTC (permalink / raw)
To: Ard Biesheuvel; +Cc: edk2-devel, eugene
On Fri, Sep 09, 2016 at 09:15:38AM +0100, Ard Biesheuvel wrote:
> We can cover the entire MMIO range and 512 GB of memory starting at
> 0x80_0000_0000 using 40 bits of VA space, both in the page tables and
> in the GCD memory map.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 5 +++++
> Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 5 +++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc
> index 8a100e0d9a3c..0a987cc3b118 100644
> --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc
> +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc
> @@ -375,6 +375,11 @@ DEFINE DO_KCS = 0
> # Size of the region used by UEFI in permanent memory (Reserved 64MB)
> gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
>
> + # 40 bits of VA space is sufficient to support up to 512 GB of RAM in the
> + # range 0x80_0000_0000 - 0xFF_FFFF_FFFF (all platform and PCI MMIO is below
> + # that)
> + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
> +
> #
> # ARM PrimeCell
> #
> diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
> index 38c3309dcff1..72ceb8b6994e 100644
> --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
> +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc
> @@ -382,6 +382,11 @@ DEFINE DO_KCS = 1
> # Size of the region used by UEFI in permanent memory (Reserved 64MB)
> gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
>
> + # 40 bits of VA space is sufficient to support up to 512 GB of RAM in the
> + # range 0x80_0000_0000 - 0xFF_FFFF_FFFF (all platform and PCI MMIO is below
> + # that)
> + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|40
> +
> #
> # ARM PrimeCell
> #
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] Platforms/ARM/FVP: limit VA range to 36 bits
2016-09-09 8:15 ` [PATCH 2/2] Platforms/ARM/FVP: limit VA range to 36 bits Ard Biesheuvel
@ 2016-09-13 10:43 ` Leif Lindholm
0 siblings, 0 replies; 4+ messages in thread
From: Leif Lindholm @ 2016-09-13 10:43 UTC (permalink / raw)
To: Ard Biesheuvel; +Cc: edk2-devel, eugene
On Fri, Sep 09, 2016 at 09:15:39AM +0100, Ard Biesheuvel wrote:
> The FVP model has up to 8 GB of memory (on the Base model), where the
> top 6GB starts at 0x8_8000_0000, and all other memory regions of interest
> live below that. This means we can cover the whole VA space with 36-bits
> worth of VA.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
> index 3d8e0cfbb57e..60df45dca276 100644
> --- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
> +++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
> @@ -175,6 +175,9 @@
> # Set tick frequency value to 100Mhz
> gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|100000000
>
> + # the entire FVP address space can be covered by 36 bit VAs
> + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36
> +
> [PcdsDynamicDefault.common]
> #
> # The size of a dynamic PCD of the (VOID*) type can not be increased at run
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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