From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x232.google.com (mail-wm0-x232.google.com [IPv6:2a00:1450:400c:c09::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0BDF71A1DFE for ; Fri, 9 Sep 2016 02:00:48 -0700 (PDT) Received: by mail-wm0-x232.google.com with SMTP id b187so19640820wme.1 for ; Fri, 09 Sep 2016 02:00:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=M6V8RvGsvlQ7/XkudyNwmHmXNaGohYQhLyjGtgwUHZo=; b=bgyPgWxzCw0Svc5oN9ATy/ONFbHcVMFm0FAy13c0yicvSsAxKxr4VOdRttVwG8ta60 6yxUWPtIO0LPGjMCmCU3gdu8GrtClJg0Nx+iTbfwWYwOI5SgvNkRcM0B/fj+2559c3Xi xZx388zkVLEwHm5OV1MYY0PQc50G++ajp1MBY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=M6V8RvGsvlQ7/XkudyNwmHmXNaGohYQhLyjGtgwUHZo=; b=GExmzhm5KPweHPkr8m8HMwa17oBb3ZZ3I+WQQpnZkZnSW6i7X1G9SgUqrfF7d0pqXE fjA5H+ploDWYodUU/Doqd46QbBQzAPV7ZBI/iBhes17tC8tsiopGbOfyLHq1J96YnMFs UaFg+eZMT1JCOAy2cjND77hcZPhWfZkM3o3bTCQBN3CuXZ0YsjdPPH54vUWe0/L3t63K 9UvuJVIIi5R3qtG2X4Gcz90zif4VGBBNyP6sxBTqL98KbQHrPLWzlgKubBXln2t9WU/2 8alN3fBwx4g/zAe2tETvHRvg/zTFtLSZVFp0VYKD4Oqr44HMTO+L9k/1rTpwozE/0toc MXBw== X-Gm-Message-State: AE9vXwMqCDZ6V7HQ4l6O51Y8Pta16iGLdVeSB4MhYHO6vQdZkh4iZjzXSSQGcU27wZs+NxSR X-Received: by 10.28.13.149 with SMTP id 143mr1863520wmn.113.1473411646404; Fri, 09 Sep 2016 02:00:46 -0700 (PDT) Received: from localhost.localdomain ([105.190.180.180]) by smtp.gmail.com with ESMTPSA id 188sm2318045wmo.1.2016.09.09.02.00.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Sep 2016 02:00:45 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, eugene@hp.com Cc: Ard Biesheuvel Date: Fri, 9 Sep 2016 10:00:33 +0100 Message-Id: <1473411633-25763-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Subject: [PATCH] ArmPkg/ArmMmuLib: use a pool allocation for the root table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Sep 2016 09:00:48 -0000 Currently, we allocate a full page for the root translation table, even if the configured translation only requires two entries (16 bytes) for the root level, which happens to be the case for a 40 bit VA. Likewise, for a 36-bit VA space, the root table only needs 16 entries of 8 bytes each, adding up to 128 bytes. So switch to a pool allocation for the root table, but take into account that the architecture requires it to be naturally aligned to its size, i.e., a 64 byte table requires 64 byte alignment, whereas pool allocations in general are only guaranteed to be aligned to 8 bytes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 23 +++++++++++++------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index b5900a761f80..297771a42761 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -580,11 +580,12 @@ ArmConfigureMmu ( ) { VOID* TranslationTable; - UINTN TranslationTablePageCount; + VOID* TranslationTableBuffer; UINT32 TranslationTableAttribute; UINT64 MaxAddress; UINTN T0SZ; UINTN RootTableEntryCount; + UINTN RootTableEntrySize; UINT64 TCR; RETURN_STATUS Status; @@ -656,12 +657,18 @@ ArmConfigureMmu ( // Set TCR ArmSetTCR (TCR); - // Allocate pages for translation table - TranslationTablePageCount = EFI_SIZE_TO_PAGES(RootTableEntryCount * sizeof(UINT64)); - TranslationTable = (UINT64*)AllocateAlignedPages (TranslationTablePageCount, TT_ALIGNMENT_DESCRIPTION_TABLE); - if (TranslationTable == NULL) { + // Allocate pages for translation table. Pool allocations are 8 byte aligned, + // but we may require a higher alignment based on the size of the root table. + RootTableEntrySize = RootTableEntryCount * sizeof(UINT64); + TranslationTableBuffer = AllocatePool (2 * RootTableEntrySize - 8); + if (TranslationTableBuffer == NULL) { return RETURN_OUT_OF_RESOURCES; } + // + // Naturally align the root table + // + TranslationTable = (VOID *)((UINTN)(TranslationTableBuffer - 1) | (RootTableEntrySize - 1)) + 1; + // We set TTBR0 just after allocating the table to retrieve its location from the subsequent // functions without needing to pass this value across the functions. The MMU is only enabled // after the translation tables are populated. @@ -672,10 +679,10 @@ ArmConfigureMmu ( } if (TranslationTableSize != NULL) { - *TranslationTableSize = RootTableEntryCount * sizeof(UINT64); + *TranslationTableSize = RootTableEntrySize; } - ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); + ZeroMem (TranslationTable, RootTableEntrySize); // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs ArmDisableMmu (); @@ -735,7 +742,7 @@ ArmConfigureMmu ( return RETURN_SUCCESS; FREE_TRANSLATION_TABLE: - FreePages (TranslationTable, TranslationTablePageCount); + FreePool (TranslationTableBuffer); return Status; } -- 2.7.4