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From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, eugene@hp.com
Cc: heyi.guo@linaro.org, Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: [PATCH v2 1/4] ArmPkg/ArmMmuLib: deobfuscate GetRootTranslationTableInfo ()
Date: Fri,  9 Sep 2016 11:48:37 +0100	[thread overview]
Message-ID: <1473418120-31410-2-git-send-email-ard.biesheuvel@linaro.org> (raw)
In-Reply-To: <1473418120-31410-1-git-send-email-ard.biesheuvel@linaro.org>

The relations between T0SZ, the number of translation levels and the
size/alignment of the root table can be expressed in simple arithmetic
expressions, so get rid of the lookup table.

Note that this disregards the fact that the maximum value of T0SZ is
39 not 42 (as one would expect for the smallest VA size using 2 levels)
but since this corresponds to a VA size of 32 MB and 4 MB, respectively,
neither of which are sufficient to run UEFI, we can safely ignore the
distinction.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 35 +++-----------------
 1 file changed, 4 insertions(+), 31 deletions(-)

diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
index 6e05e6085011..84a689af7c8a 100644
--- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
@@ -121,20 +121,8 @@ GcdAttributeToArmAttribute (
   }
 }
 
-// Describe the T0SZ values for each translation table level
-typedef struct {
-  UINTN     MinT0SZ;
-  UINTN     MaxT0SZ;
-  UINTN     LargestT0SZ; // Generally (MaxT0SZ == LargestT0SZ) but at the Level3 Table
-                         // the MaxT0SZ is not at the boundary of the table
-} T0SZ_DESCRIPTION_PER_LEVEL;
-
-// Map table for the corresponding Level of Table
-STATIC CONST T0SZ_DESCRIPTION_PER_LEVEL T0SZPerTableLevel[] = {
-    { 16, 24, 24 }, // Table Level 0
-    { 25, 33, 33 }, // Table Level 1
-    { 34, 39, 42 }  // Table Level 2
-};
+#define MIN_T0SZ        16
+#define BITS_PER_LEVEL  9
 
 VOID
 GetRootTranslationTableInfo (
@@ -143,28 +131,13 @@ GetRootTranslationTableInfo (
   OUT UINTN   *TableEntryCount
   )
 {
-  UINTN Index;
-
-  // Identify the level of the root table from the given T0SZ
-  for (Index = 0; Index < sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL); Index++) {
-    if (T0SZ <= T0SZPerTableLevel[Index].MaxT0SZ) {
-      break;
-    }
-  }
-
-  // If we have not found the corresponding maximum T0SZ then we use the last one
-  if (Index == sizeof (T0SZPerTableLevel) / sizeof (T0SZ_DESCRIPTION_PER_LEVEL)) {
-    Index--;
-  }
-
   // Get the level of the root table
   if (TableLevel) {
-    *TableLevel = Index;
+    *TableLevel = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
   }
 
-  // The Size of the Table is 2^(T0SZ-LargestT0SZ)
   if (TableEntryCount) {
-    *TableEntryCount = 1 << (T0SZPerTableLevel[Index].LargestT0SZ - T0SZ + 1);
+    *TableEntryCount = 1UL << (BITS_PER_LEVEL - (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL);
   }
 }
 
-- 
2.7.4



  reply	other threads:[~2016-09-09 10:48 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-09 10:48 [PATCH v2 0/4] ArmPkg/ArmMmuLib: fixes and cleanups Ard Biesheuvel
2016-09-09 10:48 ` Ard Biesheuvel [this message]
2016-09-09 10:48 ` [PATCH v2 2/4] ArmPkg/ArmMmuLib: remove bogus alignment of page allocations Ard Biesheuvel
2016-09-09 10:48 ` [PATCH v2 3/4] ArmPkg/ArmMmuLib: use a pool allocation for the root table Ard Biesheuvel
2016-09-09 10:48 ` [PATCH v2 4/4] ArmPkg/ArmMmuLib: base page table VA size on GCD memory map size Ard Biesheuvel
2016-09-13 10:40 ` [PATCH v2 0/4] ArmPkg/ArmMmuLib: fixes and cleanups Leif Lindholm

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