From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22e.google.com (mail-wm0-x22e.google.com [IPv6:2a00:1450:400c:c09::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 80C071A1E6D for ; Fri, 9 Sep 2016 03:48:51 -0700 (PDT) Received: by mail-wm0-x22e.google.com with SMTP id w12so25639697wmf.0 for ; Fri, 09 Sep 2016 03:48:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HL1/jZQcKTb0j6xmSOeEUopychCrLwvmJ62PwrKMd+U=; b=MVU/9Djt1uKghNQ+ynVB3cuajY0q1F/7jKt8zi8/+g9xMgidDC5dLkcJvlHFGgQTKQ wwjIN6pBNRgHZkaU1gXYDLXB8NCgT6NoVc3t2l+pj1ZXHyQkISaYCxt58Oi8kWS4J5ty +A9PziskZGKeMD/F4MM6FZlZSvG/My9H6MOEQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HL1/jZQcKTb0j6xmSOeEUopychCrLwvmJ62PwrKMd+U=; b=ik7LvCff/BKCCN7t8b/dNI5vSIxOedGtQbXYZYhGz5IOwRirg/SZDuTQ2CUK/UmKof tu9rwoJqPkwsyMSPeJhL0qNNPPz//gmX0Gb9+f59W/rj3pBl7VY2JmV1oNjQ1Ndr5KQu 5Wb+aNn+SPHu34O2/8cKgbcrLuWGT6MGW2ZpzmJRk0HC7zeYGBMKnk74EAyvw/DqVAv3 U9QonNdVa9vHdxBoCKNIi80uigBlO5UIXo4lg8mN0LTRWEperekPcFceAyylrwvvSth6 3aVeG6hdp/7F0Rjd0K9oAbOEyXUxFUeNLAh4LVlxMJeUxmo9W9BvspUJYSapf7Usk/Fx +qIQ== X-Gm-Message-State: AE9vXwPzGmzvF7Rbg7CeORyW9eNl2BAV1VnA1FY7kn+g00PMG8hx9mqLIOupoJvTXCyGKZyx X-Received: by 10.28.30.14 with SMTP id e14mr2441312wme.93.1473418130088; Fri, 09 Sep 2016 03:48:50 -0700 (PDT) Received: from localhost.localdomain ([105.190.180.180]) by smtp.gmail.com with ESMTPSA id z4sm2716580wmg.19.2016.09.09.03.48.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Sep 2016 03:48:49 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, eugene@hp.com Cc: heyi.guo@linaro.org, Ard Biesheuvel Date: Fri, 9 Sep 2016 11:48:38 +0100 Message-Id: <1473418120-31410-3-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473418120-31410-1-git-send-email-ard.biesheuvel@linaro.org> References: <1473418120-31410-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH v2 2/4] ArmPkg/ArmMmuLib: remove bogus alignment of page allocations X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Sep 2016 10:48:51 -0000 In commit 7d189f99d81c ("ArmPkg/Mmu: Fix bug of aligning new allocated page table"), we fixed a flaw in the logic regarding alignment of newly allocated translation table pages. However, we all failed to spot that aligning page based allocations to page size is rather pointless to begin with, so simply allocate a single page each time we add new pages to the translation tables. Also, drop the unnecessary cast. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 84a689af7c8a..1ff584ec9eec 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -298,7 +298,7 @@ GetBlockEntryListFromAddress ( } // Create a new translation table - TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE); + TranslationTable = AllocatePages (1); if (TranslationTable == NULL) { return NULL; } @@ -321,7 +321,7 @@ GetBlockEntryListFromAddress ( // // Create a new translation table - TranslationTable = (UINT64*)AllocateAlignedPages (EFI_SIZE_TO_PAGES(TT_ENTRY_COUNT * sizeof(UINT64)), TT_ALIGNMENT_DESCRIPTION_TABLE); + TranslationTable = AllocatePages (1); if (TranslationTable == NULL) { return NULL; } @@ -553,7 +553,6 @@ ArmConfigureMmu ( ) { VOID* TranslationTable; - UINTN TranslationTablePageCount; UINT32 TranslationTableAttribute; ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry; UINT64 MaxAddress; @@ -640,8 +639,7 @@ ArmConfigureMmu ( ArmSetTCR (TCR); // Allocate pages for translation table - TranslationTablePageCount = EFI_SIZE_TO_PAGES(RootTableEntryCount * sizeof(UINT64)); - TranslationTable = (UINT64*)AllocateAlignedPages (TranslationTablePageCount, TT_ALIGNMENT_DESCRIPTION_TABLE); + TranslationTable = AllocatePages (1); if (TranslationTable == NULL) { return RETURN_OUT_OF_RESOURCES; } @@ -718,7 +716,7 @@ ArmConfigureMmu ( return RETURN_SUCCESS; FREE_TRANSLATION_TABLE: - FreePages (TranslationTable, TranslationTablePageCount); + FreePages (TranslationTable, 1); return Status; } -- 2.7.4