From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x230.google.com (mail-wm0-x230.google.com [IPv6:2a00:1450:400c:c09::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3F4A31A1E70 for ; Fri, 9 Sep 2016 03:48:53 -0700 (PDT) Received: by mail-wm0-x230.google.com with SMTP id 1so25529185wmz.1 for ; Fri, 09 Sep 2016 03:48:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V2a/1Th59eyVS9NPlHx7+owE8K6BIJ9r4INOASDg2Vs=; b=aNvp9+S5GWvm54hXrcitALzj/434+VCrC0SvtQ4qaO4ysSRX/zwi5nFkxDU75TBmGH KihyN/y4Dboc5fQlUGDSFrxxlafRVZXHdOoFL0alo7c1cZco93LRLdzCcO4sV89ktcZ3 FwBnUzRdyfqa1jtdZYDgMKcIfTYt/ZCnHzt2Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V2a/1Th59eyVS9NPlHx7+owE8K6BIJ9r4INOASDg2Vs=; b=PHbY7IGVzEIU11cetkz+nSIL51Pyn8f0DZPdT7waUcy/ryaYepMLByqxHvXlSB66Fn LIlc3pSZzmWX7L4F5ypLojQZ/owVfMeHdQJU7EBUkFNKXYX4JBZGRlJ5f9KlgptE+WpA x8aZgigXDv+Qb/22zMm5nkz/CTfh1ems8V0J5l+On2WePTplJfYWOkEestRyizfc9zA9 FLB2tvnIrbVdIkWH3RuZiqbOi/2kq9T0CPjGDhslB9ebh1CHqbYPixZZOqvUyySbu2Tg SrgNptdp2uvoJvV+rm1+1zO/ioW9rmKpBMrQS0tq3Dtb5yPU/DEWmQVPR3/Y4LgvkH28 2WJQ== X-Gm-Message-State: AE9vXwMrNDPxhv+bupNbaRUxcRVqjciDSz4g/+rpHMCIVdYnQmvIxGOm49LXNy84KZYjArUT X-Received: by 10.194.73.9 with SMTP id h9mr1110056wjv.21.1473418131656; Fri, 09 Sep 2016 03:48:51 -0700 (PDT) Received: from localhost.localdomain ([105.190.180.180]) by smtp.gmail.com with ESMTPSA id z4sm2716580wmg.19.2016.09.09.03.48.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Sep 2016 03:48:51 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, eugene@hp.com Cc: heyi.guo@linaro.org, Ard Biesheuvel Date: Fri, 9 Sep 2016 11:48:39 +0100 Message-Id: <1473418120-31410-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473418120-31410-1-git-send-email-ard.biesheuvel@linaro.org> References: <1473418120-31410-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH v2 3/4] ArmPkg/ArmMmuLib: use a pool allocation for the root table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Sep 2016 10:48:53 -0000 Currently, we allocate a full page for the root translation table, even if the configured translation only requires two entries (16 bytes) for the root level, which happens to be the case for a 40 bit VA. Likewise, for a 36-bit VA space, the root table only needs 16 entries of 8 bytes each, adding up to 128 bytes. So switch to a pool allocation for the root table if we can, but take into account that the architecture requires it to be naturally aligned to its size, i.e., a 64 byte table requires 64 byte alignment, whereas pool allocations in general are only guaranteed to be aligned to 8 bytes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 27 ++++++++++++++++---- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 1ff584ec9eec..57e789f68b3b 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -553,12 +553,14 @@ ArmConfigureMmu ( ) { VOID* TranslationTable; + VOID* TranslationTableBuffer; UINT32 TranslationTableAttribute; ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry; UINT64 MaxAddress; UINT64 TopAddress; UINTN T0SZ; UINTN RootTableEntryCount; + UINTN RootTableEntrySize; UINT64 TCR; RETURN_STATUS Status; @@ -638,8 +640,19 @@ ArmConfigureMmu ( // Set TCR ArmSetTCR (TCR); - // Allocate pages for translation table - TranslationTable = AllocatePages (1); + // Allocate pages for translation table. Pool allocations are 8 byte aligned, + // but we may require a higher alignment based on the size of the root table. + RootTableEntrySize = RootTableEntryCount * sizeof(UINT64); + if (RootTableEntrySize < EFI_PAGE_SIZE / 2) { + TranslationTableBuffer = AllocatePool (2 * RootTableEntrySize - 8); + // + // Naturally align the root table. Preserves possible NULL value + // + TranslationTable = (VOID *)((UINTN)(TranslationTableBuffer - 1) | (RootTableEntrySize - 1)) + 1; + } else { + TranslationTable = AllocatePages (1); + TranslationTableBuffer = NULL; + } if (TranslationTable == NULL) { return RETURN_OUT_OF_RESOURCES; } @@ -653,10 +666,10 @@ ArmConfigureMmu ( } if (TranslationTableSize != NULL) { - *TranslationTableSize = RootTableEntryCount * sizeof(UINT64); + *TranslationTableSize = RootTableEntrySize; } - ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); + ZeroMem (TranslationTable, RootTableEntrySize); // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs ArmDisableMmu (); @@ -716,7 +729,11 @@ ArmConfigureMmu ( return RETURN_SUCCESS; FREE_TRANSLATION_TABLE: - FreePages (TranslationTable, 1); + if (TranslationTableBuffer != NULL) { + FreePool (TranslationTableBuffer); + } else { + FreePages (TranslationTable, 1); + } return Status; } -- 2.7.4