From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x232.google.com (mail-wm0-x232.google.com [IPv6:2a00:1450:400c:c09::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D04AD1A1E76 for ; Fri, 9 Sep 2016 03:48:54 -0700 (PDT) Received: by mail-wm0-x232.google.com with SMTP id 1so25530256wmz.1 for ; Fri, 09 Sep 2016 03:48:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=twI6eb+n3k2cB8WHJZgsMW0FOX1b00+SrF+4D9EvEHw=; b=GoqhOSVcHsrR4jcUfjMiytQOihoFzp0mV2R9Y5XLPCCIKnhTCUQk8jzdwbn1DgH8l8 BnsXip2AEYfE17M+JhkRdL86VSK1wam8UBcX7VXvMg7XU6cJxF+irWAE/qcYh74oOnSQ nMjE44f0lWd8MZj0dcgGdSVRmX5vG5+lTgXwc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=twI6eb+n3k2cB8WHJZgsMW0FOX1b00+SrF+4D9EvEHw=; b=F6OG/5RygW29aWm4OxT0QloJrSjYaHIaY4dTeedGP/tuQ3WUFbVRGhLtXuk9JIAZ+q KWnXslh/pT4n1PevgVNXWR3eZDBOsXjwUlSabW2CXVwmLzi+uBhFezd+IbuDuJnO3rVz FSmAC9VjHlVkKjecNDqHuE//0JbcRQFzXYilTsyx6Hf2m+rHeaLweuMLiS5fi4bZyCDV 65CGWirkObRwGHlxE7GMSUbpUDxVnRRjnDuYa2TorWumM/HxkJPOe/fh4Rk+eyYSeasI 10TaqFUUe2IdXFSdzYrwvd7ko3uLnlN/9Y9XOcqAhu8hJEuppNeIaJPoMu6zqcPkrRpp Pd1g== X-Gm-Message-State: AE9vXwO1rk87n+o14ul6Y4RsyZlwqX//7/oNnl7+Hujo3lBrP8EyU5S1kuPKyiy/ManitkAa X-Received: by 10.28.74.217 with SMTP id n86mr2464670wmi.84.1473418133253; Fri, 09 Sep 2016 03:48:53 -0700 (PDT) Received: from localhost.localdomain ([105.190.180.180]) by smtp.gmail.com with ESMTPSA id z4sm2716580wmg.19.2016.09.09.03.48.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Sep 2016 03:48:52 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, eugene@hp.com Cc: heyi.guo@linaro.org, Ard Biesheuvel Date: Fri, 9 Sep 2016 11:48:40 +0100 Message-Id: <1473418120-31410-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473418120-31410-1-git-send-email-ard.biesheuvel@linaro.org> References: <1473418120-31410-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH v2 4/4] ArmPkg/ArmMmuLib: base page table VA size on GCD memory map size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Sep 2016 10:48:55 -0000 As reported by Eugene, the practice of sizing the address space in the virtual memory system based on the maximum address in the table passed to ArmConfigureMmu() is problematic, since it fails to take into account the fact that the GCD memory space may be extended at a later time, both for memory and for MMIO. So instead, choose the VA size identical to the GCD memory map size, which is based on PcdPrePiCpuMemorySize on ARM systems. Reported-by: Eugene Cohen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 14 ++------------ ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 4 ++++ ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf | 4 ++++ 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 57e789f68b3b..1fb3bbec6347 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -555,9 +555,7 @@ ArmConfigureMmu ( VOID* TranslationTable; VOID* TranslationTableBuffer; UINT32 TranslationTableAttribute; - ARM_MEMORY_REGION_DESCRIPTOR *MemoryTableEntry; UINT64 MaxAddress; - UINT64 TopAddress; UINTN T0SZ; UINTN RootTableEntryCount; UINTN RootTableEntrySize; @@ -569,16 +567,8 @@ ArmConfigureMmu ( return RETURN_INVALID_PARAMETER; } - // Identify the highest address of the memory table - MaxAddress = MemoryTable->PhysicalBase + MemoryTable->Length - 1; - MemoryTableEntry = MemoryTable; - while (MemoryTableEntry->Length != 0) { - TopAddress = MemoryTableEntry->PhysicalBase + MemoryTableEntry->Length - 1; - if (TopAddress > MaxAddress) { - MaxAddress = TopAddress; - } - MemoryTableEntry++; - } + // Cover the entire GCD memory space + MaxAddress = (1UL << PcdGet8 (PcdPrePiCpuMemorySize)) - 1; // Lookup the Table Level to get the information LookupAddresstoRootTable (MaxAddress, &T0SZ, &RootTableEntryCount); diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf index 1533c2944e8e..b9f264de8d26 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf @@ -32,6 +32,7 @@ [Sources.ARM] [Packages] ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec [LibraryClasses] @@ -39,5 +40,8 @@ [LibraryClasses] CacheMaintenanceLib MemoryAllocationLib +[Pcd.AARCH64] + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize + [Pcd.ARM] gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf b/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf index 14ebf8de673d..ecf13f790734 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf @@ -28,9 +28,13 @@ [Sources.AARCH64] [Packages] ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec [LibraryClasses] ArmLib CacheMaintenanceLib MemoryAllocationLib + +[Pcd.AARCH64] + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize -- 2.7.4