From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9AA6B1A1EE1 for ; Tue, 20 Sep 2016 23:47:17 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 20 Sep 2016 23:47:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,372,1470726000"; d="scan'208";a="1059859292" Received: from jyao1-mobl.ccr.corp.intel.com ([10.239.192.109]) by fmsmga002.fm.intel.com with ESMTP; 20 Sep 2016 23:47:14 -0700 From: Jiewen Yao To: edk2-devel@lists.01.org Cc: Michael D Kinney , Kelly Steele , Feng Tian , Star Zeng , Liming Gao , Chao Zhang Date: Wed, 21 Sep 2016 14:45:12 +0800 Message-Id: <1474440326-9292-32-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1474440326-9292-1-git-send-email-jiewen.yao@intel.com> References: <1474440326-9292-1-git-send-email-jiewen.yao@intel.com> Subject: [PATCH 31/45] QuarkPlatformPkg/PlatformFlashAccessLib: Add instance for capsule update. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Sep 2016 06:47:17 -0000 Add PlatformFlashAccessLib for capsule update. Cc: Michael D Kinney Cc: Kelly Steele Cc: Feng Tian Cc: Star Zeng Cc: Liming Gao Cc: Chao Zhang Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao --- QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c | 200 ++++++++++++ QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf | 52 +++ QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.c | 336 ++++++++++++++++++++ QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.h | 186 +++++++++++ 4 files changed, 774 insertions(+) diff --git a/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c b/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c new file mode 100644 index 0000000..3ad30b1 --- /dev/null +++ b/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c @@ -0,0 +1,200 @@ +/** @file + Platform Flash Access library. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +// +// SPI default opcode slots +// +#define SPI_OPCODE_JEDEC_ID_INDEX 0 +#define SPI_OPCODE_READ_ID_INDEX 1 +#define SPI_OPCODE_WRITE_S_INDEX 2 +#define SPI_OPCODE_WRITE_INDEX 3 +#define SPI_OPCODE_READ_INDEX 4 +#define SPI_OPCODE_ERASE_INDEX 5 +#define SPI_OPCODE_READ_S_INDEX 6 +#define SPI_OPCODE_CHIP_ERASE_INDEX 7 + +#define SPI_ERASE_SECTOR_SIZE SIZE_4KB //This is the chipset requirement + +STATIC EFI_PHYSICAL_ADDRESS mInternalFdAddress; +EFI_SPI_PROTOCOL *mSpiProtocol; + +/** + Writes specified number of bytes from the input buffer to the address + + @param WriteAddress The flash address to be written. + @param NumBytes The number of bytes. + @param Buffer The data buffer to be written. + + @return The status of flash write. +**/ +EFI_STATUS +FlashFdWrite ( + IN UINTN WriteAddress, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + + Status = EFI_SUCCESS; + + Status = mSpiProtocol->Execute ( + mSpiProtocol, + SPI_OPCODE_WRITE_INDEX, // OpcodeIndex + 0, // PrefixOpcodeIndex + TRUE, // DataCycle + TRUE, // Atomic + TRUE, // ShiftOut + WriteAddress, // Address + (UINT32) (*NumBytes), // Data Number + Buffer, + EnumSpiRegionBios + ); + DEBUG((EFI_D_INFO, "FlashFdWrite - 0x%x - %r\n", (UINTN)WriteAddress, Status)); + + AsmWbinvd (); + + return Status; +} + +/** + Erase a certain block from address LbaWriteAddress + + @param WriteAddress The flash address to be erased. + + @return The status of flash erase. +**/ +EFI_STATUS +FlashFdErase ( + IN UINTN WriteAddress + ) +{ + EFI_STATUS Status; + + Status = mSpiProtocol->Execute ( + mSpiProtocol, + SPI_OPCODE_ERASE_INDEX, // OpcodeIndex + 0, // PrefixOpcodeIndex + FALSE, // DataCycle + TRUE, // Atomic + FALSE, // ShiftOut + WriteAddress, // Address + 0, // Data Number + NULL, + EnumSpiRegionBios // SPI_REGION_TYPE + ); + DEBUG((EFI_D_INFO, "FlashFdErase - 0x%x - %r\n", (UINTN)WriteAddress, Status)); + + AsmWbinvd (); + + return Status; +} + +/** + Perform flash write opreation. + + @param FirmwareType The type of firmware. + @param FlashAddress The address of flash device to be accessed. + @param FlashAddressType The type of flash device address. + @param Buffer The pointer to the data buffer. + @param Length The length of data buffer in bytes. + + @retval EFI_SUCCESS The operation returns successfully. + @retval EFI_WRITE_PROTECTED The flash device is read only. + @retval EFI_UNSUPPORTED The flash device access is unsupported. + @retval EFI_INVALID_PARAMETER The input parameter is not valid. +**/ +EFI_STATUS +EFIAPI +PerformFlashWrite( + IN PLATFORM_FIRMWARE_TYPE FirmwareType, + IN EFI_PHYSICAL_ADDRESS FlashAddress, + IN FLASH_ADDRESS_TYPE FlashAddressType, + IN VOID *Buffer, + IN UINTN Length + ) +{ + EFI_STATUS Status; + UINTN SectorNum; + UINTN Index; + UINTN NumBytes; + + DEBUG((EFI_D_INFO, "PerformFlashWrite - 0x%x(%x) - 0x%x\n", (UINTN)FlashAddress, (UINTN)FlashAddressType, Length)); + if (FirmwareType >= PlatformFirmwareTypeMax) { + return EFI_UNSUPPORTED; + } + if (FlashAddressType == FlashAddressTypeAbsoluteAddress) { + FlashAddress = FlashAddress - mInternalFdAddress; + } + + // + // Erase & Write + // + SectorNum = Length / SPI_ERASE_SECTOR_SIZE; + for (Index = 0; Index < SectorNum; Index++){ + Status = FlashFdErase ( + (UINTN)FlashAddress + Index * SPI_ERASE_SECTOR_SIZE + ); + if (Status != EFI_SUCCESS){ + break; + } + NumBytes = SPI_ERASE_SECTOR_SIZE; + Status = FlashFdWrite ( + (UINTN)FlashAddress + Index * SPI_ERASE_SECTOR_SIZE, + &NumBytes, + (UINT8 *)Buffer + Index * SPI_ERASE_SECTOR_SIZE + ); + if (Status != EFI_SUCCESS){ + break; + } + } + + return EFI_SUCCESS; +} + +/** + Platform Flash Access Lib Constructor. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS Constructor returns successfully. +**/ +EFI_STATUS +EFIAPI +PerformFlashAccessLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mInternalFdAddress = FixedPcdGet64(PcdFlashAreaBaseAddress); + DEBUG((EFI_D_INFO, "PcdFlashAreaBaseAddress - 0x%x\n", mInternalFdAddress)); + + Status = gBS->LocateProtocol(&gEfiSpiProtocolGuid, NULL, (VOID **)&mSpiProtocol); + ASSERT_EFI_ERROR(Status); + + return EFI_SUCCESS; +} diff --git a/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf b/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf new file mode 100644 index 0000000..2099bf6 --- /dev/null +++ b/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf @@ -0,0 +1,52 @@ +## @file +# Platform Flash Access library. +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformFlashAccessLibDxe + FILE_GUID = 9168384A-5F66-4CF7-AEB6-845BDEBD3012 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformFlashAccessLib|DXE_DRIVER DXE_RUNTIME_DRIVER + CONSTRUCTOR = PerformFlashAccessLibConstructor + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources] + PlatformFlashAccessLibDxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + QuarkSocPkg/QuarkSocPkg.dec + QuarkPlatformPkg/QuarkPlatformPkg.dec + +[LibraryClasses] + BaseMemoryLib + PcdLib + DebugLib + UefiBootServicesTableLib + +[Protocols] + gEfiSpiProtocolGuid + +[FixedPcd] + gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress + +[Depex] + gEfiSpiProtocolGuid diff --git a/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.c b/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.c new file mode 100644 index 0000000..e2827b9 --- /dev/null +++ b/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.c @@ -0,0 +1,336 @@ +/** @file + SPI flash device description. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + +**/ + +#include "SpiFlashDevice.h" + +#define FLASH_SIZE (FixedPcdGet32 (PcdFlashAreaSize)) + +SPI_INIT_TABLE mSpiInitTable[] = { + // + // Macronix 32Mbit part + // + { + SPI_MX25L3205_ID1, + SPI_MX25L3205_ID2, + SPI_MX25L3205_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Winbond 32Mbit part + // + { + SPI_W25X32_ID1, + SF_DEVICE_ID0_W25QXX, + SF_DEVICE_ID1_W25Q32, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Winbond 32Mbit part + // + { + SPI_W25X32_ID1, + SPI_W25X32_ID2, + SPI_W25X32_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Atmel 32Mbit part + // + { + SPI_AT26DF321_ID1, + SPI_AT26DF321_ID2, // issue: byte 2 identifies family/density for Atmel + SPI_AT26DF321_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + + // + // Intel 32Mbit part bottom boot + // + { + SPI_QH25F320_ID1, + SPI_QH25F320_ID2, + SPI_QH25F320_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_ENABLE + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + 0, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // SST 64Mbit part + // + { + SPI_SST25VF080B_ID1, // VendorId + SF_DEVICE_ID0_25VF064C, // DeviceId 0 + SF_DEVICE_ID1_25VF064C, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // NUMONYX 64Mbit part + // + { + SF_VENDOR_ID_NUMONYX, // VendorId + SF_DEVICE_ID0_M25PX64, // DeviceId 0 + SF_DEVICE_ID1_M25PX64, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Atmel 64Mbit part + // + { + SF_VENDOR_ID_ATMEL, // VendorId + SF_DEVICE_ID0_AT25DF641, // DeviceId 0 + SF_DEVICE_ID1_AT25DF641, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + + // + // Spansion 64Mbit part + // + { + SF_VENDOR_ID_SPANSION, // VendorId + SF_DEVICE_ID0_S25FL064K, // DeviceId 0 + SF_DEVICE_ID1_S25FL064K, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + + // + // Macronix 64Mbit part bottom boot + // + { + SF_VENDOR_ID_MX, // VendorId + SF_DEVICE_ID0_25L6405D, // DeviceId 0 + SF_DEVICE_ID1_25L6405D, // DeviceId 1 + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Winbond 64Mbit part bottom boot + // + { + SPI_W25X64_ID1, + SF_DEVICE_ID0_W25QXX, + SF_DEVICE_ID1_W25Q64, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Winbond 64Mbit part bottom boot + // + { + SPI_W25X64_ID1, + SPI_W25X64_ID2, + SPI_W25X64_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + }, + // + // Intel 64Mbit part bottom boot + // + { + SPI_QH25F640_ID1, + SPI_QH25F640_ID2, + SPI_QH25F640_ID3, + { + SPI_COMMAND_WRITE_ENABLE, + SPI_COMMAND_WRITE_S_EN + }, + { + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus}, + {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte}, + {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData}, + {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte}, + {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus}, + {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase} + }, + 0x800000 - FLASH_SIZE, // BIOS Start Offset + FLASH_SIZE // BIOS image size in flash + } +}; diff --git a/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.h b/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.h new file mode 100644 index 0000000..298ecfa --- /dev/null +++ b/QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlashDevice.h @@ -0,0 +1,186 @@ +/** @file + SPI flash device header file. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SPI_FLASH_DEVICE_H_ +#define _SPI_FLASH_DEVICE_H_ + +#include +#include +#include + +// +// Supported SPI Flash Devices +// +typedef enum { + EnumSpiFlash25L3205D, // Macronix 32Mbit part + EnumSpiFlashW25Q32, // Winbond 32Mbit part + EnumSpiFlashW25X32, // Winbond 32Mbit part + EnumSpiFlashAT25DF321, // Atmel 32Mbit part + EnumSpiFlashQH25F320, // Intel 32Mbit part + EnumSpiFlash25VF064C, // SST 64Mbit part + EnumSpiFlashM25PX64, // NUMONYX 64Mbit part + EnumSpiFlashAT25DF641, // Atmel 64Mbit part + EnumSpiFlashS25FL064K, // Spansion 64Mbit part + EnumSpiFlash25L6405D, // Macronix 64Mbit part + EnumSpiFlashW25Q64, // Winbond 64Mbit part + EnumSpiFlashW25X64, // Winbond 64Mbit part + EnumSpiFlashQH25F640, // Intel 64Mbit part + EnumSpiFlashMax +} SPI_FLASH_TYPES_SUPPORTED; + +// +// Flash Device commands +// +// If a supported device uses a command different from the list below, a device specific command +// will be defined just below it's JEDEC id section. +// +#define SPI_COMMAND_WRITE 0x02 +#define SPI_COMMAND_WRITE_AAI 0xAD +#define SPI_COMMAND_READ 0x03 +#define SPI_COMMAND_ERASE 0x20 +#define SPI_COMMAND_WRITE_DISABLE 0x04 +#define SPI_COMMAND_READ_S 0x05 +#define SPI_COMMAND_WRITE_ENABLE 0x06 +#define SPI_COMMAND_READ_ID 0xAB +#define SPI_COMMAND_JEDEC_ID 0x9F +#define SPI_COMMAND_WRITE_S_EN 0x50 +#define SPI_COMMAND_WRITE_S 0x01 +#define SPI_COMMAND_CHIP_ERASE 0xC7 +#define SPI_COMMAND_BLOCK_ERASE 0xD8 + +// +// Flash JEDEC device ids +// +// SST 8Mbit part +// +#define SPI_SST25VF080B_ID1 0xBF +#define SPI_SST25VF080B_ID2 0x25 +#define SPI_SST25VF080B_ID3 0x8E +// +// SST 16Mbit part +// +#define SPI_SST25VF016B_ID1 0xBF +#define SPI_SST25VF016B_ID2 0x25 +#define SPI_SST25V016BF_ID3 0x41 +// +// Macronix 32Mbit part +// +// MX25 part does not support WRITE_AAI comand (0xAD) +// +#define SPI_MX25L3205_ID1 0xC2 +#define SPI_MX25L3205_ID2 0x20 +#define SPI_MX25L3205_ID3 0x16 +// +// Intel 32Mbit part bottom boot +// +#define SPI_QH25F320_ID1 0x89 +#define SPI_QH25F320_ID2 0x89 +#define SPI_QH25F320_ID3 0x12 // 32Mbit bottom boot +// +// Intel 64Mbit part bottom boot +// +#define SPI_QH25F640_ID1 0x89 +#define SPI_QH25F640_ID2 0x89 +#define SPI_QH25F640_ID3 0x13 // 64Mbit bottom boot +// +// QH part does not support command 0x20 for erase; only 0xD8 (sector erase) +// QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part) +// 0x40 command ignored if address outside of parameter block range +// +#define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40 +// +// Winbond 32Mbit part +// +#define SPI_W25X32_ID1 0xEF +#define SPI_W25X32_ID2 0x30 // Memory Type +#define SPI_W25X32_ID3 0x16 // Capacity +#define SF_DEVICE_ID1_W25Q32 0x16 + +// +// Winbond 64Mbit part +// +#define SPI_W25X64_ID1 0xEF +#define SPI_W25X64_ID2 0x30 // Memory Type +#define SPI_W25X64_ID3 0x17 // Capacity +#define SF_DEVICE_ID0_W25QXX 0x40 +#define SF_DEVICE_ID1_W25Q64 0x17 +// +// Winbond 128Mbit part +// +#define SF_DEVICE_ID0_W25Q128 0x40 +#define SF_DEVICE_ID1_W25Q128 0x18 + +// +// Atmel 32Mbit part +// +#define SPI_AT26DF321_ID1 0x1F +#define SPI_AT26DF321_ID2 0x47 // [7:5]=Family, [4:0]=Density +#define SPI_AT26DF321_ID3 0x00 + +#define SF_VENDOR_ID_ATMEL 0x1F +#define SF_DEVICE_ID0_AT25DF641 0x48 +#define SF_DEVICE_ID1_AT25DF641 0x00 + +// +// SST 8Mbit part +// +#define SPI_SST25VF080B_ID1 0xBF +#define SPI_SST25VF080B_ID2 0x25 +#define SPI_SST25VF080B_ID3 0x8E +#define SF_DEVICE_ID0_25VF064C 0x25 +#define SF_DEVICE_ID1_25VF064C 0x4B + +// +// SST 16Mbit part +// +#define SPI_SST25VF016B_ID1 0xBF +#define SPI_SST25VF016B_ID2 0x25 +#define SPI_SST25V016BF_ID3 0x41 + +// +// Winbond 32Mbit part +// +#define SPI_W25X32_ID1 0xEF +#define SPI_W25X32_ID2 0x30 // Memory Type +#define SPI_W25X32_ID3 0x16 // Capacity + +#define SF_VENDOR_ID_MX 0xC2 +#define SF_DEVICE_ID0_25L6405D 0x20 +#define SF_DEVICE_ID1_25L6405D 0x17 + +#define SF_VENDOR_ID_NUMONYX 0x20 +#define SF_DEVICE_ID0_M25PX64 0x71 +#define SF_DEVICE_ID1_M25PX64 0x17 + +// +// Spansion 64Mbit part +// +#define SF_VENDOR_ID_SPANSION 0xEF +#define SF_DEVICE_ID0_S25FL064K 0x40 +#define SF_DEVICE_ID1_S25FL064K 0x00 + +// +// index for prefix opcodes +// +#define SPI_WREN_INDEX 0 // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE +#define SPI_EWSR_INDEX 1 // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN +#define BIOS_CTRL 0xDC + +#define PFAB_CARD_DEVICE_ID 0x5150 +#define PFAB_CARD_VENDOR_ID 0x8086 +#define PFAB_CARD_SETUP_REGISTER 0x40 +#define PFAB_CARD_SETUP_BYTE 0x0d + + +#endif -- 2.7.4.windows.1