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Ip=[217.140.96.140]; Helo=[nebula.arm.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB1118 X-MC-Unique: FAJCJVH_PiGui9h_PZ17KQ-1 Subject: [PATCH] ArmPkg ArmVirtPkg: fix the GIC base address variables as 64-bit X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 17 Oct 2016 05:03:35 -0000 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Since ACPI spec defines the GIC base addresses (CPU interface, Distributor and Redistributor*GICv3 only*) as 64-bit, so we should define these corresponding base address variables as 64-bit instead of 32-bit. This patch redefines them according to the ACPI spec. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Ard Biesheuvel Cc: Leif Lindholm Signed-off-by: Dennis Chen --- ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 4 ++-- ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/Arm= Gic/GicV2/ArmGicV2Dxe.c index b9ecd55..a4ba5cf 100644 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c @@ -30,8 +30,8 @@ Abstract: =20 extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol; =20 -STATIC UINT32 mGicInterruptInterfaceBase; -STATIC UINT32 mGicDistributorBase; +STATIC UINTN mGicInterruptInterfaceBase; +STATIC UINTN mGicDistributorBase; =20 /** Enable interrupt source Source. diff --git a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c b/Arm= VirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c index 64afc4d..16683ef 100644 --- a/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c +++ b/ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.c @@ -79,11 +79,11 @@ ArmVirtGicArchLibConstructor ( =20 // RegProp[0..1] =3D=3D { GICD base, GICD size } DistBase =3D SwapBytes64 (Reg[0]); - ASSERT (DistBase < MAX_UINT32); + ASSERT (DistBase < MAX_UINT64); =20 // RegProp[2..3] =3D=3D { GICR base, GICR size } RedistBase =3D SwapBytes64 (Reg[2]); - ASSERT (RedistBase < MAX_UINT32); + ASSERT (RedistBase < MAX_UINT64); =20 PcdSet64 (PcdGicDistributorBase, DistBase); PcdSet64 (PcdGicRedistributorsBase, RedistBase); @@ -117,8 +117,8 @@ ArmVirtGicArchLibConstructor ( =20 DistBase =3D SwapBytes64 (Reg[0]); CpuBase =3D SwapBytes64 (Reg[2]); - ASSERT (DistBase < MAX_UINT32); - ASSERT (CpuBase < MAX_UINT32); + ASSERT (DistBase < MAX_UINT64); + ASSERT (CpuBase < MAX_UINT64); =20 PcdSet64 (PcdGicDistributorBase, DistBase); PcdSet64 (PcdGicInterruptInterfaceBase, CpuBase); --=20 2.7.4