From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x235.google.com (mail-wm0-x235.google.com [IPv6:2a00:1450:400c:c09::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7E83581D23 for ; Mon, 31 Oct 2016 11:13:23 -0700 (PDT) Received: by mail-wm0-x235.google.com with SMTP id p190so163187927wmp.1 for ; Mon, 31 Oct 2016 11:13:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5Lek3C+0XVRCnCaUDy8csyHz192YCYRtAvjCAM4rxK8=; b=atyZQ1iuZmf+E3dwK2esqhBzEhJP0LBrhtidku5mf9ouEL+QU+um4tighm2AYM5der LJJHgcoS7GJ5UqHmAHqpxS5AOf4M75ubUPu+JCc5x2+x1H/kmZkJtDqm5n5D+e8/kbmS n92iXy6PKPI5wteXU5u5L+wSaPRs+lkgQcOxE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5Lek3C+0XVRCnCaUDy8csyHz192YCYRtAvjCAM4rxK8=; b=UHQV24nEjUH0dW6MBSqwW88L9oFLVbMGzJnYMeGRpYF8H0WB4SDxCLfCW27jJ/oEOb jk26dPLZ+Im/h41iS0RtsHn1wnXNk1BVCqLtypmGasfYESRNmXUqrNBseTyKSMzm8dyP TV5SS+RZ/z00Y9JM3HwNR798ifLV0vZQuLGSJVIPkWKpkd2GttCxv5VBXSQQD3Z2ODuc 8KmLHyKm2rclSqQpFJ6biLmUduoZ2hysAmqmDiflFllgwezyBdHSUTfETb33lv+x2Qch uHYk02yxgObLCSIdyjyCd7QTAaWYZ4FoEDqJXLTCcxwkZqRfnCuw4Z9IbIX+kudNTWck yCgw== X-Gm-Message-State: ABUngvdIdDRcr/3bMR4zuEHSA+10Uln86UDad95hy7JQSngFi8wcG2cA1nvEjTR1D7aVjrvt X-Received: by 10.194.112.196 with SMTP id is4mr931471wjb.92.1477937602975; Mon, 31 Oct 2016 11:13:22 -0700 (PDT) Received: from localhost.localdomain ([105.151.153.127]) by smtp.gmail.com with ESMTPSA id 132sm26054809wmn.16.2016.10.31.11.13.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 31 Oct 2016 11:13:22 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Cc: Ard Biesheuvel Date: Mon, 31 Oct 2016 18:13:09 +0000 Message-Id: <1477937590-10361-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477937590-10361-1-git-send-email-ard.biesheuvel@linaro.org> References: <1477937590-10361-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH 4/5] ArmPkg/CpuDxe: set DmaBufferAlignment according to CWG X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 31 Oct 2016 18:13:23 -0000 The DmaBufferAlignment currently defaults to 4, which is dangerously small and may result in lost data on platform that perform non-coherent DMA. So instead, take the CWG value from the cache info registers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/CpuDxe.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c index d089cb2d119f..ddc64fd255a0 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c @@ -225,7 +225,7 @@ EFI_CPU_ARCH_PROTOCOL mCpu = { CpuGetTimerValue, CpuSetMemoryAttributes, 0, // NumberOfTimers - 4, // DmaBufferAlignment + 2048, // DmaBufferAlignment }; EFI_STATUS @@ -239,6 +239,8 @@ CpuDxeInitialize ( InitializeExceptions (&mCpu); + mCpu.DmaBufferAlignment = ArmCacheWritebackGranule (); + Status = gBS->InstallMultipleProtocolInterfaces ( &mCpuHandle, &gEfiCpuArchProtocolGuid, &mCpu, -- 2.7.4