From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x233.google.com (mail-wm0-x233.google.com [IPv6:2a00:1450:400c:c09::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6EC3F81F11 for ; Sat, 12 Nov 2016 05:02:31 -0800 (PST) Received: by mail-wm0-x233.google.com with SMTP id g23so23459505wme.1 for ; Sat, 12 Nov 2016 05:02:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lzvrXl13imBzK1NWrJ07PxzLAOHuOaCAeL56XZ99qLM=; b=Sc6QoEvPzzpp2NUh74m0JnTUAJtCtL3N4vU3iUV3KmPCBInWrRODLFUgvTUn6994Ud z/urYs6WgSDaMWOQUzrwr3k+TwRm5A0BM84fZMKrxDfNtOW1qbl3OvQSzkpy8H7n3lRO /9pDJQkirLfFZydjFX0Pp1HJJhSrXRQB1pEwY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lzvrXl13imBzK1NWrJ07PxzLAOHuOaCAeL56XZ99qLM=; b=DWzpRAX8ChQkfZN59gYpScUi9VHi1OZpUp4KLQNuyUy9St1eLZTl8TB1COLwgtSa3h N+nTUnmRI/PGzK/eo4qS7b57zGOvuAcUCQ8XQ2MA3sKeVqsZS57qftG485IJ1Atfg9yz S2io9nACR5W6ckj1gXOb1sybiE9+gFG868EI3Oy2A4aOrRbND3wGTu15UNlGtAlSb2+q ahdlYJX5V+KzNJ4KOZuKp9IEIMvCUXi/0Qo4QWNTHvNuy2CyL5VBR8gT5AIOZEQPa7qN 0ELC1b99BD7UcREcmQMozrDCvZ/aPNc9bHHevQlpizuPNAKqZMmzCrK7yglEXtqqXR07 Q+1Q== X-Gm-Message-State: ABUngvdpjsDMVRwA6+0ZGGIMIF43AhpXGE+9qpYHD+IVMNztQZbmaToq1o5apbEzjSqqFHqY X-Received: by 10.194.172.3 with SMTP id ay3mr12582727wjc.84.1478955754187; Sat, 12 Nov 2016 05:02:34 -0800 (PST) Received: from ards-macbook-pro.access.network ([193.57.185.11]) by smtp.gmail.com with ESMTPSA id e188sm6084212wma.21.2016.11.12.05.02.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 12 Nov 2016 05:02:33 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Cc: Ard Biesheuvel Date: Sat, 12 Nov 2016 14:02:27 +0100 Message-Id: <1478955748-14819-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1478955748-14819-1-git-send-email-ard.biesheuvel@linaro.org> References: <1478955748-14819-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH v2 3/4] ArmPkg/ArmDmaLib: clean up abuse of device address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 12 Nov 2016 13:02:31 -0000 In preparation of adding support to ArmDmalib for DMA bus masters whose view of memory is offset by a constant compared to the CPU's view, clean up some abuse of the device address. The device address is not defined in terms of the CPU's address space, and so it should not be used in CopyMem () or cache maintenance operations that require a valid mapping. This not only applies to the above use case, but also to the DebugUncachedMemoryAllocationLib that unmaps the primary, cached mapping of an allocation, and returns a host address which is an uncached alias offset by a constant. Since we should never access the device address from the CPU, there is no need to record it in the MAPINFO struct. Instead, record the buffer address in case of double buffering, since we do need to copy the contents (in case of a bus master write) and free the buffer (in all cases) when DmaUnmap() is called. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmDmaLib/ArmDmaLib.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c index c2a44398d25a..7321388de63e 100644 --- a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c +++ b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c @@ -27,7 +27,7 @@ typedef struct { EFI_PHYSICAL_ADDRESS HostAddress; - EFI_PHYSICAL_ADDRESS DeviceAddress; + VOID *BufferAddress; UINTN NumberOfBytes; DMA_MAP_OPERATION Operation; BOOLEAN DoubleBuffer; @@ -94,7 +94,7 @@ DmaMap ( ((*NumberOfBytes & (mCpu->DmaBufferAlignment - 1)) != 0)) { // Get the cacheability of the region - Status = gDS->GetMemorySpaceDescriptor (*DeviceAddress, &GcdDescriptor); + Status = gDS->GetMemorySpaceDescriptor ((UINTN)HostAddress, &GcdDescriptor); if (EFI_ERROR(Status)) { return Status; } @@ -128,6 +128,7 @@ DmaMap ( } *DeviceAddress = ConvertToPhysicalAddress ((UINTN)Buffer); + Map->BufferAddress = Buffer; } else { Map->DoubleBuffer = FALSE; } @@ -143,7 +144,7 @@ DmaMap ( // So duplicate the check here when running in DEBUG mode, just to assert // that we are not trying to create a consistent mapping for cached memory. // - Status = gDS->GetMemorySpaceDescriptor (*DeviceAddress, &GcdDescriptor); + Status = gDS->GetMemorySpaceDescriptor ((UINTN)HostAddress, &GcdDescriptor); ASSERT_EFI_ERROR(Status); ASSERT (Operation != MapOperationBusMasterCommonBuffer || @@ -152,12 +153,11 @@ DmaMap ( DEBUG_CODE_END (); // Flush the Data Cache (should not have any effect if the memory region is uncached) - mCpu->FlushDataCache (mCpu, *DeviceAddress, *NumberOfBytes, + mCpu->FlushDataCache (mCpu, (UINTN)HostAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate); } Map->HostAddress = (UINTN)HostAddress; - Map->DeviceAddress = *DeviceAddress; Map->NumberOfBytes = *NumberOfBytes; Map->Operation = Operation; @@ -200,10 +200,11 @@ DmaUnmap ( if (Map->Operation == MapOperationBusMasterCommonBuffer) { Status = EFI_INVALID_PARAMETER; } else if (Map->Operation == MapOperationBusMasterWrite) { - CopyMem ((VOID *)(UINTN)Map->HostAddress, (VOID *)(UINTN)Map->DeviceAddress, Map->NumberOfBytes); + CopyMem ((VOID *)(UINTN)Map->HostAddress, Map->BufferAddress, + Map->NumberOfBytes); } - DmaFreeBuffer (EFI_SIZE_TO_PAGES (Map->NumberOfBytes), (VOID *)(UINTN)Map->DeviceAddress); + DmaFreeBuffer (EFI_SIZE_TO_PAGES (Map->NumberOfBytes), Map->BufferAddress); } else { if (Map->Operation == MapOperationBusMasterWrite) { -- 2.7.4