From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id A75D481E12 for ; Mon, 14 Nov 2016 13:10:16 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4EF0515AB; Mon, 14 Nov 2016 13:10:21 -0800 (PST) Received: from u200856.usa.arm.com (u201426.usa.arm.com [10.118.28.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DD03F3F218; Mon, 14 Nov 2016 13:10:20 -0800 (PST) From: Jeremy Linton To: edk2-devel@lists.01.org Cc: linaro-uefi@lists.linaro.org, ryan.harkin@linaro.org, leif.lindholm@linaro.org, steve.capper@arm.com, evan.lloyd@arm.com, daniil.egranov@arm.com, Jeremy Linton Date: Mon, 14 Nov 2016 15:09:44 -0600 Message-Id: <1479157789-14674-4-git-send-email-jeremy.linton@arm.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1479157789-14674-1-git-send-email-jeremy.linton@arm.com> References: <1479157789-14674-1-git-send-email-jeremy.linton@arm.com> Subject: [PATCH 3/7] EmbeddedPkg: SiI3132: Add SCSI protocol support to header X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Nov 2016 21:10:16 -0000 Add EXT_SCSI_PASS_THRU structures to SI3132_PORT structure, along with helpers and new entry points. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton --- EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h | 89 +++++++++++++++++++++++- 1 file changed, 87 insertions(+), 2 deletions(-) diff --git a/EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h b/EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h index f23446a..91f9448 100644 --- a/EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h +++ b/EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h @@ -20,6 +20,7 @@ #include #include +#include #include #include @@ -57,6 +58,7 @@ #define SII3132_PORT_SLOTSTATUS_REG 0x1800 #define SII3132_PORT_CMDACTIV_REG 0x1C00 #define SII3132_PORT_SSTATUS_REG 0x1F04 +#define SII3132_PORT_SERROR_REG 0x1F08 #define SII3132_PORT_CONTROL_RESET (1 << 0) #define SII3132_PORT_DEVICE_RESET (1 << 1) @@ -81,6 +83,7 @@ #define PRB_CTRL_INT_MASK 0x40 #define PRB_CTRL_SRST 0x80 +#define PRB_PROT_DEFAULT 0x00 #define PRB_PROT_PACKET 0x01 #define PRB_PROT_LEGACY_QUEUE 0x02 #define PRB_PROT_NATIVE_QUEUE 0x04 @@ -88,6 +91,9 @@ #define PRB_PROT_WRITE 0x10 #define PRB_PROT_TRANSPARENT 0x20 +#define SII_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device +#define SII_FIS_CONTROL_CMD (1 << 7) //Indicate FIS is a command + #define SGE_XCF (1 << 28) #define SGE_DRD (1 << 29) #define SGE_LNK (1 << 30) @@ -95,7 +101,7 @@ #define SI_MAX_CDB 12 //MAX supported CDB #define SI_MAX_SENSE 256 -#define SI_DEFAULT_TIMEOUT 20000 +#define SI_DEFAULT_TIMEOUT 50000 typedef struct _SATA_SI3132_SGE { @@ -126,6 +132,8 @@ typedef struct _SATA_SI3132_DEVICE { UINTN Index; struct _SATA_SI3132_PORT *Port; //Parent Port UINT32 BlockSize; + BOOLEAN Atapi; //ATAPI device + BOOLEAN Cdb16; //Uses 16byte CDB transfers (or 12) } SATA_SI3132_DEVICE; typedef struct _SATA_SI3132_PORT { @@ -146,13 +154,18 @@ typedef struct _SATA_SI3132_INSTANCE { SATA_SI3132_PORT Ports[SATA_SII3132_MAXPORT]; - EFI_ATA_PASS_THRU_PROTOCOL AtaPassThruProtocol; + EFI_ATA_PASS_THRU_MODE AtaPassThruMode; + EFI_ATA_PASS_THRU_PROTOCOL AtaPassThruProtocol; + EFI_EXT_SCSI_PASS_THRU_MODE ExtScsiPassThruMode; + EFI_EXT_SCSI_PASS_THRU_PROTOCOL ExtScsiPassThru; + EFI_PCI_IO_PROTOCOL *PciIo; } SATA_SI3132_INSTANCE; #define SATA_SII3132_SIGNATURE SIGNATURE_32('s', 'i', '3', '2') #define INSTANCE_FROM_ATAPASSTHRU_THIS(a) CR(a, SATA_SI3132_INSTANCE, AtaPassThruProtocol, SATA_SII3132_SIGNATURE) +#define INSTANCE_FROM_SCSIPASSTHRU_THIS(a) CR(a, SATA_SI3132_INSTANCE, ExtScsiPassThru, SATA_SII3132_SIGNATURE) #define SATA_GLOBAL_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, Value) #define SATA_GLOBAL_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, &Value32); } @@ -271,4 +284,76 @@ EFI_STATUS SiI3132ResetDevice ( IN UINT16 PortMultiplierPort ); +/** + * EFI ATA Pass Thru Entry points for SCSI Protocol + */ +SATA_SI3132_DEVICE* GetSataDevice ( + IN SATA_SI3132_INSTANCE *SataInstance, + IN UINT16 Port, + IN UINT16 PortMultiplierPort + ); + + +EFI_STATUS SiI3132IssueCommand( + IN SATA_SI3132_PORT *SataPort, + EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT32 Timeout, + VOID *StatusBlock + ); + + + +/** + * EFI SCSI Pass Thru Protocol + */ +EFI_STATUS SiI3132ScsiPassThru( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, + IN UINT8 *Target, + IN UINT64 Lun, + IN OUT EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet, + IN EFI_EVENT Event OPTIONAL + ); + +EFI_STATUS SiI3132GetNextTargetLun( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, + IN OUT UINT8 **Target, + IN OUT UINT64 *Lun +); + +EFI_STATUS SiI3132GetNextTargetLun2( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, + IN UINT8 *Target, + IN UINT64 Lun, + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ); + +EFI_STATUS SiI3132ScsiBuildDevicePath( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, + IN UINT8 *Target, + IN UINT64 Lun, + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ); + +EFI_STATUS SiI3132GetTargetLun ( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + OUT UINT8 **Target, + OUT UINT64 *Lun + ); + +EFI_STATUS SiI3132ResetChannel( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This + ); + +EFI_STATUS SiI3132ResetTargetLun( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, + IN UINT8 *Target, + IN UINT64 Lun + ); + +EFI_STATUS SiI3132GetNextTarget( + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, + IN OUT UINT8 **Target + ); + #endif -- 2.5.5