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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id 125sm7295678ljj.26.2016.11.23.06.56.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 Nov 2016 06:56:15 -0800 (PST) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: feng.tian@intel.com, michael.d.kinney@intel.com, liming.gao@intel.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com Date: Wed, 23 Nov 2016 15:58:44 +0100 Message-Id: <1479913124-7869-1-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 Subject: [PATCH] MdeModulePkg/AtaAtapiPassThru: Set GHC.AE bit unconditionally for Ahci X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Nov 2016 14:56:19 -0000 According to AHCI Spec 1.3 GHC.AE bit description: "The implementation of this bit is dependent upon the value of the CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be read-only and shall have a reset value of '1'." Being in AhciMode, for proper operation it is required, that GHC.AE bit is always set, before any other AHCI registers are written to. Current AhciMode implementation, both in AhciReset() and AhciModeInitialization() functions, set GHC.AE bit only depending on 'CAP.SAM == 0' condition, assuming (according to the AHCI spec), that otherwise it has to be set anyway. It may however happen, that even if 'CAP.SAM == 1', GHC.AE requires updating by software. This patch enables setting GHC.AE bit unconditionally in AhciMode, which fixes AHCI support for Marvell Armada 70x0 and 80x0 SoC families. The change is transparent to all other platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Signed-off-by: Jan Dabros --- MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c index 533d201..6266ff3 100644 --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c @@ -1451,19 +1451,11 @@ AhciReset ( { UINT64 Delay; UINT32 Value; - UINT32 Capability; // - // Collect AHCI controller information - // - Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); - + // Enable AE before accessing any AHCI registers. // - // Enable AE before accessing any AHCI registers if Supports AHCI Mode Only is not set - // - if ((Capability & EFI_AHCI_CAP_SAM) == 0) { - AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); - } + AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET); @@ -2272,11 +2264,9 @@ AhciModeInitialization ( Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); // - // Enable AE before accessing any AHCI registers if Supports AHCI Mode Only is not set + // Enable AE before accessing any AHCI registers. // - if ((Capability & EFI_AHCI_CAP_SAM) == 0) { - AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); - } + AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); // // Enable 64-bit DMA support in the PCI layer if this controller -- 1.8.3.1