From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf0-x231.google.com (mail-lf0-x231.google.com [IPv6:2a00:1450:4010:c07::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A3EC881EDA for ; Wed, 23 Nov 2016 23:52:08 -0800 (PST) Received: by mail-lf0-x231.google.com with SMTP id c13so22034825lfg.0 for ; Wed, 23 Nov 2016 23:52:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=ZC40oA7SkhkoUbffbKGzxCybU/ka+F8GX51ek8SBtSQ=; b=vQW8rnaaTVC7Yv5SUkSbwYyZQUyLKbBZPk2mTF7kB1SNHyDVF7z5EqqfSnwC7h3wnA q6S3BhgQpOJHWiajCmU9rxpk7DLXoESb5PGDhFcdYwnNKF+VKpuIEhU14u/LOfc33F3+ QYT3zpaftPACsJmKJxCGO8sv2XSRBO3WfqhFbz39mSRjHlgZzKzsFE0uvrUhsCpeDgnz /aiF3AUZ5DP58REvuA3vAb2WZQLj4TE7LrieQKDXpLC1GGKhcNtNjiibvvaNp5LTrxmN lj+uaw+btxTP4hQwrXJougJVd4CTTs2TPOYLl4Dqyt0qpg7syTz0IForMO2dRMDqkE9c RQew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ZC40oA7SkhkoUbffbKGzxCybU/ka+F8GX51ek8SBtSQ=; b=hMzeV6INGlLgnNZler4qWQJ51lxwrcDhrOqjNvK15/QIhTlS9YncV3JLzMBytJ840N SU4VjGO6MytxW1uVFVmukKXoGlFZ6J2xKnqkpf+7VejAboL5nxsqG4iTYjTT7T6jWA75 WlpaYzuvlT1T9qJzR0brYu9J3BT6E9HZjKlefMEcGlfV1U3SRqP2+MNus/kNO2BA5izM I/JPtcLaVrCujvYyIEuBXdNrOS947BK2eY3bkXbyeftjx40bm6PNNwn4pC7MPJ3FyDPJ YBCC4+HJv40uZuCufZMERLvzlheNa/4qLj02z/Qdv4plh786iETvoUBd1Gcx1/Cs041W DUhw== X-Gm-Message-State: AKaTC00UsQLUZP0De+lNzOmwzWb8Q2Sen8NPy4FmaNAzV6Sup2nR5N4wvP7afeihUakGHw== X-Received: by 10.46.0.102 with SMTP id 99mr493803lja.15.1479973926755; Wed, 23 Nov 2016 23:52:06 -0800 (PST) Received: from enkidu.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id u63sm7834666lja.34.2016.11.23.23.52.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 Nov 2016 23:52:06 -0800 (PST) From: Marcin Wojtas To: edk2-devel@lists.01.org Cc: feng.tian@intel.com, michael.d.kinney@intel.com, liming.gao@intel.com, leif.lindholm@linaro.org, ard.biesheuvel@linaro.org, mw@semihalf.com, jsd@semihalf.com Date: Thu, 24 Nov 2016 08:54:33 +0100 Message-Id: <1479974073-29154-1-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 Subject: [PATCH v2] MdeModulePkg/AtaAtapiPassThru: Ensure GHC.AE bit is always set in Ahci X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Nov 2016 07:52:09 -0000 According to AHCI Spec 1.3 GHC.AE bit description: "The implementation of this bit is dependent upon the value of the CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be read-only and shall have a reset value of '1'." Being in AhciMode, for proper operation it is required, that GHC.AE bit is always set, before any other AHCI registers are written to. Current AhciMode implementation, both in AhciReset() and AhciModeInitialization() functions, set GHC.AE bit only depending on 'CAP.SAM == 0' condition, assuming (according to the AHCI spec), that otherwise it has to be set anyway. It may however happen, that even if 'CAP.SAM == 1', GHC.AE requires updating by software. This patch enables in AhciMode setting GHC.AE in case its initial value is '0'. It fixes AHCI support for Marvell Armada 70x0 and 80x0 SoC families. The change is transparent to all other platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Signed-off-by: Jan Dabros --- Changelog: v1 -> v2 * Instead of doing it uncoditionally, enable setting GHC.AE bit only in case its initial value is '0' --- MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c index 533d201..4d01c1d 100644 --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c @@ -1451,17 +1451,13 @@ AhciReset ( { UINT64 Delay; UINT32 Value; - UINT32 Capability; // - // Collect AHCI controller information - // - Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); - - // - // Enable AE before accessing any AHCI registers if Supports AHCI Mode Only is not set + // Make sure that GHC.AE bit is set before accessing any AHCI registers. // - if ((Capability & EFI_AHCI_CAP_SAM) == 0) { + Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET); + + if ((Value & EFI_AHCI_GHC_ENABLE) == 0) { AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); } @@ -2252,6 +2248,7 @@ AhciModeInitialization ( EFI_ATA_COLLECTIVE_MODE *SupportedModes; EFI_ATA_TRANSFER_MODE TransferMode; UINT32 PhyDetectDelay; + UINT32 Value; if (Instance == NULL) { return EFI_INVALID_PARAMETER; @@ -2270,11 +2267,13 @@ AhciModeInitialization ( // Collect AHCI controller information // Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); - + // - // Enable AE before accessing any AHCI registers if Supports AHCI Mode Only is not set + // Make sure that GHC.AE bit is set before accessing any AHCI registers. // - if ((Capability & EFI_AHCI_CAP_SAM) == 0) { + Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET); + + if ((Value & EFI_AHCI_GHC_ENABLE) == 0) { AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); } -- 1.8.3.1