From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D2C9981EAC for ; Tue, 29 Nov 2016 23:07:00 -0800 (PST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP; 29 Nov 2016 23:07:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,720,1473145200"; d="scan'208";a="37101116" Received: from mdkinney-mobl.amr.corp.intel.com ([10.254.72.205]) by orsmga005.jf.intel.com with ESMTP; 29 Nov 2016 23:07:00 -0800 From: Michael Kinney To: edk2-devel@lists.01.org Cc: Jiewen Yao , Jeff Fan , Feng Tian Date: Tue, 29 Nov 2016 23:06:56 -0800 Message-Id: <1480489617-17028-2-git-send-email-michael.d.kinney@intel.com> X-Mailer: git-send-email 2.6.3.windows.1 In-Reply-To: <1480489617-17028-1-git-send-email-michael.d.kinney@intel.com> References: <1480489617-17028-1-git-send-email-michael.d.kinney@intel.com> Subject: [Patch 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Nov 2016 07:07:00 -0000 https://bugzilla.tianocore.org/show_bug.cgi?id=277 All CPUs use the same MTRR settings. Move MTRR settings from a field in the PROCESSOR_SMM_DESCRIPTOR structure into a module global variable. Cc: Jiewen Yao Cc: Jeff Fan Cc: Feng Tian Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 18 ++++-------------- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 2 +- 2 files changed, 5 insertions(+), 15 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index cfbf59e..6dc9607 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -17,7 +17,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. // // Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE) // -UINT64 gSmiMtrrs[MTRR_NUMBER_OF_FIXED_MTRR + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; +MTRR_SETTINGS gSmiMtrrs; UINT64 gPhyMask; SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData = NULL; UINTN mSmmMpSyncDataSize; @@ -283,20 +283,12 @@ ReplaceOSMtrrs ( IN UINTN CpuIndex ) { - PROCESSOR_SMM_DESCRIPTOR *Psd; - UINT64 *SmiMtrrs; - MTRR_SETTINGS *BiosMtrr; - - Psd = (PROCESSOR_SMM_DESCRIPTOR*)(mCpuHotPlugData.SmBase[CpuIndex] + SMM_PSD_OFFSET); - SmiMtrrs = (UINT64*)(UINTN)Psd->MtrrBaseMaskPtr; - SmmCpuFeaturesDisableSmrr (); // // Replace all MTRRs registers // - BiosMtrr = (MTRR_SETTINGS*)SmiMtrrs; - MtrrSetAllMtrrs(BiosMtrr); + MtrrSetAllMtrrs (&gSmiMtrrs); } /** @@ -1376,7 +1368,6 @@ InitializeMpServiceData ( { UINT32 Cr3; UINTN Index; - MTRR_SETTINGS *Mtrr; PROCESSOR_SMM_DESCRIPTOR *Psd; UINT8 *GdtTssTables; UINTN GdtTableStepSize; @@ -1439,9 +1430,8 @@ InitializeMpServiceData ( // // Record current MTRR settings // - ZeroMem(gSmiMtrrs, sizeof (gSmiMtrrs)); - Mtrr = (MTRR_SETTINGS*)gSmiMtrrs; - MtrrGetAllMtrrs (Mtrr); + ZeroMem (&gSmiMtrrs, sizeof (gSmiMtrrs)); + MtrrGetAllMtrrs (&gSmiMtrrs); return Cr3; } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index abe5cc6..bd6abf2 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -380,7 +380,7 @@ typedef struct { UINT16 Reserved11; // Offset 0x50 UINT16 Reserved12; // Offset 0x52 UINT32 Reserved13; // Offset 0x54 - UINT64 MtrrBaseMaskPtr; // Offset 0x58 + UINT64 Reserved14; // Offset 0x58 } PROCESSOR_SMM_DESCRIPTOR; -- 2.6.3.windows.1