From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id 2D0278214D for ; Mon, 12 Dec 2016 23:24:33 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EE4BAF; Mon, 12 Dec 2016 23:24:32 -0800 (PST) Received: from usa.arm.com (unknown [10.119.48.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6D6343F445; Mon, 12 Dec 2016 23:24:32 -0800 (PST) From: Daniil Egranov To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, ryan.harkin@linaro.org, Daniil Egranov Date: Tue, 13 Dec 2016 01:24:24 -0600 Message-Id: <1481613864-114733-1-git-send-email-daniil.egranov@arm.com> X-Mailer: git-send-email 2.7.4 Subject: [PATCH v2] ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe: Set Marvell Yukon MAC address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Dec 2016 07:24:33 -0000 Corrected style issues and code structure. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Daniil Egranov --- Changelog: v1 The patch reads a valid MAC address form the Juno IOFPGA registers and pushes it into onboard Marvell Yukon NIC. .../ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c | 147 +++++++++++++++++++++ .../Drivers/ArmJunoDxe/ArmJunoDxeInternal.h | 13 ++ 2 files changed, 160 insertions(+) diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c index b97f044..a36c6ff 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c @@ -15,7 +15,9 @@ #include "ArmJunoDxeInternal.h" #include +#include #include +#include #include #include @@ -69,6 +71,148 @@ STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mPciRootComplexDevicePath = { EFI_EVENT mAcpiRegistration = NULL; /** + The function reads MAC address from Juno IOFPGA registers and writes it + into Marvell Yukon NIC. +**/ +STATIC +EFI_STATUS +ArmJunoSetNetworkMAC () +{ + + EFI_STATUS Status; + UINTN HandleCount; + EFI_HANDLE *HandleBuffer; + UINTN HIndex; + EFI_PCI_IO_PROTOCOL* PciIo; + UINT64 PciID; + UINT32 MacHigh; + UINT32 MacLow; + UINT32 PciRegBase; + UINT64 OldPciAttributes; + UINT64 AttrSupports; + UINT8 *PciBarAttributes; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *AddrSpaceDescriptor; + + Status = gBS->LocateHandleBuffer (ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, &HandleCount, &HandleBuffer); + + if (EFI_ERROR (Status)) { + return (Status); + } + + for (HIndex = 0; HIndex < HandleCount; ++HIndex) { + Status = gBS->OpenProtocol ( + HandleBuffer[HIndex], + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo, + NULL, + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + + if (EFI_ERROR (Status)) { + continue; + } + + Status = PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint32, + PCI_VENDOR_ID_OFFSET, + 1, + &PciID + ); + + if (EFI_ERROR (Status)) { + continue; + } + + if ((PciID & 0xFFFFFFFF) != JUNO_MARVELL_YUKON_ID) { + continue; + } + + // Read MAC address from IOFPGA + MacHigh= MmioRead32 (ARM_JUNO_SYS_PCIGBE_H); + MacLow = MmioRead32 (ARM_JUNO_SYS_PCIGBE_L); + + Status = PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationGet, + 0, + &OldPciAttributes + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + Status = PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationSupported, + 0, + &AttrSupports + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + AttrSupports &= EFI_PCI_DEVICE_ENABLE; + Status = PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationEnable, + AttrSupports, + NULL + ); + + Status = PciIo->GetBarAttributes (PciIo, 0, &AttrSupports, (VOID**)&PciBarAttributes); + if (EFI_ERROR (Status)) { + return Status; + } + + AddrSpaceDescriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)PciBarAttributes; + + if (AddrSpaceDescriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR && + AddrSpaceDescriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM && + !(AddrSpaceDescriptor->SpecificFlag & ACPI_SPECFLAG_PREFETCHABLE)) { + + PciRegBase = AddrSpaceDescriptor->AddrRangeMin; + + // Set software reset control register to protect from deactivation + // the config write state + MmioWrite16 (PciRegBase + R_CONTROL_STATUS, CS_RESET_CLR); + + // Convert to Marvell MAC Address register format + MacHigh = SwapBytes32 ((MacHigh & 0xFFFF) << 16 | + (MacLow & 0xFFFF0000) >> 16); + MacLow = SwapBytes32 (MacLow) >> 16; + + // Set MAC Address + MmioWrite8 (PciRegBase + R_TST_CTRL_1, TST_CFG_WRITE_ENABLE); + MmioWrite32 (PciRegBase + R_MAC, MacHigh); + MmioWrite32 (PciRegBase + R_MAC_MAINT, MacHigh); + MmioWrite32 (PciRegBase + R_MAC + R_MAC_LOW, MacLow); + MmioWrite32 (PciRegBase + R_MAC_MAINT + R_MAC_LOW, MacLow); + MmioWrite8 (PciRegBase + R_TST_CTRL_1, TST_CFG_WRITE_DISABLE); + + // Initiate device reset + MmioWrite16 (PciRegBase + R_CONTROL_STATUS, CS_RESET_SET); + MmioWrite16 (PciRegBase + R_CONTROL_STATUS, CS_RESET_CLR); + + Status = EFI_SUCCESS; + } + + PciIo->Attributes ( + PciIo, + EfiPciIoAttributeOperationSet, + OldPciAttributes, + NULL + ); + } + + return Status; +} + +/** Notification function of the event defined as belonging to the EFI_END_OF_DXE_EVENT_GROUP_GUID event group that was created in the entry point of the driver. @@ -106,6 +250,9 @@ OnEndOfDxe ( Status = gBS->ConnectController (Handle, NULL, PciRootComplexDevicePath, FALSE); ASSERT_EFI_ERROR (Status); + + Status = ArmJunoSetNetworkMAC(); + ASSERT_EFI_ERROR (Status); } STATIC diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h index 662c413..df02770 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxeInternal.h @@ -29,6 +29,19 @@ #include +#define ACPI_SPECFLAG_PREFETCHABLE 0x06 +#define JUNO_MARVELL_YUKON_ID 0x438011AB /* Juno Marvell PCI Dev ID */ +#define TST_CFG_WRITE_ENABLE 0x02 /* Enable Config Write */ +#define TST_CFG_WRITE_DISABLE 0x00 /* Disable Config Write */ +#define CS_RESET_CLR 0x02 /* SW Reset Clear */ +#define CS_RESET_SET 0x00 /* SW Reset Set */ +#define R_CONTROL_STATUS 0x0004 /* Control/Status Register */ +#define R_MAC 0x0100 /* MAC Address */ +#define R_MAC_MAINT 0x0110 /* MAC Address Maintenance */ +#define R_MAC_LOW 0x04 /* MAC Address Low Register Offset */ +#define R_TST_CTRL_1 0x0158 /* Test Control Register 1 */ + + EFI_STATUS PciEmulationEntryPoint ( VOID -- 2.7.4