* [PATCH 0/4] Update CPUID & MSR header files with SDM (Sep.2016)
@ 2016-12-14 8:33 Hao Wu
2016-12-14 8:33 ` [PATCH 1/4] UefiCpuPkg/Include: Update " Hao Wu
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Hao Wu @ 2016-12-14 8:33 UTC (permalink / raw)
To: edk2-devel; +Cc: Hao Wu, Michael Kinney, Jeff Fan
https://bugzilla.tianocore.org/show_bug.cgi?id=176
According to the latest version (Sep.'16) of Intel(R) 64 and IA-32
Architectures Software Developer's Manual (SDM), this patch series will
update the MSR and CPUID related definitions in .h files under
UefiCpuPkg/Include/Register.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Hao Wu (4):
UefiCpuPkg/Include: Update MSR header files with SDM (Sep.2016)
UefiCpuPkg/Include: Update Skylake MSR header file with SDM (Sep.2016)
UefiCpuPkg/Include: Add Goldmont MSR header file with SDM (Sep.2016)
UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016)
UefiCpuPkg/Application/Cpuid/Cpuid.c | 115 +-
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 159 +-
UefiCpuPkg/Include/Register/Cpuid.h | 363 +++-
UefiCpuPkg/Include/Register/Msr.h | 3 +-
UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 167 +-
UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 43 +-
UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 286 +--
UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 64 +-
UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 2515 ++++++++++++++++++++++
UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 451 ++--
UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 62 +-
UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 416 ++--
UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 340 +--
UefiCpuPkg/Include/Register/Msr/P6Msr.h | 6 +-
UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 146 +-
UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 26 +-
UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 8 +-
UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 537 ++---
UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 411 ++--
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1189 +++++++++-
UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 2 +-
UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 456 +---
UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 74 +-
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 314 +--
24 files changed, 5323 insertions(+), 2830 deletions(-)
create mode 100644 UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
--
1.9.5.msysgit.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/4] UefiCpuPkg/Include: Update MSR header files with SDM (Sep.2016)
2016-12-14 8:33 [PATCH 0/4] Update CPUID & MSR header files with SDM (Sep.2016) Hao Wu
@ 2016-12-14 8:33 ` Hao Wu
2016-12-14 8:33 ` [PATCH 2/4] UefiCpuPkg/Include: Update Skylake MSR header file " Hao Wu
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Hao Wu @ 2016-12-14 8:33 UTC (permalink / raw)
To: edk2-devel; +Cc: Hao Wu, Michael Kinney, Jeff Fan
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=UTF-8, Size: 230126 bytes --]
https://bugzilla.tianocore.org/show_bug.cgi?id=176
Update MSR header files of processors (excluding Goldmont and Skylake
processors) according to Intel(R) 64 and IA-32 Architectures Software
Developer's Manual, Volume 3, September 2016, Chapter 35
Model-Specific-Registers (MSR).
Summary of incompatible changes:
General:
1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS in processor-specific header
files has been removed or renamed to IA32_PERF_GLOBAL_STATUS
Typo 'STAUS' has been fixed in SDM.
If the MSR definition is the same with architectural MSR, we remove it.
Otherwise, we rename the MSR.
2. MSRs (address starting from 400H) MSR_MC{X}_{XXX} (like MSR_MC4_STATUS)
in processor-specific header files have been removed or renamed to
IA32_MC{X}_{XXX} (like IA32_MC4_STATUS)
Register name change from 'MSR_MC{X}_{XXX}' to 'IA32_MC{X}_{XXX}' in SDM.
If the MSR definition is the same with architectural MSR, we remove it.
Otherwise, we rename the MSR.
Please note that for those MSRs still have name like 'MSR_MC{X}_{XXX}' in
SDM are still kept in processor-specific header files.
HaswellMsr.h:
1. MSR (address C80H) IA32_DEBUG_FEATURE has been removed
Register name change from 'IA32_DEBUG_FEATURE' to 'IA32_DEBUG_INTERFACE'
in SDM.
Since the MSR definition is the same with architectural MSR, we remove it.
SandyBridgeMsr.h:
1. MSR (address 391H) MSR_UNC_PERF_GLOBAL_CTRL, name change for bit fields
0:3
Bit description change from 'Core {X} select' to 'Slice {X} select' for
bit 0:3 in SDM.
SilvermontMsr.h:
1. MSR (address 2AH) MSR_EBL_CR_POWERON, structure definition changed
Bit description for this MSR is totally changed in SDM, we modify the
structure definition to align with it.
XeonDMsr.h:
1. MSRs (address 630H to 632H) MSR_PKG_C8_RESIDENCY, MSR_PKG_C9_RESIDENCY
and MSR_PKG_C10_RESIDENCY have been removed
Those 3 MSRs are not defined for this processor in SDM, we remove them.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
---
UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 159 ++++---
UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 167 +------
UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 43 +-
UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 286 +-----------
UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 64 +--
UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 451 +++++++++----------
UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 62 +--
UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 416 +++++-------------
UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 340 ++------------
UefiCpuPkg/Include/Register/Msr/P6Msr.h | 6 +-
UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 146 +++---
UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 26 +-
UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 8 +-
UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 537 ++++++++---------------
UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 411 +++++++++--------
UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 2 +-
UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 456 +++----------------
UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 74 +++-
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 314 +++++--------
19 files changed, 1312 insertions(+), 2656 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index a7a221d..af3f39d 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -17,15 +17,15 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Appendix A VMX Capability Reporting Facility, Section A.1.
+ September 2016, Appendix A VMX Capability Reporting Facility, Section A.1.
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Appendix A VMX Capability Reporting Facility, Section A.6.
+ September 2016, Appendix A VMX Capability Reporting Facility, Section A.6.
**/
@@ -33,7 +33,7 @@
#define __ARCHITECTURAL_MSR_H__
/**
- See Section 35.20, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
+ See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
@param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@@ -52,7 +52,7 @@
/**
- See Section 35.20, "MSRs in Pentium Processors.". DF_DM = 05_01H.
+ See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
@param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@@ -91,7 +91,7 @@
/**
- See Section 17.14, "Time-Stamp Counter.". Introduced at Display Family /
+ See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family /
Display Model 05_01H.
@param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
@@ -295,11 +295,16 @@ typedef union {
/// 6] is set. If CPUID.01H:ECX[6] = 1.
///
UINT32 SenterGlobalEnable:1;
- UINT32 Reserved2:2;
+ UINT32 Reserved2:1;
+ ///
+ /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to
+ /// enable runtime reconfiguration of SGX Launch Control via
+ /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
+ ///
+ UINT32 SgxLaunchControlEnable:1;
///
/// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
- /// leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is
- /// set. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
+ /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
///
UINT32 SgxEnable:1;
UINT32 Reserved3:1;
@@ -419,6 +424,37 @@ typedef union {
/**
+ IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the
+ SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the
+ default value is the digest of Intel's signing key. Read permitted If
+ CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):
+ EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.
+
+ @param ECX MSR_IA32_SGXLEPUBKEYHASHn
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);
+ AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);
+ @endcode
+ @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.
+ MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.
+ MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.
+ MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.
+ @{
+**/
+#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
+#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
+#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
+#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
+/// @}
+
+
+/**
SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =
1.
@@ -1113,7 +1149,7 @@ typedef union {
/**
Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled
- Clock Modulation.". Introduced at Display Family / Display Model 0F_0H.
+ Clock Modulation.". If CPUID.01H:EDX[22] = 1.
@param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)
@param EAX Lower 32-bits of MSR value.
@@ -1147,11 +1183,12 @@ typedef union {
UINT32 ExtendedOnDemandClockModulationDutyCycle:1;
///
/// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded
- /// values for target duty cycle modulation.
+ /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.
///
UINT32 OnDemandClockModulationDutyCycle:3;
///
/// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.
+ /// If CPUID.01H:EDX[22] = 1.
///
UINT32 OnDemandClockModulationEnable:1;
UINT32 Reserved1:27;
@@ -1172,7 +1209,7 @@ typedef union {
Thermal Interrupt Control (R/W) Enables and disables the generation of an
interrupt on temperature transitions detected with the processor's thermal
sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".
- Introduced at Display Family / Display Model 0F_0H.
+ If CPUID.01H:EDX[22] = 1
@param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)
@param EAX Lower 32-bits of MSR value.
@@ -1200,40 +1237,41 @@ typedef union {
///
struct {
///
- /// [Bit 0] High-Temperature Interrupt Enable.
+ /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
UINT32 HighTempEnable:1;
///
- /// [Bit 1] Low-Temperature Interrupt Enable.
+ /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
UINT32 LowTempEnable:1;
///
- /// [Bit 2] PROCHOT# Interrupt Enable.
+ /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
UINT32 PROCHOT_Enable:1;
///
- /// [Bit 3] FORCEPR# Interrupt Enable.
+ /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
UINT32 FORCEPR_Enable:1;
///
/// [Bit 4] Critical Temperature Interrupt Enable.
+ /// If CPUID.01H:EDX[22] = 1.
///
UINT32 CriticalTempEnable:1;
UINT32 Reserved1:3;
///
- /// [Bits 14:8] Threshold #1 Value.
+ /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.
///
UINT32 Threshold1:7;
///
- /// [Bit 15] Threshold #1 Interrupt Enable.
+ /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
UINT32 Threshold1Enable:1;
///
- /// [Bits 22:16] Threshold #2 Value.
+ /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.
///
UINT32 Threshold2:7;
///
- /// [Bit 23] Threshold #2 Interrupt Enable.
+ /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
///
UINT32 Threshold2Enable:1;
///
@@ -1257,8 +1295,7 @@ typedef union {
/**
Thermal Status Information (RO) Contains status information about the
processor's thermal sensor and automatic thermal monitoring facilities. See
- Section 14.7.2, "Thermal Monitor". Introduced at Display Family / Display
- Model 0F_0H.
+ Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.
@param ECX MSR_IA32_THERM_STATUS (0x0000019C)
@param EAX Lower 32-bits of MSR value.
@@ -1285,27 +1322,28 @@ typedef union {
///
struct {
///
- /// [Bit 0] Thermal Status (RO):.
+ /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.
///
UINT32 ThermalStatus:1;
///
- /// [Bit 1] Thermal Status Log (R/W):.
+ /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.
///
UINT32 ThermalStatusLog:1;
///
- /// [Bit 2] PROCHOT # or FORCEPR# event (RO).
+ /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.
///
UINT32 PROCHOT_FORCEPR_Event:1;
///
- /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0).
+ /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.
///
UINT32 PROCHOT_FORCEPR_Log:1;
///
- /// [Bit 4] Critical Temperature Status (RO).
+ /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.
///
UINT32 CriticalTempStatus:1;
///
/// [Bit 5] Critical Temperature Status log (R/WC0).
+ /// If CPUID.01H:EDX[22] = 1.
///
UINT32 CriticalTempStatusLog:1;
///
@@ -1418,8 +1456,9 @@ typedef union {
/// automatically reduce power consumption in response to TCC activation.
/// 0 = Disabled. Note: In some products clearing this bit might be
/// ignored in critical thermal conditions, and TM1, TM2 and adaptive
- /// thermal throttling will still be activated. Introduced at Display
- /// Family / Display Model 0F_0H.
+ /// thermal throttling will still be activated. The default value of this
+ /// field varies with product. See respective tables where default value is
+ /// listed. Introduced at Display Family / Display Model 0F_0H.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
@@ -1437,7 +1476,7 @@ typedef union {
///
UINT32 BTS:1;
///
- /// [Bit 12] Precise Event Based Sampling (PEBS) Unavailable (RO) 1 =
+ /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =
/// PEBS is not supported; 0 = PEBS is supported. Introduced at Display
/// Family / Display Model 06_0FH.
///
@@ -1466,15 +1505,15 @@ typedef union {
UINT32 Reserved6:3;
///
/// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H
- /// returns a maximum value in EAX[7:0] of 3. BIOS should contain a setup
+ /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup
/// question that allows users to specify when the installed OS does not
- /// support CPUID functions greater than 3. Before setting this bit, BIOS
+ /// support CPUID functions greater than 2. Before setting this bit, BIOS
/// must execute the CPUID.0H and examine the maximum value returned in
- /// EAX[7:0]. If the maximum value is greater than 3, the bit is
- /// supported. Otherwise, the bit is not supported. Writing to this bit
- /// when the maximum value is greater than 3 may generate a #GP exception.
+ /// EAX[7:0]. If the maximum value is greater than 2, this bit is
+ /// supported. Otherwise, this bit is not supported. Setting this bit when
+ /// the maximum value is not greater than 2 may generate a #GP exception.
/// Setting this bit may cause unexpected behavior in software that
- /// depends on the availability of CPUID leaves greater than 3. Introduced
+ /// depends on the availability of CPUID leaves greater than 2. Introduced
/// at Display Family / Display Model 0F_03H.
///
UINT32 LimitCpuidMaxval:1;
@@ -2687,8 +2726,8 @@ typedef union {
/**
- Fixed-Function Performance Counter 1 0 (R/W): Counts CPU_CLK_Unhalted.Core.
- If CPUID.0AH: EDX[4:0] > 1.
+ Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If
+ CPUID.0AH: EDX[4:0] > 1.
@param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)
@param EAX Lower 32-bits of MSR value.
@@ -2707,8 +2746,8 @@ typedef union {
/**
- Fixed-Function Performance Counter 0 0 (R/W): Counts CPU_CLK_Unhalted.Ref.
- If CPUID.0AH: EDX[4:0] > 2.
+ Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If
+ CPUID.0AH: EDX[4:0] > 2.
@param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)
@param EAX Lower 32-bits of MSR value.
@@ -3789,10 +3828,10 @@ typedef union {
///
UINT32 MemoryType:4;
///
- /// [Bit 54] If bit 54 is read as 1, the logical processor reports
- /// information in the VM-exit instruction-information field on VM exits
- /// due to execution of the INS and OUTS instructions. This reporting is
- /// done only if this bit is read as 1.
+ /// [Bit 54] If bit 54 is read as 1, the processor reports information in
+ /// the VM-exit instruction-information field on VM exitsdue to execution
+ /// of the INS and OUTS instructions (see Section 27.2.4). This reporting
+ /// is done only if this bit is read as 1.
///
UINT32 InsOutsReporting:1;
///
@@ -3951,11 +3990,21 @@ typedef union {
/// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).
///
UINT32 WaitForSipiActivityStateSupported:1;
- UINT32 Reserved1:6;
+ UINT32 Reserved1:5;
+ ///
+ /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used
+ /// in VMX operation. If the processor supports Intel PT but does not allow
+ /// it to be used in VMX operation, execution of VMXON clears
+ /// IA32_RTIT_CTL.TraceEn (see “VMXON—Enter VMX Operation” in Chapter 30);
+ /// any attempt to set that bit while in VMX operation (including VMX root
+ /// operation) using the WRMSR instruction causes a general-protection
+ /// exception.
+ ///
+ UINT32 ProcessorTraceSupported:1;
///
/// [Bit 15] If read as 1, the RDMSR instruction can be used in system-
/// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).
- /// See Section 34.15.6.4.
+ /// See Section 34.15.6.3.
///
UINT32 SmBaseMsrSupported:1;
///
@@ -3986,7 +4035,13 @@ typedef union {
/// information fields.
///
UINT32 VmWriteSupported:1;
- UINT32 Reserved2:2;
+ ///
+ /// [Bit 30] If read as 1, VM entry allows injection of a software
+ /// interrupt, software exception, or privileged software exception with an
+ /// instruction length of 0.
+ ///
+ UINT32 VmInjectSupported:1;
+ UINT32 Reserved2:1;
///
/// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the
/// processor.
@@ -4343,13 +4398,13 @@ typedef union {
///
struct {
///
- /// [Bit 0] Lock. See Section 42.12.3, "Interactions with Authenticated
+ /// [Bit 0] Lock. See Section 42.11.3, "Interactions with Authenticated
/// Code Modules (ACMs)".
///
UINT32 Lock:1;
UINT32 Reserved1:15;
///
- /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.12.3, "Interactions with
+ /// [Bits 23:16] SGX_SVN_SINIT. See Section 42.11.3, "Interactions with
/// Authenticated Code Modules (ACMs)".
///
UINT32 SGX_SVN_SINIT:8;
@@ -4776,7 +4831,7 @@ typedef union {
/**
DS Save Area (R/W) Points to the linear address of the first byte of the DS
buffer management area, which is used to manage the BTS and PEBS buffers.
- See Section 18.12.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]
+ See Section 18.15.4, "Debug Store (DS) Mechanism.". If( CPUID.01H:EDX.DS[21]
= 1.
[Bits 31..0] The linear address of the first byte of the DS buffer
@@ -5876,8 +5931,8 @@ typedef union {
/**
- Resource Association Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] =
- 1 ).
+ Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]
+ =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).
@param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
index 25e0927..c314195 100644
--- a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-3.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.3.
**/
@@ -177,12 +177,10 @@ typedef union {
/**
- Unique. Last Branch Record 0 From IP (R/W) One of eight pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the source instruction for one of the last eight
- branches, exceptions, or interrupts taken by the processor. See also: -
- Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,
- Interrupt, and Exception Recording (Pentium M Processors).".
+ Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch
+ record registers on the last branch record stack. The From_IP part of the
+ stack contains pointers to the source instruction . See also: - Last Branch
+ Record Stack TOS at 1C9H - Section 17.5.
@param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP
@param EAX Lower 32-bits of MSR value.
@@ -217,10 +215,9 @@ typedef union {
/**
- Unique. Last Branch Record 0 To IP (R/W) One of eight pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the destination instruction for one of the last eight
- branches, exceptions, or interrupts taken by the processor.
+ Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch
+ record registers on the last branch record stack. The To_IP part of the
+ stack contains pointers to the destination instruction.
@param ECX MSR_ATOM_LASTBRANCH_n_TO_IP
@param EAX Lower 32-bits of MSR value.
@@ -507,7 +504,7 @@ typedef union {
UINT32 Reserved1:2;
///
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2.
+ /// Table 35-2. Default value is 0.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
@@ -529,7 +526,7 @@ typedef union {
///
UINT32 BTS:1;
///
- /// [Bit 12] Shared. Precise Event Based Sampling Unavailable (RO) See
+ /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
/// Table 35-2.
///
UINT32 PEBS:1;
@@ -656,27 +653,7 @@ typedef union {
/**
- Unique. See Table 35-2. See Section 18.4.2, "Global Counter Control
- Facilities.".
-
- @param ECX MSR_ATOM_IA32_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_ATOM_IA32_PERF_GLOBAL_STAUS, Msr);
- @endcode
- @note MSR_ATOM_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
-**/
-#define MSR_ATOM_IA32_PERF_GLOBAL_STAUS 0x0000038E
-
-
-/**
- Unique. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling
+ Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)
@@ -723,128 +700,6 @@ typedef union {
/**
- Shared. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_ATOM_MC3_CTL (0x0000040C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_CTL);
- AsmWriteMsr64 (MSR_ATOM_MC3_CTL, Msr);
- @endcode
- @note MSR_ATOM_MC3_CTL is defined as MSR_MC3_CTL in SDM.
-**/
-#define MSR_ATOM_MC3_CTL 0x0000040C
-
-
-/**
- Shared. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_ATOM_MC3_STATUS (0x0000040D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_STATUS);
- AsmWriteMsr64 (MSR_ATOM_MC3_STATUS, Msr);
- @endcode
- @note MSR_ATOM_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
-**/
-#define MSR_ATOM_MC3_STATUS 0x0000040D
-
-
-/**
- Shared. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
- register is either not implemented or contains no address if the ADDRV flag
- in the MSR_MC3_STATUS register is clear. When not implemented in the
- processor, all reads and writes to this MSR will cause a general-protection
- exception.
-
- @param ECX MSR_ATOM_MC3_ADDR (0x0000040E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_ADDR);
- AsmWriteMsr64 (MSR_ATOM_MC3_ADDR, Msr);
- @endcode
- @note MSR_ATOM_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
-**/
-#define MSR_ATOM_MC3_ADDR 0x0000040E
-
-
-/**
- Shared. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_ATOM_MC4_CTL (0x00000410)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_CTL);
- AsmWriteMsr64 (MSR_ATOM_MC4_CTL, Msr);
- @endcode
- @note MSR_ATOM_MC4_CTL is defined as MSR_MC4_CTL in SDM.
-**/
-#define MSR_ATOM_MC4_CTL 0x00000410
-
-
-/**
- Shared. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_ATOM_MC4_STATUS (0x00000411)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_STATUS);
- AsmWriteMsr64 (MSR_ATOM_MC4_STATUS, Msr);
- @endcode
- @note MSR_ATOM_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
-**/
-#define MSR_ATOM_MC4_STATUS 0x00000411
-
-
-/**
- Shared. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
- register is either not implemented or contains no address if the ADDRV flag
- in the MSR_MC4_STATUS register is clear. When not implemented in the
- processor, all reads and writes to this MSR will cause a general-protection
- exception.
-
- @param ECX MSR_ATOM_MC4_ADDR (0x00000412)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_ADDR);
- AsmWriteMsr64 (MSR_ATOM_MC4_ADDR, Msr);
- @endcode
- @note MSR_ATOM_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
-**/
-#define MSR_ATOM_MC4_ADDR 0x00000412
-
-
-/**
Package. Package C2 Residency Note: C-state values are processor specific
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
C-States. Package. Package C2 Residency Counter. (R/O) Time that this
diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
index 0673685..1c3c2dc 100644
--- a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.13.
**/
@@ -30,25 +30,25 @@
Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
Facilities.".
- @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS (0x0000038E)
+ @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)
@param EAX Lower 32-bits of MSR value.
- Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.
+ Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
@param EDX Upper 32-bits of MSR value.
- Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.
+ Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
<b>Example usage</b>
@code
- MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;
+ MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
- Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
+ Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);
+ AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
@endcode
- @note MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
+ @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
**/
-#define MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS 0x0000038E
+#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E
/**
- MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS
+ MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS
**/
typedef union {
///
@@ -86,7 +86,7 @@ typedef union {
UINT32 Ovf_FixedCtr2:1;
UINT32 Reserved2:20;
///
- /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.4.2, "Table of Physical
+ /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical
/// Addresses (ToPA).".
///
UINT32 Trace_ToPA_PMI:1;
@@ -108,7 +108,7 @@ typedef union {
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
-} MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER;
+} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;
/**
@@ -265,4 +265,23 @@ typedef union {
UINT64 Uint64;
} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
+
+/**
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
+ Domains.".
+
+ @param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);
+ @endcode
+ @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639
+
#endif
diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
index 44da688..9f0e790 100644
--- a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.2.
**/
@@ -239,11 +239,9 @@ typedef union {
/**
Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the source instruction for one of the last four
- branches, exceptions, or interrupts taken by the processor. See also: -
- Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,
- Interrupt, and Exception Recording (Pentium M Processors).".
+ record registers on the last branch record stack. The From_IP part of the
+ stack contains pointers to the source instruction. See also: - Last Branch
+ Record Stack TOS at 1C9H - Section 17.5.
@param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP
@param EAX Lower 32-bits of MSR value.
@@ -271,9 +269,8 @@ typedef union {
/**
Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the destination instruction for one of the last four
- branches, exceptions, or interrupts taken by the processor.
+ record registers on the last branch record stack. This To_IP part of the
+ stack contains pointers to the destination instruction.
@param ECX MSR_CORE2_LASTBRANCH_n_TO_IP
@param EAX Lower 32-bits of MSR value.
@@ -692,7 +689,7 @@ typedef union {
///
UINT32 BTS:1;
///
- /// [Bit 12] Shared. Precise Event Based Sampling Unavailable (RO) See
+ /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
/// Table 35-2.
///
UINT32 PEBS:1;
@@ -959,29 +956,9 @@ typedef union {
/**
- Unique. See Table 35-2. See Section 18.4.2, "Global Counter Control
- Facilities.".
-
- @param ECX MSR_CORE2_IA32_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS, Msr);
- @endcode
- @note MSR_CORE2_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
-**/
-#define MSR_CORE2_IA32_PERF_GLOBAL_STAUS 0x0000038E
-
-
-/**
Unique. See Section 18.4.2, "Global Counter Control Facilities.".
- @param ECX MSR_CORE2_PERF_GLOBAL_STAUS (0x0000038E)
+ @param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -989,12 +966,12 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS, Msr);
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS);
+ AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr);
@endcode
- @note MSR_CORE2_PERF_GLOBAL_STAUS is defined as MSR_PERF_GLOBAL_STAUS in SDM.
+ @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.
**/
-#define MSR_CORE2_PERF_GLOBAL_STAUS 0x0000038E
+#define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E
/**
@@ -1036,7 +1013,7 @@ typedef union {
/**
- Unique. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling
+ Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)
@@ -1083,243 +1060,6 @@ typedef union {
/**
- Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_CORE2_MC4_CTL (0x0000040C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_CTL);
- AsmWriteMsr64 (MSR_CORE2_MC4_CTL, Msr);
- @endcode
- @note MSR_CORE2_MC4_CTL is defined as MSR_MC4_CTL in SDM.
-**/
-#define MSR_CORE2_MC4_CTL 0x0000040C
-
-
-/**
- Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_CORE2_MC4_STATUS (0x0000040D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_STATUS);
- AsmWriteMsr64 (MSR_CORE2_MC4_STATUS, Msr);
- @endcode
- @note MSR_CORE2_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
-**/
-#define MSR_CORE2_MC4_STATUS 0x0000040D
-
-
-/**
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
- register is either not implemented or contains no address if the ADDRV flag
- in the MSR_MC4_STATUS register is clear. When not implemented in the
- processor, all reads and writes to this MSR will cause a general-protection
- exception.
-
- @param ECX MSR_CORE2_MC4_ADDR (0x0000040E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_ADDR);
- AsmWriteMsr64 (MSR_CORE2_MC4_ADDR, Msr);
- @endcode
- @note MSR_CORE2_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
-**/
-#define MSR_CORE2_MC4_ADDR 0x0000040E
-
-
-/**
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_CORE2_MC3_CTL (0x00000410)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_CTL);
- AsmWriteMsr64 (MSR_CORE2_MC3_CTL, Msr);
- @endcode
- @note MSR_CORE2_MC3_CTL is defined as MSR_MC3_CTL in SDM.
-**/
-#define MSR_CORE2_MC3_CTL 0x00000410
-
-
-/**
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_CORE2_MC3_STATUS (0x00000411)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_STATUS);
- AsmWriteMsr64 (MSR_CORE2_MC3_STATUS, Msr);
- @endcode
- @note MSR_CORE2_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
-**/
-#define MSR_CORE2_MC3_STATUS 0x00000411
-
-
-/**
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
- register is either not implemented or contains no address if the ADDRV flag
- in the MSR_MC3_STATUS register is clear. When not implemented in the
- processor, all reads and writes to this MSR will cause a general-protection
- exception.
-
- @param ECX MSR_CORE2_MC3_ADDR (0x00000412)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_ADDR);
- AsmWriteMsr64 (MSR_CORE2_MC3_ADDR, Msr);
- @endcode
- @note MSR_CORE2_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
-**/
-#define MSR_CORE2_MC3_ADDR 0x00000412
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE2_MC3_MISC (0x00000413)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_MISC);
- AsmWriteMsr64 (MSR_CORE2_MC3_MISC, Msr);
- @endcode
- @note MSR_CORE2_MC3_MISC is defined as MSR_MC3_MISC in SDM.
-**/
-#define MSR_CORE2_MC3_MISC 0x00000413
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE2_MC5_CTL (0x00000414)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_CTL);
- AsmWriteMsr64 (MSR_CORE2_MC5_CTL, Msr);
- @endcode
- @note MSR_CORE2_MC5_CTL is defined as MSR_MC5_CTL in SDM.
-**/
-#define MSR_CORE2_MC5_CTL 0x00000414
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE2_MC5_STATUS (0x00000415)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_STATUS);
- AsmWriteMsr64 (MSR_CORE2_MC5_STATUS, Msr);
- @endcode
- @note MSR_CORE2_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
-**/
-#define MSR_CORE2_MC5_STATUS 0x00000415
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE2_MC5_ADDR (0x00000416)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_ADDR);
- AsmWriteMsr64 (MSR_CORE2_MC5_ADDR, Msr);
- @endcode
- @note MSR_CORE2_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
-**/
-#define MSR_CORE2_MC5_ADDR 0x00000416
-
-
-/**
- Unique.
-
- @param ECX MSR_CORE2_MC5_MISC (0x00000417)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_MISC);
- AsmWriteMsr64 (MSR_CORE2_MC5_MISC, Msr);
- @endcode
- @note MSR_CORE2_MC5_MISC is defined as MSR_MC5_MISC in SDM.
-**/
-#define MSR_CORE2_MC5_MISC 0x00000417
-
-
-/**
- Unique. Apply to Intel Xeon processor 7400 series (processor signature
- 06_1D) only. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS." and Chapter 23.
-
- @param ECX MSR_CORE2_MC6_STATUS (0x00000419)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE2_MC6_STATUS);
- AsmWriteMsr64 (MSR_CORE2_MC6_STATUS, Msr);
- @endcode
- @note MSR_CORE2_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.
-**/
-#define MSR_CORE2_MC6_STATUS 0x00000419
-
-
-/**
Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon
processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.
diff --git a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
index ac45e6f..0902aa9 100644
--- a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-17.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.19.
**/
@@ -27,7 +27,7 @@
#include <Register/ArchitecturalMsr.h>
/**
- Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.
+ Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.
@param ECX MSR_CORE_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@@ -46,7 +46,7 @@
/**
- Unique. See Section 35.20, "MSRs in Pentium Processors," and see Table 35-2.
+ Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.
@param ECX MSR_CORE_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@@ -178,7 +178,7 @@ typedef union {
Unique. Last Branch Record n (R/W) One of 8 last branch record registers on
the last branch record stack: bits 31-0 hold the 'from' address and bits
63-32 hold the 'to' address. See also: - Last Branch Record Stack TOS at
- 1C9H - Section 17.12, "Last Branch, Interrupt, and Exception Recording
+ 1C9H - Section 17.13, "Last Branch, Interrupt, and Exception Recording
(Pentium M Processors).".
@param ECX MSR_CORE_LASTBRANCH_n
@@ -434,14 +434,14 @@ typedef union {
/// thermal sensor indicates that the die temperature is at the
/// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
/// TM2 will reduce the bus to core ratio and voltage according to the
- /// value last written to MSR_THERM2_CTL bits 15:0.
- /// When this bit is clear (0, default), the processor does not change
- /// the VID signals or the bus to core ratio when the processor enters a
- /// thermal managed state. If the TM2 feature flag (ECX[8]) is not set
- /// to 1 after executing CPUID with EAX = 1, then this feature is not
- /// supported and BIOS must not alter the contents of this bit location.
- /// The processor is operating out of spec if both this bit and the TM1
- /// bit are set to disabled states.
+ /// value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear
+ /// (0, default), the processor does not change the VID signals or the bus
+ /// to core ratio when the processor enters a thermal managed state. If
+ /// the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID
+ /// with EAX = 1, then this feature is not supported and BIOS must not
+ /// alter the contents of this bit location. The processor is operating
+ /// out of spec if both this bit and the TM1 bit are set to disabled
+ /// states.
///
UINT32 TM2:1;
UINT32 Reserved5:2;
@@ -460,7 +460,7 @@ typedef union {
///
/// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2. Setting this
/// bit may cause behavior in software that depends on the availability of
- /// CPUID leaves greater than 3.
+ /// CPUID leaves greater than 2.
///
UINT32 LimitCpuidMaxval:1;
UINT32 Reserved9:9;
@@ -928,44 +928,6 @@ typedef union {
/**
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_CORE_MC3_CTL (0x00000410)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MC3_CTL);
- AsmWriteMsr64 (MSR_CORE_MC3_CTL, Msr);
- @endcode
- @note MSR_CORE_MC3_CTL is defined as MSR_MC3_CTL in SDM.
-**/
-#define MSR_CORE_MC3_CTL 0x00000410
-
-
-/**
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_CORE_MC3_STATUS (0x00000411)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_CORE_MC3_STATUS);
- AsmWriteMsr64 (MSR_CORE_MC3_STATUS, Msr);
- @endcode
- @note MSR_CORE_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
-**/
-#define MSR_CORE_MC3_STATUS 0x00000411
-
-
-/**
Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
register is either not implemented or contains no address if the ADDRV flag
in the MSR_MC3_STATUS register is clear. When not implemented in the
diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
index f201e9c..7b190b5 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-11.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.12.
**/
@@ -27,6 +27,113 @@
#include <Register/ArchitecturalMsr.h>
/**
+ Package. Configured State of Enabled Processor Core Count and Logical
+ Processor Count (RO) - After a Power-On RESET, enumerates factory
+ configuration of the number of processor cores and logical processors in the
+ physical package. - Following the sequence of (i) BIOS modified a
+ Configuration Mask which selects a subset of processor cores to be active
+ post RESET and (ii) a RESET event after the modification, enumerates the
+ current configuration of enabled processor core count and logical processor
+ count in the physical package.
+
+ @param ECX MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);
+ @endcode
+ @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.
+**/
+#define MSR_HASWELL_E_CORE_THREAD_COUNT 0x00000035
+
+/**
+ MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are
+ /// currently enabled (by either factory configuration or BIOS
+ /// configuration) in the physical package.
+ ///
+ UINT32 Core_Count:16;
+ ///
+ /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that
+ /// are currently enabled (by either factory configuration or BIOS
+ /// configuration) in the physical package.
+ ///
+ UINT32 Thread_Count:16;
+ UINT32 Reserved:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;
+
+
+/**
+ Thread. A Hardware Assigned ID for the Logical Processor (RO).
+
+ @param ECX MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);
+ @endcode
+ @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.
+**/
+#define MSR_HASWELL_E_THREAD_ID_INFO 0x00000053
+
+/**
+ MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific
+ /// numerical. value physically assigned to each logical processor. This
+ /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within
+ /// a physical package.
+ ///
+ UINT32 Logical_Processor_ID:8;
+ UINT32 Reserved1:24;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;
+
+
+/**
Core. C-State Configuration Control (R/W) Note: C-state values are processor
specific C-state code names, unrelated to MWAIT extension C-state parameters
or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
@@ -502,236 +609,6 @@ typedef union {
/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- * Bank MC5 reports MC error from the Intel QPI 0 module.
- * Bank MC6 reports MC error from the integrated I/O module.
- * Bank MC7 reports MC error from the home agent HA 0.
- * Bank MC8 reports MC error from the home agent HA 1.
- * Banks MC9 through MC16 report MC error from each channel of the integrated
- memory controllers.
- * Bank MC17 reports MC error from the following pair of CBo/L3 Slices
- (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.
- * Bank MC18 reports MC error from the following pair of CBo/L3 Slices
- (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.
- * Bank MC19 reports MC error from the following pair of CBo/L3 Slices
- (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.
- * Bank MC20 reports MC error from the Intel QPI 1 module.
- * Bank MC21 reports MC error from the Intel QPI 2 module.
-
- @param ECX MSR_HASWELL_E_MCi_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_CTL);
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_CTL, Msr);
- @endcode
- @note MSR_HASWELL_E_MC5_CTL is defined as MSR_MC5_CTL in SDM.
- MSR_HASWELL_E_MC6_CTL is defined as MSR_MC6_CTL in SDM.
- MSR_HASWELL_E_MC7_CTL is defined as MSR_MC7_CTL in SDM.
- MSR_HASWELL_E_MC8_CTL is defined as MSR_MC8_CTL in SDM.
- MSR_HASWELL_E_MC9_CTL is defined as MSR_MC9_CTL in SDM.
- MSR_HASWELL_E_MC10_CTL is defined as MSR_MC10_CTL in SDM.
- MSR_HASWELL_E_MC11_CTL is defined as MSR_MC11_CTL in SDM.
- MSR_HASWELL_E_MC12_CTL is defined as MSR_MC12_CTL in SDM.
- MSR_HASWELL_E_MC13_CTL is defined as MSR_MC13_CTL in SDM.
- MSR_HASWELL_E_MC14_CTL is defined as MSR_MC14_CTL in SDM.
- MSR_HASWELL_E_MC15_CTL is defined as MSR_MC15_CTL in SDM.
- MSR_HASWELL_E_MC16_CTL is defined as MSR_MC16_CTL in SDM.
- MSR_HASWELL_E_MC17_CTL is defined as MSR_MC17_CTL in SDM.
- MSR_HASWELL_E_MC18_CTL is defined as MSR_MC18_CTL in SDM.
- MSR_HASWELL_E_MC19_CTL is defined as MSR_MC19_CTL in SDM.
- MSR_HASWELL_E_MC20_CTL is defined as MSR_MC20_CTL in SDM.
- MSR_HASWELL_E_MC21_CTL is defined as MSR_MC21_CTL in SDM.
- @{
-**/
-#define MSR_HASWELL_E_MC5_CTL 0x00000414
-#define MSR_HASWELL_E_MC6_CTL 0x00000418
-#define MSR_HASWELL_E_MC7_CTL 0x0000041C
-#define MSR_HASWELL_E_MC8_CTL 0x00000420
-#define MSR_HASWELL_E_MC9_CTL 0x00000424
-#define MSR_HASWELL_E_MC10_CTL 0x00000428
-#define MSR_HASWELL_E_MC11_CTL 0x0000042C
-#define MSR_HASWELL_E_MC12_CTL 0x00000430
-#define MSR_HASWELL_E_MC13_CTL 0x00000434
-#define MSR_HASWELL_E_MC14_CTL 0x00000438
-#define MSR_HASWELL_E_MC15_CTL 0x0000043C
-#define MSR_HASWELL_E_MC16_CTL 0x00000440
-#define MSR_HASWELL_E_MC17_CTL 0x00000444
-#define MSR_HASWELL_E_MC18_CTL 0x00000448
-#define MSR_HASWELL_E_MC19_CTL 0x0000044C
-#define MSR_HASWELL_E_MC20_CTL 0x00000450
-#define MSR_HASWELL_E_MC21_CTL 0x00000454
-/// @}
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_HASWELL_E_MCi_STATUS
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_STATUS);
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_STATUS, Msr);
- @endcode
- @note MSR_HASWELL_E_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
- MSR_HASWELL_E_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.
- MSR_HASWELL_E_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.
- MSR_HASWELL_E_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.
- MSR_HASWELL_E_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.
- MSR_HASWELL_E_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
- MSR_HASWELL_E_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
- MSR_HASWELL_E_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
- MSR_HASWELL_E_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
- MSR_HASWELL_E_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
- MSR_HASWELL_E_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
- MSR_HASWELL_E_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
- MSR_HASWELL_E_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.
- MSR_HASWELL_E_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.
- MSR_HASWELL_E_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.
- MSR_HASWELL_E_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.
- MSR_HASWELL_E_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.
- @{
-**/
-#define MSR_HASWELL_E_MC5_STATUS 0x00000415
-#define MSR_HASWELL_E_MC6_STATUS 0x00000419
-#define MSR_HASWELL_E_MC7_STATUS 0x0000041D
-#define MSR_HASWELL_E_MC8_STATUS 0x00000421
-#define MSR_HASWELL_E_MC9_STATUS 0x00000425
-#define MSR_HASWELL_E_MC10_STATUS 0x00000429
-#define MSR_HASWELL_E_MC11_STATUS 0x0000042D
-#define MSR_HASWELL_E_MC12_STATUS 0x00000431
-#define MSR_HASWELL_E_MC13_STATUS 0x00000435
-#define MSR_HASWELL_E_MC14_STATUS 0x00000439
-#define MSR_HASWELL_E_MC15_STATUS 0x0000043D
-#define MSR_HASWELL_E_MC16_STATUS 0x00000441
-#define MSR_HASWELL_E_MC17_STATUS 0x00000445
-#define MSR_HASWELL_E_MC18_STATUS 0x00000449
-#define MSR_HASWELL_E_MC19_STATUS 0x0000044D
-#define MSR_HASWELL_E_MC20_STATUS 0x00000451
-#define MSR_HASWELL_E_MC21_STATUS 0x00000455
-/// @}
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_HASWELL_E_MCi_ADDR
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_ADDR);
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_ADDR, Msr);
- @endcode
- @note MSR_HASWELL_E_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
- MSR_HASWELL_E_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.
- MSR_HASWELL_E_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.
- MSR_HASWELL_E_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.
- MSR_HASWELL_E_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.
- MSR_HASWELL_E_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.
- MSR_HASWELL_E_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.
- MSR_HASWELL_E_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.
- MSR_HASWELL_E_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.
- MSR_HASWELL_E_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.
- MSR_HASWELL_E_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.
- MSR_HASWELL_E_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.
- MSR_HASWELL_E_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.
- MSR_HASWELL_E_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.
- MSR_HASWELL_E_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.
- MSR_HASWELL_E_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.
- MSR_HASWELL_E_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.
- @{
-**/
-#define MSR_HASWELL_E_MC5_ADDR 0x00000416
-#define MSR_HASWELL_E_MC6_ADDR 0x0000041A
-#define MSR_HASWELL_E_MC7_ADDR 0x0000041E
-#define MSR_HASWELL_E_MC8_ADDR 0x00000422
-#define MSR_HASWELL_E_MC9_ADDR 0x00000426
-#define MSR_HASWELL_E_MC10_ADDR 0x0000042A
-#define MSR_HASWELL_E_MC11_ADDR 0x0000042E
-#define MSR_HASWELL_E_MC12_ADDR 0x00000432
-#define MSR_HASWELL_E_MC13_ADDR 0x00000436
-#define MSR_HASWELL_E_MC14_ADDR 0x0000043A
-#define MSR_HASWELL_E_MC15_ADDR 0x0000043E
-#define MSR_HASWELL_E_MC16_ADDR 0x00000442
-#define MSR_HASWELL_E_MC17_ADDR 0x00000446
-#define MSR_HASWELL_E_MC18_ADDR 0x0000044A
-#define MSR_HASWELL_E_MC19_ADDR 0x0000044E
-#define MSR_HASWELL_E_MC20_ADDR 0x00000452
-#define MSR_HASWELL_E_MC21_ADDR 0x00000456
-/// @}
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_HASWELL_E_MCi_MISC
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_E_MC5_MISC);
- AsmWriteMsr64 (MSR_HASWELL_E_MC5_MISC, Msr);
- @endcode
- @note MSR_HASWELL_E_MC5_MISC is defined as MSR_MC5_MISC in SDM.
- MSR_HASWELL_E_MC6_MISC is defined as MSR_MC6_MISC in SDM.
- MSR_HASWELL_E_MC7_MISC is defined as MSR_MC7_MISC in SDM.
- MSR_HASWELL_E_MC8_MISC is defined as MSR_MC8_MISC in SDM.
- MSR_HASWELL_E_MC9_MISC is defined as MSR_MC9_MISC in SDM.
- MSR_HASWELL_E_MC10_MISC is defined as MSR_MC10_MISC in SDM.
- MSR_HASWELL_E_MC11_MISC is defined as MSR_MC11_MISC in SDM.
- MSR_HASWELL_E_MC12_MISC is defined as MSR_MC12_MISC in SDM.
- MSR_HASWELL_E_MC13_MISC is defined as MSR_MC13_MISC in SDM.
- MSR_HASWELL_E_MC14_MISC is defined as MSR_MC14_MISC in SDM.
- MSR_HASWELL_E_MC15_MISC is defined as MSR_MC15_MISC in SDM.
- MSR_HASWELL_E_MC16_MISC is defined as MSR_MC16_MISC in SDM.
- MSR_HASWELL_E_MC17_MISC is defined as MSR_MC17_MISC in SDM.
- MSR_HASWELL_E_MC18_MISC is defined as MSR_MC18_MISC in SDM.
- MSR_HASWELL_E_MC19_MISC is defined as MSR_MC19_MISC in SDM.
- MSR_HASWELL_E_MC20_MISC is defined as MSR_MC20_MISC in SDM.
- MSR_HASWELL_E_MC21_MISC is defined as MSR_MC21_MISC in SDM.
- @{
-**/
-#define MSR_HASWELL_E_MC5_MISC 0x00000417
-#define MSR_HASWELL_E_MC6_MISC 0x0000041B
-#define MSR_HASWELL_E_MC7_MISC 0x0000041F
-#define MSR_HASWELL_E_MC8_MISC 0x00000423
-#define MSR_HASWELL_E_MC9_MISC 0x00000427
-#define MSR_HASWELL_E_MC10_MISC 0x0000042B
-#define MSR_HASWELL_E_MC11_MISC 0x0000042F
-#define MSR_HASWELL_E_MC12_MISC 0x00000433
-#define MSR_HASWELL_E_MC13_MISC 0x00000437
-#define MSR_HASWELL_E_MC14_MISC 0x0000043B
-#define MSR_HASWELL_E_MC15_MISC 0x0000043F
-#define MSR_HASWELL_E_MC16_MISC 0x00000443
-#define MSR_HASWELL_E_MC17_MISC 0x00000447
-#define MSR_HASWELL_E_MC18_MISC 0x0000044B
-#define MSR_HASWELL_E_MC19_MISC 0x0000044F
-#define MSR_HASWELL_E_MC20_MISC 0x00000453
-#define MSR_HASWELL_E_MC21_MISC 0x00000457
-/// @}
-
-
-/**
Package. Unit Multipliers used in RAPL Interfaces (R/O).
@param ECX MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)
@@ -811,22 +688,49 @@ typedef union {
/**
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
+ Package. DRAM Energy Status (R/O) Energy Consumed by DRAM devices.
@param ECX MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)
@param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
@param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
<b>Example usage</b>
@code
- UINT64 Msr;
+ MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Msr;
- Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);
@endcode
@note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
**/
#define MSR_HASWELL_E_DRAM_ENERGY_STATUS 0x00000619
+/**
+ MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
+ /// to enable DRAM RAPL mode 0 (Direct VR).
+ ///
+ UINT32 Energy:32;
+ UINT32 Reserved:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;
+
/**
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
@@ -867,6 +771,83 @@ typedef union {
/**
+ Package. Configuration of PCIE PLL Relative to BCLK(R/W).
+
+ @param ECX MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);
+ AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);
+ @endcode
+ @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.
+**/
+#define MSR_HASWELL_E_PCIE_PLL_RATIO 0x0000061E
+
+/**
+ MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz
+ /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use
+ /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz
+ /// operation.
+ ///
+ UINT32 PCIERatio:2;
+ ///
+ /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of
+ /// PCIE Ratio.
+ ///
+ UINT32 LPLLSelect:1;
+ ///
+ /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out
+ /// before re-locking Gen2/Gen3 PLLs.
+ ///
+ UINT32 LONGRESET:1;
+ UINT32 Reserved1:28;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;
+
+
+/**
+ Package. Reserved (R/O) Reads return 0.
+
+ @param ECX MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);
+ @endcode
+ @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_PP0_ENERGY_STATUS 0x00000639
+
+
+/**
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
refers to processor core frequency).
@@ -1048,7 +1029,7 @@ typedef union {
/**
THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,
- ECX=0):EBX.PQM[bit 12] = 1.
+ ECX=0):EBX.RDT-M[bit 12] = 1.
@param ECX MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
index f7cb6ce..8bf2c38 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-10.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.11.
**/
@@ -442,15 +442,8 @@ typedef union {
UINT32 InterruptResponseTimeLimit:10;
///
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
- /// unit of the interrupt response time limit. The following time unit
- /// encodings are supported:
- ///
- /// 000b: 1 ns
- /// 001b: 32 ns
- /// 010b: 1024 ns
- /// 011b: 32768 ns
- /// 100b: 1048576 ns
- /// 101b: 33554432 ns.
+ /// unit of the interrupt response time limit. See Table 35-18 for
+ /// supported time unit encodings.
///
UINT32 TimeUnit:3;
UINT32 Reserved1:2;
@@ -514,15 +507,8 @@ typedef union {
UINT32 InterruptResponseTimeLimit:10;
///
/// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
- /// unit of the interrupt response time limit. The following time unit
- /// encodings are supported:
- ///
- /// 000b: 1 ns
- /// 001b: 32 ns
- /// 010b: 1024 ns
- /// 011b: 32768 ns
- /// 100b: 1048576 ns
- /// 101b: 33554432 ns.
+ /// unit of the interrupt response time limit. See Table 35-18 for
+ /// supported time unit encodings.
///
UINT32 TimeUnit:3;
UINT32 Reserved1:2;
@@ -864,25 +850,6 @@ typedef union {
/**
- Package. Silicon Debug Feature Control (R/W) See Table 35-2.
-
- @param ECX MSR_HASWELL_IA32_DEBUG_FEATURE (0x00000C80)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE);
- AsmWriteMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE, Msr);
- @endcode
- @note MSR_HASWELL_IA32_DEBUG_FEATURE is defined as IA32_DEBUG_FEATURE in SDM.
-**/
-#define MSR_HASWELL_IA32_DEBUG_FEATURE 0x00000C80
-
-
-/**
Core. C-State Configuration Control (R/W) Note: C-state values are processor
specific C-state code names, unrelated to MWAIT extension C-state parameters
or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__.
@@ -1610,6 +1577,25 @@ typedef union {
/**
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
+ Domains.".
+
+ @param ECX MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);
+ @endcode
+ @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639
+
+
+/**
Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
RAPL Domains.".
diff --git a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
index d278d52..41cbd2e 100644
--- a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-9.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.10.
**/
@@ -201,6 +201,25 @@ typedef union {
/**
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
+ Domains.".
+
+ @param ECX MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS);
+ @endcode
+ @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639
+
+
+/**
Package. Base TDP Ratio (R/O).
@param ECX MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)
@@ -813,95 +832,66 @@ typedef union {
/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.". Bank MC5 reports MC error from the Intel
- QPI module.
-
- * Bank MC6 reports MC error from the integrated I/O module.
- * Banks MC7 and MC 8 report MC error from the two home agents.
- * Banks MC9 through MC 16 report MC error from each channel of the integrated
- memory controllers.
- * Banks MC17 through MC31 reports MC error from a specific CBo
- (core broadcast) and its corresponding slice of L3.
-
- @param ECX MSR_IVY_BRIDGE_MCi_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_CTL);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_CTL, Msr);
- @endcode
- @note MSR_IVY_BRIDGE_MC5_CTL is defined as MSR_MC5_CTL in SDM.
- MSR_IVY_BRIDGE_MC6_CTL is defined as MSR_MC6_CTL in SDM.
- MSR_IVY_BRIDGE_MC7_CTL is defined as MSR_MC7_CTL in SDM.
- MSR_IVY_BRIDGE_MC8_CTL is defined as MSR_MC8_CTL in SDM.
- MSR_IVY_BRIDGE_MC9_CTL is defined as MSR_MC9_CTL in SDM.
- MSR_IVY_BRIDGE_MC10_CTL is defined as MSR_MC10_CTL in SDM.
- MSR_IVY_BRIDGE_MC11_CTL is defined as MSR_MC11_CTL in SDM.
- MSR_IVY_BRIDGE_MC12_CTL is defined as MSR_MC12_CTL in SDM.
- MSR_IVY_BRIDGE_MC13_CTL is defined as MSR_MC13_CTL in SDM.
- MSR_IVY_BRIDGE_MC14_CTL is defined as MSR_MC14_CTL in SDM.
- MSR_IVY_BRIDGE_MC15_CTL is defined as MSR_MC15_CTL in SDM.
- MSR_IVY_BRIDGE_MC16_CTL is defined as MSR_MC16_CTL in SDM.
- MSR_IVY_BRIDGE_MC17_CTL is defined as MSR_MC17_CTL in SDM.
- MSR_IVY_BRIDGE_MC18_CTL is defined as MSR_MC18_CTL in SDM.
- MSR_IVY_BRIDGE_MC19_CTL is defined as MSR_MC19_CTL in SDM.
- MSR_IVY_BRIDGE_MC20_CTL is defined as MSR_MC20_CTL in SDM.
- MSR_IVY_BRIDGE_MC21_CTL is defined as MSR_MC21_CTL in SDM.
- MSR_IVY_BRIDGE_MC22_CTL is defined as MSR_MC22_CTL in SDM.
- MSR_IVY_BRIDGE_MC23_CTL is defined as MSR_MC23_CTL in SDM.
- MSR_IVY_BRIDGE_MC24_CTL is defined as MSR_MC24_CTL in SDM.
- MSR_IVY_BRIDGE_MC25_CTL is defined as MSR_MC25_CTL in SDM.
- MSR_IVY_BRIDGE_MC26_CTL is defined as MSR_MC26_CTL in SDM.
- MSR_IVY_BRIDGE_MC27_CTL is defined as MSR_MC27_CTL in SDM.
- MSR_IVY_BRIDGE_MC28_CTL is defined as MSR_MC28_CTL in SDM.
- MSR_IVY_BRIDGE_MC29_CTL is defined as MSR_MC29_CTL in SDM.
- MSR_IVY_BRIDGE_MC30_CTL is defined as MSR_MC30_CTL in SDM.
- MSR_IVY_BRIDGE_MC31_CTL is defined as MSR_MC31_CTL in SDM.
- @{
+ Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.
+
+ @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);
+ @endcode
+ @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
**/
-#define MSR_IVY_BRIDGE_MC5_CTL 0x00000414
-#define MSR_IVY_BRIDGE_MC6_CTL 0x00000418
-#define MSR_IVY_BRIDGE_MC7_CTL 0x0000041C
-#define MSR_IVY_BRIDGE_MC8_CTL 0x00000420
-#define MSR_IVY_BRIDGE_MC9_CTL 0x00000424
-#define MSR_IVY_BRIDGE_MC10_CTL 0x00000428
-#define MSR_IVY_BRIDGE_MC11_CTL 0x0000042C
-#define MSR_IVY_BRIDGE_MC12_CTL 0x00000430
-#define MSR_IVY_BRIDGE_MC13_CTL 0x00000434
-#define MSR_IVY_BRIDGE_MC14_CTL 0x00000438
-#define MSR_IVY_BRIDGE_MC15_CTL 0x0000043C
-#define MSR_IVY_BRIDGE_MC16_CTL 0x00000440
-#define MSR_IVY_BRIDGE_MC17_CTL 0x00000444
-#define MSR_IVY_BRIDGE_MC18_CTL 0x00000448
-#define MSR_IVY_BRIDGE_MC19_CTL 0x0000044C
-#define MSR_IVY_BRIDGE_MC20_CTL 0x00000450
-#define MSR_IVY_BRIDGE_MC21_CTL 0x00000454
-#define MSR_IVY_BRIDGE_MC22_CTL 0x00000458
-#define MSR_IVY_BRIDGE_MC23_CTL 0x0000045C
-#define MSR_IVY_BRIDGE_MC24_CTL 0x00000460
-#define MSR_IVY_BRIDGE_MC25_CTL 0x00000464
-#define MSR_IVY_BRIDGE_MC26_CTL 0x00000468
-#define MSR_IVY_BRIDGE_MC27_CTL 0x0000046C
-#define MSR_IVY_BRIDGE_MC28_CTL 0x00000470
-#define MSR_IVY_BRIDGE_MC29_CTL 0x00000474
-#define MSR_IVY_BRIDGE_MC30_CTL 0x00000478
-#define MSR_IVY_BRIDGE_MC31_CTL 0x0000047C
-/// @}
+#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B
+
+/**
+ MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 5:0] Recoverable Address LSB.
+ ///
+ UINT32 RecoverableAddressLSB:6;
+ ///
+ /// [Bits 8:6] Address Mode.
+ ///
+ UINT32 AddressMode:3;
+ UINT32 Reserved1:7;
+ ///
+ /// [Bits 31:16] PCI Express Requestor ID.
+ ///
+ UINT32 PCIExpressRequestorID:16;
+ ///
+ /// [Bits 39:32] PCI Express Segment Number.
+ ///
+ UINT32 PCIExpressSegmentNumber:8;
+ UINT32 Reserved2:24;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;
/**
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
15.3.2.4, "IA32_MCi_MISC MSRs.".
- Bank MC20 reports MC error from a specific CBo (core broadcast) and
- its corresponding slice of L3.
+ Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
+ and its corresponding slice of L3.
- @param ECX MSR_IVY_BRIDGE_MCi_STATUS
+ @param ECX MSR_IVY_BRIDGE_IA32_MCi_CTL
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -909,65 +899,17 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_STATUS);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_STATUS, Msr);
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);
@endcode
- @note MSR_IVY_BRIDGE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
- MSR_IVY_BRIDGE_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.
- MSR_IVY_BRIDGE_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.
- MSR_IVY_BRIDGE_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.
- MSR_IVY_BRIDGE_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.
- MSR_IVY_BRIDGE_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
- MSR_IVY_BRIDGE_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
- MSR_IVY_BRIDGE_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
- MSR_IVY_BRIDGE_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
- MSR_IVY_BRIDGE_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
- MSR_IVY_BRIDGE_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
- MSR_IVY_BRIDGE_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
- MSR_IVY_BRIDGE_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.
- MSR_IVY_BRIDGE_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.
- MSR_IVY_BRIDGE_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.
- MSR_IVY_BRIDGE_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.
- MSR_IVY_BRIDGE_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.
- MSR_IVY_BRIDGE_MC22_STATUS is defined as MSR_MC22_STATUS in SDM.
- MSR_IVY_BRIDGE_MC23_STATUS is defined as MSR_MC23_STATUS in SDM.
- MSR_IVY_BRIDGE_MC24_STATUS is defined as MSR_MC24_STATUS in SDM.
- MSR_IVY_BRIDGE_MC25_STATUS is defined as MSR_MC25_STATUS in SDM.
- MSR_IVY_BRIDGE_MC26_STATUS is defined as MSR_MC26_STATUS in SDM.
- MSR_IVY_BRIDGE_MC27_STATUS is defined as MSR_MC27_STATUS in SDM.
- MSR_IVY_BRIDGE_MC28_STATUS is defined as MSR_MC28_STATUS in SDM.
- MSR_IVY_BRIDGE_MC29_STATUS is defined as MSR_MC29_STATUS in SDM.
- MSR_IVY_BRIDGE_MC30_STATUS is defined as MSR_MC30_STATUS in SDM.
- MSR_IVY_BRIDGE_MC31_STATUS is defined as MSR_MC31_STATUS in SDM.
+ @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM.
+ MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM.
+ MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.
@{
**/
-#define MSR_IVY_BRIDGE_MC5_STATUS 0x00000415
-#define MSR_IVY_BRIDGE_MC6_STATUS 0x00000419
-#define MSR_IVY_BRIDGE_MC7_STATUS 0x0000041D
-#define MSR_IVY_BRIDGE_MC8_STATUS 0x00000421
-#define MSR_IVY_BRIDGE_MC9_STATUS 0x00000425
-#define MSR_IVY_BRIDGE_MC10_STATUS 0x00000429
-#define MSR_IVY_BRIDGE_MC11_STATUS 0x0000042D
-#define MSR_IVY_BRIDGE_MC12_STATUS 0x00000431
-#define MSR_IVY_BRIDGE_MC13_STATUS 0x00000435
-#define MSR_IVY_BRIDGE_MC14_STATUS 0x00000439
-#define MSR_IVY_BRIDGE_MC15_STATUS 0x0000043D
-#define MSR_IVY_BRIDGE_MC16_STATUS 0x00000441
-#define MSR_IVY_BRIDGE_MC17_STATUS 0x00000445
-#define MSR_IVY_BRIDGE_MC18_STATUS 0x00000449
-#define MSR_IVY_BRIDGE_MC19_STATUS 0x0000044D
-#define MSR_IVY_BRIDGE_MC20_STATUS 0x00000451
-#define MSR_IVY_BRIDGE_MC21_STATUS 0x00000455
-#define MSR_IVY_BRIDGE_MC22_STATUS 0x00000459
-#define MSR_IVY_BRIDGE_MC23_STATUS 0x0000045D
-#define MSR_IVY_BRIDGE_MC24_STATUS 0x00000461
-#define MSR_IVY_BRIDGE_MC25_STATUS 0x00000465
-#define MSR_IVY_BRIDGE_MC26_STATUS 0x00000469
-#define MSR_IVY_BRIDGE_MC27_STATUS 0x0000046D
-#define MSR_IVY_BRIDGE_MC28_STATUS 0x00000471
-#define MSR_IVY_BRIDGE_MC29_STATUS 0x00000475
-#define MSR_IVY_BRIDGE_MC30_STATUS 0x00000479
-#define MSR_IVY_BRIDGE_MC31_STATUS 0x0000047D
+#define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474
+#define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478
+#define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C
/// @}
@@ -975,7 +917,10 @@ typedef union {
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
15.3.2.4, "IA32_MCi_MISC MSRs.".
- @param ECX MSR_IVY_BRIDGE_MCi_ADDR
+ Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
+ and its corresponding slice of L3.
+
+ @param ECX MSR_IVY_BRIDGE_IA32_MCi_STATUS
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -983,65 +928,17 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_ADDR);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_ADDR, Msr);
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);
@endcode
- @note MSR_IVY_BRIDGE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
- MSR_IVY_BRIDGE_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.
- MSR_IVY_BRIDGE_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.
- MSR_IVY_BRIDGE_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.
- MSR_IVY_BRIDGE_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.
- MSR_IVY_BRIDGE_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.
- MSR_IVY_BRIDGE_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.
- MSR_IVY_BRIDGE_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.
- MSR_IVY_BRIDGE_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.
- MSR_IVY_BRIDGE_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.
- MSR_IVY_BRIDGE_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.
- MSR_IVY_BRIDGE_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.
- MSR_IVY_BRIDGE_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.
- MSR_IVY_BRIDGE_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.
- MSR_IVY_BRIDGE_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.
- MSR_IVY_BRIDGE_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.
- MSR_IVY_BRIDGE_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.
- MSR_IVY_BRIDGE_MC22_ADDR is defined as MSR_MC22_ADDR in SDM.
- MSR_IVY_BRIDGE_MC23_ADDR is defined as MSR_MC23_ADDR in SDM.
- MSR_IVY_BRIDGE_MC24_ADDR is defined as MSR_MC24_ADDR in SDM.
- MSR_IVY_BRIDGE_MC25_ADDR is defined as MSR_MC25_ADDR in SDM.
- MSR_IVY_BRIDGE_MC26_ADDR is defined as MSR_MC26_ADDR in SDM.
- MSR_IVY_BRIDGE_MC27_ADDR is defined as MSR_MC27_ADDR in SDM.
- MSR_IVY_BRIDGE_MC28_ADDR is defined as MSR_MC28_ADDR in SDM.
- MSR_IVY_BRIDGE_MC29_ADDR is defined as MSR_MC29_ADDR in SDM.
- MSR_IVY_BRIDGE_MC30_ADDR is defined as MSR_MC30_ADDR in SDM.
- MSR_IVY_BRIDGE_MC31_ADDR is defined as MSR_MC31_ADDR in SDM.
+ @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM.
+ MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM.
+ MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.
@{
**/
-#define MSR_IVY_BRIDGE_MC5_ADDR 0x00000416
-#define MSR_IVY_BRIDGE_MC6_ADDR 0x0000041A
-#define MSR_IVY_BRIDGE_MC7_ADDR 0x0000041E
-#define MSR_IVY_BRIDGE_MC8_ADDR 0x00000422
-#define MSR_IVY_BRIDGE_MC9_ADDR 0x00000426
-#define MSR_IVY_BRIDGE_MC10_ADDR 0x0000042A
-#define MSR_IVY_BRIDGE_MC11_ADDR 0x0000042E
-#define MSR_IVY_BRIDGE_MC12_ADDR 0x00000432
-#define MSR_IVY_BRIDGE_MC13_ADDR 0x00000436
-#define MSR_IVY_BRIDGE_MC14_ADDR 0x0000043A
-#define MSR_IVY_BRIDGE_MC15_ADDR 0x0000043E
-#define MSR_IVY_BRIDGE_MC16_ADDR 0x00000442
-#define MSR_IVY_BRIDGE_MC17_ADDR 0x00000446
-#define MSR_IVY_BRIDGE_MC18_ADDR 0x0000044A
-#define MSR_IVY_BRIDGE_MC19_ADDR 0x0000044E
-#define MSR_IVY_BRIDGE_MC20_ADDR 0x00000452
-#define MSR_IVY_BRIDGE_MC21_ADDR 0x00000456
-#define MSR_IVY_BRIDGE_MC22_ADDR 0x0000045A
-#define MSR_IVY_BRIDGE_MC23_ADDR 0x0000045E
-#define MSR_IVY_BRIDGE_MC24_ADDR 0x00000462
-#define MSR_IVY_BRIDGE_MC25_ADDR 0x00000466
-#define MSR_IVY_BRIDGE_MC26_ADDR 0x0000046A
-#define MSR_IVY_BRIDGE_MC27_ADDR 0x0000046E
-#define MSR_IVY_BRIDGE_MC28_ADDR 0x00000472
-#define MSR_IVY_BRIDGE_MC29_ADDR 0x00000476
-#define MSR_IVY_BRIDGE_MC30_ADDR 0x0000047A
-#define MSR_IVY_BRIDGE_MC31_ADDR 0x0000047E
+#define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475
+#define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479
+#define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D
/// @}
@@ -1049,7 +946,10 @@ typedef union {
Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
15.3.2.4, "IA32_MCi_MISC MSRs.".
- @param ECX MSR_IVY_BRIDGE_MCi_MISC
+ Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
+ and its corresponding slice of L3.
+
+ @param ECX MSR_IVY_BRIDGE_IA32_MCi_ADDR
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -1057,119 +957,47 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_MISC);
- AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_MISC, Msr);
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);
@endcode
- @note MSR_IVY_BRIDGE_MC5_MISC is defined as MSR_MC5_MISC in SDM.
- MSR_IVY_BRIDGE_MC6_MISC is defined as MSR_MC6_MISC in SDM.
- MSR_IVY_BRIDGE_MC7_MISC is defined as MSR_MC7_MISC in SDM.
- MSR_IVY_BRIDGE_MC8_MISC is defined as MSR_MC8_MISC in SDM.
- MSR_IVY_BRIDGE_MC9_MISC is defined as MSR_MC9_MISC in SDM.
- MSR_IVY_BRIDGE_MC10_MISC is defined as MSR_MC10_MISC in SDM.
- MSR_IVY_BRIDGE_MC11_MISC is defined as MSR_MC11_MISC in SDM.
- MSR_IVY_BRIDGE_MC12_MISC is defined as MSR_MC12_MISC in SDM.
- MSR_IVY_BRIDGE_MC13_MISC is defined as MSR_MC13_MISC in SDM.
- MSR_IVY_BRIDGE_MC14_MISC is defined as MSR_MC14_MISC in SDM.
- MSR_IVY_BRIDGE_MC15_MISC is defined as MSR_MC15_MISC in SDM.
- MSR_IVY_BRIDGE_MC16_MISC is defined as MSR_MC16_MISC in SDM.
- MSR_IVY_BRIDGE_MC17_MISC is defined as MSR_MC17_MISC in SDM.
- MSR_IVY_BRIDGE_MC18_MISC is defined as MSR_MC18_MISC in SDM.
- MSR_IVY_BRIDGE_MC19_MISC is defined as MSR_MC19_MISC in SDM.
- MSR_IVY_BRIDGE_MC20_MISC is defined as MSR_MC20_MISC in SDM.
- MSR_IVY_BRIDGE_MC21_MISC is defined as MSR_MC21_MISC in SDM.
- MSR_IVY_BRIDGE_MC22_MISC is defined as MSR_MC22_MISC in SDM.
- MSR_IVY_BRIDGE_MC23_MISC is defined as MSR_MC23_MISC in SDM.
- MSR_IVY_BRIDGE_MC24_MISC is defined as MSR_MC24_MISC in SDM.
- MSR_IVY_BRIDGE_MC25_MISC is defined as MSR_MC25_MISC in SDM.
- MSR_IVY_BRIDGE_MC26_MISC is defined as MSR_MC26_MISC in SDM.
- MSR_IVY_BRIDGE_MC27_MISC is defined as MSR_MC27_MISC in SDM.
- MSR_IVY_BRIDGE_MC28_MISC is defined as MSR_MC28_MISC in SDM.
- MSR_IVY_BRIDGE_MC29_MISC is defined as MSR_MC29_MISC in SDM.
- MSR_IVY_BRIDGE_MC30_MISC is defined as MSR_MC30_MISC in SDM.
- MSR_IVY_BRIDGE_MC31_MISC is defined as MSR_MC31_MISC in SDM.
+ @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM.
+ MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM.
+ MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.
@{
**/
-#define MSR_IVY_BRIDGE_MC5_MISC 0x00000417
-#define MSR_IVY_BRIDGE_MC6_MISC 0x0000041B
-#define MSR_IVY_BRIDGE_MC7_MISC 0x0000041F
-#define MSR_IVY_BRIDGE_MC8_MISC 0x00000423
-#define MSR_IVY_BRIDGE_MC9_MISC 0x00000427
-#define MSR_IVY_BRIDGE_MC10_MISC 0x0000042B
-#define MSR_IVY_BRIDGE_MC11_MISC 0x0000042F
-#define MSR_IVY_BRIDGE_MC12_MISC 0x00000433
-#define MSR_IVY_BRIDGE_MC13_MISC 0x00000437
-#define MSR_IVY_BRIDGE_MC14_MISC 0x0000043B
-#define MSR_IVY_BRIDGE_MC15_MISC 0x0000043F
-#define MSR_IVY_BRIDGE_MC16_MISC 0x00000443
-#define MSR_IVY_BRIDGE_MC17_MISC 0x00000447
-#define MSR_IVY_BRIDGE_MC18_MISC 0x0000044B
-#define MSR_IVY_BRIDGE_MC19_MISC 0x0000044F
-#define MSR_IVY_BRIDGE_MC20_MISC 0x00000453
-#define MSR_IVY_BRIDGE_MC21_MISC 0x00000457
-#define MSR_IVY_BRIDGE_MC22_MISC 0x0000045B
-#define MSR_IVY_BRIDGE_MC23_MISC 0x0000045F
-#define MSR_IVY_BRIDGE_MC24_MISC 0x00000463
-#define MSR_IVY_BRIDGE_MC25_MISC 0x00000467
-#define MSR_IVY_BRIDGE_MC26_MISC 0x0000046B
-#define MSR_IVY_BRIDGE_MC27_MISC 0x0000046F
-#define MSR_IVY_BRIDGE_MC28_MISC 0x00000473
-#define MSR_IVY_BRIDGE_MC29_MISC 0x00000477
-#define MSR_IVY_BRIDGE_MC30_MISC 0x0000047B
-#define MSR_IVY_BRIDGE_MC31_MISC 0x0000047F
+#define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476
+#define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A
+#define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E
/// @}
/**
- Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".
- @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)
+ Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
+ and its corresponding slice of L3.
+
+ @param ECX MSR_IVY_BRIDGE_IA32_MCi_MISC
@param EAX Lower 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
@param EDX Upper 32-bits of MSR value.
- Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
<b>Example usage</b>
@code
- MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr;
+ UINT64 Msr;
- Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);
+ Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);
+ AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);
@endcode
- @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
-**/
-#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B
-
-/**
- MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC
+ @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM.
+ MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM.
+ MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.
+ @{
**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 5:0] Recoverable Address LSB.
- ///
- UINT32 RecoverableAddressLSB:6;
- ///
- /// [Bits 8:6] Address Mode.
- ///
- UINT32 AddressMode:3;
- UINT32 Reserved1:7;
- ///
- /// [Bits 31:16] PCI Express Requestor ID.
- ///
- UINT32 PCIExpressRequestorID:16;
- ///
- /// [Bits 39:32] PCI Express Segment Number.
- ///
- UINT32 PCIExpressSegmentNumber:8;
- UINT32 Reserved2:24;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;
+#define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477
+#define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B
+#define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F
+/// @}
/**
@@ -1267,7 +1095,7 @@ typedef union {
/**
- Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".
+ Thread. See Section 18.8.1.1, "Precise Event Based Sampling (PEBS).".
@param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
index 6f3d4f4..20e60df 100644
--- a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-5.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.6.
**/
@@ -254,7 +254,23 @@ typedef union {
/// auto-demote information.
///
UINT32 C1AutoDemotion:1;
- UINT32 Reserved4:5;
+ ///
+ /// [Bit 27] Enable C3 Undemotion (R/W).
+ ///
+ UINT32 C3Undemotion:1;
+ ///
+ /// [Bit 28] Enable C1 Undemotion (R/W).
+ ///
+ UINT32 C1Undemotion:1;
+ ///
+ /// [Bit 29] Package C State Demotion Enable (R/W).
+ ///
+ UINT32 CStateDemotion:1;
+ ///
+ /// [Bit 30] Package C State UnDemotion Enable (R/W).
+ ///
+ UINT32 CStateUndemotion:1;
+ UINT32 Reserved4:1;
UINT32 Reserved5:32;
} Bits;
///
@@ -364,7 +380,7 @@ typedef union {
UINT32 Reserved1:2;
///
/// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2.
+ /// Table 35-2. Default value is 1.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
@@ -378,7 +394,7 @@ typedef union {
///
UINT32 BTS:1;
///
- /// [Bit 12] Thread. Precise Event Based Sampling Unavailable (RO) See
+ /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
/// Table 35-2.
///
UINT32 PEBS:1;
@@ -744,7 +760,7 @@ typedef union {
/**
Core. Last Branch Record Filtering Select Register (R/W) See Section
- 17.6.2, "Filtering of Last Branch Records.".
+ 17.7.2, "Filtering of Last Branch Records.".
@param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)
@param EAX Lower 32-bits of MSR value.
@@ -933,46 +949,26 @@ typedef union {
/**
- Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
- Facilities.".
-
- @param ECX MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS, Msr);
- @endcode
- @note MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
-**/
-#define MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS 0x0000038E
-
-
-/**
Thread. (RO).
- @param ECX MSR_NEHALEM_PERF_GLOBAL_STAUS (0x0000038E)
+ @param ECX MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)
@param EAX Lower 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.
+ Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.
@param EDX Upper 32-bits of MSR value.
- Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.
+ Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.
<b>Example usage</b>
@code
- MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER Msr;
+ MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Msr;
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STAUS);
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);
@endcode
- @note MSR_NEHALEM_PERF_GLOBAL_STAUS is defined as MSR_PERF_GLOBAL_STAUS in SDM.
+ @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.
**/
-#define MSR_NEHALEM_PERF_GLOBAL_STAUS 0x0000038E
+#define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E
/**
- MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STAUS
+ MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS
**/
typedef union {
///
@@ -991,7 +987,7 @@ typedef union {
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
-} MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER;
+} MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER;
/**
@@ -1038,7 +1034,7 @@ typedef union {
/**
- Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".
+ Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".
@param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
@@ -1108,7 +1104,7 @@ typedef union {
/**
- Thread. See Section 18.7.1.2, "Load Latency Performance Monitoring
+ Thread. See Section 18.8.1.2, "Load Latency Performance Monitoring
Facility.".
@param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)
@@ -1266,256 +1262,11 @@ typedef union {
/**
- See Section 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_NEHALEM_MCi_MISC
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC0_MISC);
- AsmWriteMsr64 (MSR_NEHALEM_MC0_MISC, Msr);
- @endcode
- @note MSR_NEHALEM_MC0_MISC is defined as MSR_MC0_MISC in SDM.
- MSR_NEHALEM_MC1_MISC is defined as MSR_MC1_MISC in SDM.
- MSR_NEHALEM_MC2_MISC is defined as MSR_MC2_MISC in SDM.
- MSR_NEHALEM_MC3_MISC is defined as MSR_MC3_MISC in SDM.
- MSR_NEHALEM_MC4_MISC is defined as MSR_MC4_MISC in SDM.
- MSR_NEHALEM_MC5_MISC is defined as MSR_MC5_MISC in SDM.
- MSR_NEHALEM_MC6_MISC is defined as MSR_MC6_MISC in SDM.
- MSR_NEHALEM_MC7_MISC is defined as MSR_MC7_MISC in SDM.
- MSR_NEHALEM_MC8_MISC is defined as MSR_MC8_MISC in SDM.
- MSR_NEHALEM_MC9_MISC is defined as MSR_MC9_MISC in SDM.
- MSR_NEHALEM_MC10_MISC is defined as MSR_MC10_MISC in SDM.
- MSR_NEHALEM_MC11_MISC is defined as MSR_MC11_MISC in SDM.
- MSR_NEHALEM_MC12_MISC is defined as MSR_MC12_MISC in SDM.
- MSR_NEHALEM_MC13_MISC is defined as MSR_MC13_MISC in SDM.
- MSR_NEHALEM_MC14_MISC is defined as MSR_MC14_MISC in SDM.
- MSR_NEHALEM_MC15_MISC is defined as MSR_MC15_MISC in SDM.
- MSR_NEHALEM_MC16_MISC is defined as MSR_MC16_MISC in SDM.
- MSR_NEHALEM_MC17_MISC is defined as MSR_MC17_MISC in SDM.
- MSR_NEHALEM_MC18_MISC is defined as MSR_MC18_MISC in SDM.
- MSR_NEHALEM_MC19_MISC is defined as MSR_MC19_MISC in SDM.
- MSR_NEHALEM_MC20_MISC is defined as MSR_MC20_MISC in SDM.
- MSR_NEHALEM_MC21_MISC is defined as MSR_MC21_MISC in SDM.
- @{
-**/
-#define MSR_NEHALEM_MC0_MISC 0x00000403
-#define MSR_NEHALEM_MC1_MISC 0x00000407
-#define MSR_NEHALEM_MC2_MISC 0x0000040B
-#define MSR_NEHALEM_MC3_MISC 0x0000040F
-#define MSR_NEHALEM_MC4_MISC 0x00000413
-#define MSR_NEHALEM_MC5_MISC 0x00000417
-#define MSR_NEHALEM_MC6_MISC 0x0000041B
-#define MSR_NEHALEM_MC7_MISC 0x0000041F
-#define MSR_NEHALEM_MC8_MISC 0x00000423
-#define MSR_NEHALEM_MC9_MISC 0x00000427
-#define MSR_NEHALEM_MC10_MISC 0x0000042B
-#define MSR_NEHALEM_MC11_MISC 0x0000042F
-#define MSR_NEHALEM_MC12_MISC 0x00000433
-#define MSR_NEHALEM_MC13_MISC 0x00000437
-#define MSR_NEHALEM_MC14_MISC 0x0000043B
-#define MSR_NEHALEM_MC15_MISC 0x0000043F
-#define MSR_NEHALEM_MC16_MISC 0x00000443
-#define MSR_NEHALEM_MC17_MISC 0x00000447
-#define MSR_NEHALEM_MC18_MISC 0x0000044B
-#define MSR_NEHALEM_MC19_MISC 0x0000044F
-#define MSR_NEHALEM_MC20_MISC 0x00000453
-#define MSR_NEHALEM_MC21_MISC 0x00000457
-/// @}
-
-
-/**
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_NEHALEM_MCi_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_CTL);
- AsmWriteMsr64 (MSR_NEHALEM_MC3_CTL, Msr);
- @endcode
- @note MSR_NEHALEM_MC3_CTL is defined as MSR_MC3_CTL in SDM.
- MSR_NEHALEM_MC4_CTL is defined as MSR_MC4_CTL in SDM.
- MSR_NEHALEM_MC5_CTL is defined as MSR_MC5_CTL in SDM.
- MSR_NEHALEM_MC6_CTL is defined as MSR_MC6_CTL in SDM.
- MSR_NEHALEM_MC7_CTL is defined as MSR_MC7_CTL in SDM.
- MSR_NEHALEM_MC8_CTL is defined as MSR_MC8_CTL in SDM.
- MSR_NEHALEM_MC9_CTL is defined as MSR_MC9_CTL in SDM.
- MSR_NEHALEM_MC10_CTL is defined as MSR_MC10_CTL in SDM.
- MSR_NEHALEM_MC11_CTL is defined as MSR_MC11_CTL in SDM.
- MSR_NEHALEM_MC12_CTL is defined as MSR_MC12_CTL in SDM.
- MSR_NEHALEM_MC13_CTL is defined as MSR_MC13_CTL in SDM.
- MSR_NEHALEM_MC14_CTL is defined as MSR_MC14_CTL in SDM.
- MSR_NEHALEM_MC15_CTL is defined as MSR_MC15_CTL in SDM.
- MSR_NEHALEM_MC16_CTL is defined as MSR_MC16_CTL in SDM.
- MSR_NEHALEM_MC17_CTL is defined as MSR_MC17_CTL in SDM.
- MSR_NEHALEM_MC18_CTL is defined as MSR_MC18_CTL in SDM.
- MSR_NEHALEM_MC19_CTL is defined as MSR_MC19_CTL in SDM.
- MSR_NEHALEM_MC20_CTL is defined as MSR_MC20_CTL in SDM.
- MSR_NEHALEM_MC21_CTL is defined as MSR_MC21_CTL in SDM.
- @{
-**/
-#define MSR_NEHALEM_MC3_CTL 0x0000040C
-#define MSR_NEHALEM_MC4_CTL 0x00000410
-#define MSR_NEHALEM_MC5_CTL 0x00000414
-#define MSR_NEHALEM_MC6_CTL 0x00000418
-#define MSR_NEHALEM_MC7_CTL 0x0000041C
-#define MSR_NEHALEM_MC8_CTL 0x00000420
-#define MSR_NEHALEM_MC9_CTL 0x00000424
-#define MSR_NEHALEM_MC10_CTL 0x00000428
-#define MSR_NEHALEM_MC11_CTL 0x0000042C
-#define MSR_NEHALEM_MC12_CTL 0x00000430
-#define MSR_NEHALEM_MC13_CTL 0x00000434
-#define MSR_NEHALEM_MC14_CTL 0x00000438
-#define MSR_NEHALEM_MC15_CTL 0x0000043C
-#define MSR_NEHALEM_MC16_CTL 0x00000440
-#define MSR_NEHALEM_MC17_CTL 0x00000444
-#define MSR_NEHALEM_MC18_CTL 0x00000448
-#define MSR_NEHALEM_MC19_CTL 0x0000044C
-#define MSR_NEHALEM_MC20_CTL 0x00000450
-#define MSR_NEHALEM_MC21_CTL 0x00000454
-/// @}
-
-
-/**
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS," and Chapter 16.
-
- @param ECX MSR_NEHALEM_MCi_STATUS (0x0000040D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_STATUS);
- AsmWriteMsr64 (MSR_NEHALEM_MC3_STATUS, Msr);
- @endcode
- @note MSR_NEHALEM_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
- MSR_NEHALEM_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
- MSR_NEHALEM_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
- MSR_NEHALEM_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.
- MSR_NEHALEM_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.
- MSR_NEHALEM_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.
- MSR_NEHALEM_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.
- MSR_NEHALEM_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
- MSR_NEHALEM_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
- MSR_NEHALEM_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
- MSR_NEHALEM_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
- MSR_NEHALEM_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
- MSR_NEHALEM_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
- MSR_NEHALEM_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
- MSR_NEHALEM_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.
- MSR_NEHALEM_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.
- MSR_NEHALEM_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.
- MSR_NEHALEM_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.
- MSR_NEHALEM_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.
- @{
-**/
-#define MSR_NEHALEM_MC3_STATUS 0x0000040D
-#define MSR_NEHALEM_MC4_STATUS 0x00000411
-#define MSR_NEHALEM_MC5_STATUS 0x00000415
-#define MSR_NEHALEM_MC6_STATUS 0x00000419
-#define MSR_NEHALEM_MC7_STATUS 0x0000041D
-#define MSR_NEHALEM_MC8_STATUS 0x00000421
-#define MSR_NEHALEM_MC9_STATUS 0x00000425
-#define MSR_NEHALEM_MC10_STATUS 0x00000429
-#define MSR_NEHALEM_MC11_STATUS 0x0000042D
-#define MSR_NEHALEM_MC12_STATUS 0x00000431
-#define MSR_NEHALEM_MC13_STATUS 0x00000435
-#define MSR_NEHALEM_MC14_STATUS 0x00000439
-#define MSR_NEHALEM_MC15_STATUS 0x0000043D
-#define MSR_NEHALEM_MC16_STATUS 0x00000441
-#define MSR_NEHALEM_MC17_STATUS 0x00000445
-#define MSR_NEHALEM_MC18_STATUS 0x00000449
-#define MSR_NEHALEM_MC19_STATUS 0x0000044D
-#define MSR_NEHALEM_MC20_STATUS 0x00000451
-#define MSR_NEHALEM_MC21_STATUS 0x00000455
-/// @}
-
-
-/**
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs."
-
- The MSR_MC3_ADDR register is either not implemented or contains no address
- if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not
- implemented in the processor, all reads and writes to this MSR will cause a
- general-protection exception.
-
- The MSR_MC4_ADDR register is either not implemented or contains no address
- if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not
- implemented in the processor, all reads and writes to this MSR will cause a
- general-protection exception.
-
- @param ECX MSR_NEHALEM_MC3_ADDR (0x0000040E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_ADDR);
- AsmWriteMsr64 (MSR_NEHALEM_MC3_ADDR, Msr);
- @endcode
- @note MSR_NEHALEM_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
- MSR_NEHALEM_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
- MSR_NEHALEM_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
- MSR_NEHALEM_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.
- MSR_NEHALEM_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.
- MSR_NEHALEM_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.
- MSR_NEHALEM_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.
- MSR_NEHALEM_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.
- MSR_NEHALEM_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.
- MSR_NEHALEM_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.
- MSR_NEHALEM_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.
- MSR_NEHALEM_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.
- MSR_NEHALEM_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.
- MSR_NEHALEM_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.
- MSR_NEHALEM_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.
- MSR_NEHALEM_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.
- MSR_NEHALEM_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.
- MSR_NEHALEM_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.
- MSR_NEHALEM_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.
- @{
-**/
-#define MSR_NEHALEM_MC3_ADDR 0x0000040E
-#define MSR_NEHALEM_MC4_ADDR 0x00000412
-#define MSR_NEHALEM_MC5_ADDR 0x00000416
-#define MSR_NEHALEM_MC6_ADDR 0x0000041A
-#define MSR_NEHALEM_MC7_ADDR 0x0000041E
-#define MSR_NEHALEM_MC8_ADDR 0x00000422
-#define MSR_NEHALEM_MC9_ADDR 0x00000426
-#define MSR_NEHALEM_MC10_ADDR 0x0000042A
-#define MSR_NEHALEM_MC11_ADDR 0x0000042E
-#define MSR_NEHALEM_MC12_ADDR 0x00000432
-#define MSR_NEHALEM_MC13_ADDR 0x00000436
-#define MSR_NEHALEM_MC14_ADDR 0x0000043A
-#define MSR_NEHALEM_MC15_ADDR 0x0000043E
-#define MSR_NEHALEM_MC16_ADDR 0x00000442
-#define MSR_NEHALEM_MC17_ADDR 0x00000446
-#define MSR_NEHALEM_MC18_ADDR 0x0000044A
-#define MSR_NEHALEM_MC19_ADDR 0x0000044E
-#define MSR_NEHALEM_MC20_ADDR 0x00000452
-#define MSR_NEHALEM_MC21_ADDR 0x00000456
-/// @}
-
-
-/**
Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
- branch record registers on the last branch record stack. This part of the
- stack contains pointers to the source instruction for one of the last
- sixteen branches, exceptions, or interrupts taken by the processor. See
- also: - Last Branch Record Stack TOS at 1C9H - Section 17.6.1, "LBR
- Stack.".
+ branch record registers on the last branch record stack. The From_IP part of
+ the stack contains pointers to the source instruction. See also: - Last
+ Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in
+ Section 17.4.8.1.
@param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP
@param EAX Lower 32-bits of MSR value.
@@ -1568,8 +1319,7 @@ typedef union {
/**
Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
record registers on the last branch record stack. This part of the stack
- contains pointers to the destination instruction for one of the last sixteen
- branches, exceptions, or interrupts taken by the processor.
+ contains pointers to the destination instruction.
@param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP
@param EAX Lower 32-bits of MSR value.
@@ -1694,7 +1444,7 @@ typedef union {
/**
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)
@@ -1714,7 +1464,7 @@ typedef union {
/**
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)
@@ -1734,7 +1484,7 @@ typedef union {
/**
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)
@@ -1754,7 +1504,7 @@ typedef union {
/**
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)
@@ -1774,7 +1524,7 @@ typedef union {
/**
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management
Facility.".
@param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)
@@ -1794,7 +1544,7 @@ typedef union {
/**
- Package. See Section 18.7.2.3, "Uncore Address/Opcode Match MSR.".
+ Package. See Section 18.8.2.3, "Uncore Address/Opcode Match MSR.".
@param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)
@param EAX Lower 32-bits of MSR value.
@@ -1813,7 +1563,7 @@ typedef union {
/**
- Package. See Section 18.7.2.2, "Uncore Performance Event Configuration
+ Package. See Section 18.8.2.2, "Uncore Performance Event Configuration
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PMCi
@@ -1848,7 +1598,7 @@ typedef union {
/// @}
/**
- Package. See Section 18.7.2.2, "Uncore Performance Event Configuration
+ Package. See Section 18.8.2.2, "Uncore Performance Event Configuration
Facility.".
@param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi
diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
index a196330..ef90800 100644
--- a/UefiCpuPkg/Include/Register/Msr/P6Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-19.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.21.
**/
@@ -27,7 +27,7 @@
#include <Register/ArchitecturalMsr.h>
/**
- See Section 35.20, "MSRs in Pentium Processors.".
+ See Section 35.22, "MSRs in Pentium Processors.".
@param ECX MSR_P6_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@@ -46,7 +46,7 @@
/**
- See Section 35.20, "MSRs in Pentium Processors.".
+ See Section 35.22, "MSRs in Pentium Processors.".
@param ECX MSR_P6_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
index 306857f..6cf68b2 100644
--- a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.18.
**/
@@ -927,8 +927,8 @@ typedef union {
///
UINT32 BTS:1;
///
- /// [Bit 12] PEBS_UNAVILABLE: Precise Event Based Sampling Unavailable (R)
- /// See Table 35-2. When set, the processor does not support precise
+ /// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable
+ /// (R) See Table 35-2. When set, the processor does not support processor
/// event-based sampling (PEBS); when clear, PEBS is supported.
///
UINT32 PEBS:1;
@@ -1053,7 +1053,7 @@ typedef union {
0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains
a pointer to the last branch instruction that the processor executed prior
to the last exception that was generated or the last interrupt that was
- handled. See Section 17.10.3, "Last Exception Records.". Unique. From Linear
+ handled. See Section 17.11.3, "Last Exception Records.". Unique. From Linear
IP Linear address of the last branch instruction (If IA32e mode is active).
From Linear IP Linear address of the last branch instruction. Reserved.
@@ -1076,7 +1076,7 @@ typedef union {
0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area
contains a pointer to the target of the last branch instruction that the
processor executed prior to the last exception that was generated or the
- last interrupt that was handled. See Section 17.10.3, "Last Exception
+ last interrupt that was handled. See Section 17.11.3, "Last Exception
Records.". Unique. From Linear IP Linear address of the target of the last
branch instruction (If IA-32e mode is active). From Linear IP Linear address
of the target of the last branch instruction. Reserved.
@@ -1099,7 +1099,7 @@ typedef union {
/**
0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug
features are used. Bit definitions are discussed in the referenced section.
- See Section 17.10.1, "MSR_DEBUGCTLA MSR.".
+ See Section 17.11.1, "MSR_DEBUGCTLA MSR.".
@param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)
@param EAX Lower 32-bits of MSR value.
@@ -1121,7 +1121,7 @@ typedef union {
0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an
index (0-3 or 0-15) that points to the top of the last branch record stack
(that is, that points the index of the MSR containing the most recent branch
- record). See Section 17.10.2, "LBR Stack for Processors Based on Intel
+ record). See Section 17.11.2, "LBR Stack for Processors Based on Intel
NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.
@param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)
@@ -1147,7 +1147,7 @@ typedef union {
exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through
MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models
0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See
- Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording
+ Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording
for Processors based on Skylake Microarchitecture.".
@param ECX MSR_PENTIUM_4_LASTBRANCH_n
@@ -1175,7 +1175,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_BPU_COUNTERn
@param EAX Lower 32-bits of MSR value.
@@ -1202,7 +1202,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_MS_COUNTERn
@param EAX Lower 32-bits of MSR value.
@@ -1229,7 +1229,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)
@param EAX Lower 32-bits of MSR value.
@@ -1256,7 +1256,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.2, "Performance Counters.".
@param ECX MSR_PENTIUM_4_IQ_COUNTERn
@param EAX Lower 32-bits of MSR value.
@@ -1287,7 +1287,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_BPU_CCCRn
@param EAX Lower 32-bits of MSR value.
@@ -1314,7 +1314,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_MS_CCCRn
@param EAX Lower 32-bits of MSR value.
@@ -1341,7 +1341,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_FLAME_CCCRn
@param EAX Lower 32-bits of MSR value.
@@ -1368,7 +1368,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.3, "CCCR MSRs.".
@param ECX MSR_PENTIUM_4_IQ_CCCRn
@param EAX Lower 32-bits of MSR value.
@@ -1399,7 +1399,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)
@param EAX Lower 32-bits of MSR value.
@@ -1418,7 +1418,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)
@param EAX Lower 32-bits of MSR value.
@@ -1437,7 +1437,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)
@param EAX Lower 32-bits of MSR value.
@@ -1456,7 +1456,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)
@param EAX Lower 32-bits of MSR value.
@@ -1475,7 +1475,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)
@param EAX Lower 32-bits of MSR value.
@@ -1494,7 +1494,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)
@param EAX Lower 32-bits of MSR value.
@@ -1513,7 +1513,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)
@param EAX Lower 32-bits of MSR value.
@@ -1532,7 +1532,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)
@param EAX Lower 32-bits of MSR value.
@@ -1551,7 +1551,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)
@param EAX Lower 32-bits of MSR value.
@@ -1570,7 +1570,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)
@param EAX Lower 32-bits of MSR value.
@@ -1589,7 +1589,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)
@param EAX Lower 32-bits of MSR value.
@@ -1608,7 +1608,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)
@param EAX Lower 32-bits of MSR value.
@@ -1627,7 +1627,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)
@param EAX Lower 32-bits of MSR value.
@@ -1646,7 +1646,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)
@param EAX Lower 32-bits of MSR value.
@@ -1665,7 +1665,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)
@param EAX Lower 32-bits of MSR value.
@@ -1684,7 +1684,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)
@param EAX Lower 32-bits of MSR value.
@@ -1703,7 +1703,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)
@param EAX Lower 32-bits of MSR value.
@@ -1722,7 +1722,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)
@param EAX Lower 32-bits of MSR value.
@@ -1741,7 +1741,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)
@param EAX Lower 32-bits of MSR value.
@@ -1760,7 +1760,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)
@param EAX Lower 32-bits of MSR value.
@@ -1779,7 +1779,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)
@param EAX Lower 32-bits of MSR value.
@@ -1798,7 +1798,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)
@param EAX Lower 32-bits of MSR value.
@@ -1817,7 +1817,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)
@param EAX Lower 32-bits of MSR value.
@@ -1836,7 +1836,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)
@param EAX Lower 32-bits of MSR value.
@@ -1855,7 +1855,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)
@param EAX Lower 32-bits of MSR value.
@@ -1874,7 +1874,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)
@param EAX Lower 32-bits of MSR value.
@@ -1893,7 +1893,7 @@ typedef union {
/**
- 0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available
+ 0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available
on later processors. It is only available on processor family 0FH, models
01H-02H.
@@ -1914,7 +1914,7 @@ typedef union {
/**
- 0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available
+ 0, 1, 2. Shared. See Section 18.15.1, "ESCR MSRs." This MSR is not available
on later processors. It is only available on processor family 0FH, models
01H-02H.
@@ -1935,7 +1935,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)
@param EAX Lower 32-bits of MSR value.
@@ -1954,7 +1954,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)
@param EAX Lower 32-bits of MSR value.
@@ -1973,7 +1973,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)
@param EAX Lower 32-bits of MSR value.
@@ -1992,7 +1992,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)
@param EAX Lower 32-bits of MSR value.
@@ -2011,7 +2011,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)
@param EAX Lower 32-bits of MSR value.
@@ -2030,7 +2030,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)
@param EAX Lower 32-bits of MSR value.
@@ -2049,7 +2049,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)
@param EAX Lower 32-bits of MSR value.
@@ -2068,7 +2068,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)
@param EAX Lower 32-bits of MSR value.
@@ -2087,7 +2087,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)
@param EAX Lower 32-bits of MSR value.
@@ -2106,7 +2106,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)
@param EAX Lower 32-bits of MSR value.
@@ -2125,7 +2125,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)
@param EAX Lower 32-bits of MSR value.
@@ -2144,7 +2144,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_ALF_ESCRn
@param EAX Lower 32-bits of MSR value.
@@ -2175,7 +2175,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".
+ 0, 1, 2, 3, 4, 6. Shared. See Section 18.15.1, "ESCR MSRs.".
@param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)
@param EAX Lower 32-bits of MSR value.
@@ -2194,8 +2194,8 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. Precise Event-Based Sampling (PEBS) (R/W)
- Controls the enabling of precise event sampling and replay tagging.
+ 0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W)
+ Controls the enabling of processor event sampling and replay tagging.
@param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
@@ -2223,7 +2223,7 @@ typedef union {
///
struct {
///
- /// [Bits 12:0] See Table 19-26.
+ /// [Bits 12:0] See Table 19-33.
///
UINT32 EventNum:13;
UINT32 Reserved1:11;
@@ -2234,7 +2234,7 @@ typedef union {
///
/// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical
/// processor when set; disables PEBS when clear (default). See Section
- /// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
+ /// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
/// logical processor. This bit is called ENABLE_PEBS in IA-32 processors
/// that do not support Intel HyperThreading Technology.
///
@@ -2242,7 +2242,7 @@ typedef union {
///
/// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical
/// processor when set; disables PEBS when clear (default). See Section
- /// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
+ /// 18.16.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
/// logical processor. This bit is reserved for IA-32 processors that do
/// not support Intel Hyper-Threading Technology.
///
@@ -2262,7 +2262,7 @@ typedef union {
/**
- 0, 1, 2, 3, 4, 6. Shared. See Table 19-26.
+ 0, 1, 2, 3, 4, 6. Shared. See Table 19-33.
@param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)
@param EAX Lower 32-bits of MSR value.
@@ -2288,7 +2288,7 @@ typedef union {
680H-68FH, 6C0H-6CfH are not available in processor releases before family
0FH, model 03H. These MSRs replace MSRs previously located at
1DBH-1DEH.which performed the same function for early releases. See Section
- 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording for
+ 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording for
Processors based on Skylake Microarchitecture.".
@param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
@@ -2344,7 +2344,7 @@ typedef union {
record registers on the last branch record stack (6C0H-6CFH). This part of
the stack contains pointers to the destination instruction for one of the
last 16 branches, exceptions, or interrupts that the processor took. See
- Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording
+ Section 17.10, "Last Branch, Call Stack, Interrupt, and Exception Recording
for Processors based on Skylake Microarchitecture.".
@param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
@@ -2397,7 +2397,7 @@ typedef union {
/**
3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See
- Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP
+ Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP
with Up to 8-MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)
@@ -2437,7 +2437,7 @@ typedef union {
/**
3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See
- Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP
+ Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP
with Up to 8-MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)
@@ -2477,7 +2477,7 @@ typedef union {
/**
3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See
- Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP
+ Section 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP
with Up to 8-MByte L3 Cache" for details.
@param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)
@@ -2516,7 +2516,7 @@ typedef union {
/**
- 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.17,
+ 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.21,
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache" for details.
@@ -2537,7 +2537,7 @@ typedef union {
/**
- 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.17,
+ 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.21,
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache.".
@@ -2558,7 +2558,7 @@ typedef union {
/**
- 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.17,
+ 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.21,
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache.".
@@ -2599,7 +2599,7 @@ typedef union {
/**
6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section
- 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
+ 18.21, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
8-MByte L3 Cache.".
@param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)
@@ -2638,7 +2638,7 @@ typedef union {
/**
- 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.17,
+ 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.21,
"Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte
L3 Cache" for details.
diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
index 3040631..294a381 100644
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-18.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.20.
**/
@@ -27,7 +27,7 @@
#include <Register/ArchitecturalMsr.h>
/**
- See Section 35.20, "MSRs in Pentium Processors.".
+ See Section 35.22, "MSRs in Pentium Processors.".
@param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
@param EAX Lower 32-bits of MSR value.
@@ -46,7 +46,7 @@
/**
- See Section 35.20, "MSRs in Pentium Processors.".
+ See Section 35.22, "MSRs in Pentium Processors.".
@param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
@param EAX Lower 32-bits of MSR value.
@@ -184,7 +184,7 @@ typedef union {
Last Branch Record n (R/W) One of 8 last branch record registers on the last
branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section
- 17.12, "Last Branch, Interrupt, and Exception Recording (Pentium M
+ 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M
Processors)".
@param ECX MSR_PENTIUM_M_LASTBRANCH_n
@@ -424,9 +424,9 @@ typedef union {
///
UINT32 BTS:1;
///
- /// [Bit 12] Precise Event Based Sampling Unavailable (RO) 1 = Processor
- /// does not support precise event-based sampling (PEBS); 0 = PEBS is
- /// supported. The Pentium M processor does not support PEBS.
+ /// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =
+ /// Processor does not support processor event based sampling (PEBS); 0 =
+ /// PEBS is supported. The Pentium M processor does not support PEBS.
///
UINT32 PEBS:1;
UINT32 Reserved5:3;
@@ -461,7 +461,7 @@ typedef union {
/**
Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points
to the MSR containing the most recent branch record. See also: -
- MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.12, "Last Branch, Interrupt,
+ MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,
and Exception Recording (Pentium M Processors)".
@param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
@@ -482,7 +482,7 @@ typedef union {
/**
Debug Control (R/W) Controls how several debug features are used. Bit
- definitions are discussed in the referenced section. See Section 17.12,
+ definitions are discussed in the referenced section. See Section 17.13,
"Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
@param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
@@ -505,8 +505,8 @@ typedef union {
Last Exception Record To Linear IP (R) This area contains a pointer to the
target of the last branch instruction that the processor executed prior to
the last exception that was generated or the last interrupt that was
- handled. See Section 17.12, "Last Branch, Interrupt, and Exception Recording
- (Pentium M Processors)" and Section 17.13.2, "Last Branch and Last Exception
+ handled. See Section 17.13, "Last Branch, Interrupt, and Exception Recording
+ (Pentium M Processors)" and Section 17.14.2, "Last Branch and Last Exception
MSRs.".
@param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
@@ -528,8 +528,8 @@ typedef union {
Last Exception Record From Linear IP (R) Contains a pointer to the last
branch instruction that the processor executed prior to the last exception
that was generated or the last interrupt that was handled. See Section
- 17.12, "Last Branch, Interrupt, and Exception Recording (Pentium M
- Processors)" and Section 17.13.2, "Last Branch and Last Exception MSRs.".
+ 17.13, "Last Branch, Interrupt, and Exception Recording (Pentium M
+ Processors)" and Section 17.14.2, "Last Branch and Last Exception MSRs.".
@param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
index 62c5b7e..cd846ea 100644
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-20.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.22.
**/
@@ -65,7 +65,7 @@
/**
- See Section 17.14, "Time-Stamp Counter.".
+ See Section 17.15, "Time-Stamp Counter.".
@param ECX MSR_PENTIUM_TSC (0x00000010)
@param EAX Lower 32-bits of MSR value.
@@ -84,7 +84,7 @@
/**
- See Section 18.20.1, "Control and Event Select Register (CESR).".
+ See Section 18.24.1, "Control and Event Select Register (CESR).".
@param ECX MSR_PENTIUM_CESR (0x00000011)
@param EAX Lower 32-bits of MSR value.
@@ -103,7 +103,7 @@
/**
- Section 18.20.3, "Events Counted.".
+ Section 18.24.3, "Events Counted.".
@param ECX MSR_PENTIUM_CTRn
@param EAX Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
index a50bad2..1819ecb 100644
--- a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-8.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.9.
**/
@@ -508,7 +508,7 @@ typedef union {
///
UINT32 BTS:1;
///
- /// [Bit 12] Thread. Precise Event Based Sampling Unavailable (RO) See
+ /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
/// Table 35-2.
///
UINT32 PEBS:1;
@@ -734,7 +734,7 @@ typedef union {
/**
Thread. Last Branch Record Filtering Select Register (R/W) See Section
- 17.6.2, "Filtering of Last Branch Records.".
+ 17.7.2, "Filtering of Last Branch Records.".
@param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)
@param EAX Lower 32-bits of MSR value.
@@ -895,7 +895,7 @@ typedef union {
/**
Package. Always 0 (CMCI not supported).
- @param ECX MSR_SANDY_BRIDGE_MC4_CTL2 (0x00000284)
+ @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -903,37 +903,37 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL2, Msr);
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2);
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr);
@endcode
- @note MSR_SANDY_BRIDGE_MC4_CTL2 is defined as MSR_MC4_CTL2 in SDM.
+ @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.
**/
-#define MSR_SANDY_BRIDGE_MC4_CTL2 0x00000284
+#define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284
/**
See Table 35-2. See Section 18.4.2, "Global Counter Control Facilities.".
- @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS (0x0000038E)
+ @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
@param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER.
+ Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.
@param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER.
+ Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.
<b>Example usage</b>
@code
- MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;
+ MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS);
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
@endcode
- @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
+ @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
**/
-#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS 0x0000038E
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E
/**
MSR information returned for MSR index
- #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS
+ #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS
**/
typedef union {
///
@@ -1003,7 +1003,7 @@ typedef union {
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
-} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STAUS_REGISTER;
+} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER;
/**
@@ -1190,7 +1190,7 @@ typedef union {
/**
- Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".
+ Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".
@param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
@@ -1264,7 +1264,7 @@ typedef union {
/**
- Thread. see See Section 18.7.1.2, "Load Latency Performance Monitoring
+ Thread. see See Section 18.8.1.2, "Load Latency Performance Monitoring
Facility.".
@param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)
@@ -1446,25 +1446,25 @@ typedef union {
/**
Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
- @param ECX MSR_SANDY_BRIDGE_MC4_CTL (0x00000410)
+ @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410)
@param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_MC4_CTL_REGISTER.
+ Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.
@param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SANDY_BRIDGE_MC4_CTL_REGISTER.
+ Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.
<b>Example usage</b>
@code
- MSR_SANDY_BRIDGE_MC4_CTL_REGISTER Msr;
+ MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Msr;
- Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC4_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC4_CTL, Msr.Uint64);
+ Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL);
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64);
@endcode
- @note MSR_SANDY_BRIDGE_MC4_CTL is defined as MSR_MC4_CTL in SDM.
+ @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.
**/
-#define MSR_SANDY_BRIDGE_MC4_CTL 0x00000410
+#define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410
/**
- MSR information returned for MSR index #MSR_SANDY_BRIDGE_MC4_CTL
+ MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL
**/
typedef union {
///
@@ -1497,7 +1497,7 @@ typedef union {
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
-} MSR_SANDY_BRIDGE_MC4_CTL_REGISTER;
+} MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER;
/**
@@ -1789,7 +1789,8 @@ typedef union {
Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
branch record registers on the last branch record stack. This part of the
stack contains pointers to the source instruction. See also: - Last Branch
- Record Stack TOS at 1C9H - Section 17.6.1, "LBR Stack.".
+ Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section
+ 17.4.8.1.
@param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP
@param EAX Lower 32-bits of MSR value.
@@ -1997,22 +1998,26 @@ typedef union {
///
struct {
///
- /// [Bit 0] Core 0 select.
+ /// [Bit 0] Slice 0 select.
///
- UINT32 PMI_Sel_Core0:1;
+ UINT32 PMI_Sel_Slice0:1;
///
- /// [Bit 1] Core 1 select.
+ /// [Bit 1] Slice 1 select.
///
- UINT32 PMI_Sel_Core1:1;
+ UINT32 PMI_Sel_Slice1:1;
///
- /// [Bit 2] Core 2 select.
+ /// [Bit 2] Slice 2 select.
///
- UINT32 PMI_Sel_Core2:1;
+ UINT32 PMI_Sel_Slice2:1;
///
- /// [Bit 3] Core 3 select.
+ /// [Bit 3] Slice 3 select.
///
- UINT32 PMI_Sel_Core3:1;
- UINT32 Reserved1:15;
+ UINT32 PMI_Sel_Slice3:1;
+ ///
+ /// [Bit 4] Slice 4 select.
+ ///
+ UINT32 PMI_Sel_Slice4:1;
+ UINT32 Reserved1:14;
UINT32 Reserved2:10;
///
/// [Bit 29] Enable all uncore counters.
@@ -2220,7 +2225,8 @@ typedef union {
///
struct {
///
- /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".
+ /// [Bits 3:0] Report the number of C-Box units with performance counters,
+ /// including processor cores and processor graphics".
///
UINT32 CBox:4;
UINT32 Reserved1:28;
@@ -2459,9 +2465,9 @@ typedef union {
/**
- Package. Uncore C-Box 0, counter 0 event select MSR.
+ Package. Uncore C-Box 0, counter n event select MSR.
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -2473,14 +2479,22 @@ typedef union {
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);
@endcode
@note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM.
+ @{
**/
#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703
+/// @}
/**
- Package. Uncore C-Box 0, counter 1 event select MSR.
+ Package. Uncore C-Box n, unit status for counter 0-3.
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -2488,18 +2502,28 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1, Msr);
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS);
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr);
@endcode
- @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
+ @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM.
+ @{
**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745
+/// @}
/**
- Package. Uncore C-Box 0, performance counter 0.
+ Package. Uncore C-Box 0, performance counter n.
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 (0x00000706)
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -2511,33 +2535,22 @@ typedef union {
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);
@endcode
@note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM.
+ @{
**/
#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706
-
-
-/**
- Package. Uncore C-Box 0, performance counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 (0x00000707)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1, Msr);
- @endcode
- @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
-**/
#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709
+/// @}
/**
- Package. Uncore C-Box 1, counter 0 event select MSR.
+ Package. Uncore C-Box 1, counter n event select MSR.
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -2549,33 +2562,22 @@ typedef union {
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);
@endcode
@note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM.
+ @{
**/
#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710
-
-
-/**
- Package. Uncore C-Box 1, counter 1 event select MSR.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1, Msr);
- @endcode
- @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
-**/
#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713
+/// @}
/**
- Package. Uncore C-Box 1, performance counter 0.
+ Package. Uncore C-Box 1, performance counter n.
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 (0x00000716)
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -2587,33 +2589,22 @@ typedef union {
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);
@endcode
@note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM.
+ @{
**/
#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716
-
-
-/**
- Package. Uncore C-Box 1, performance counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 (0x00000717)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1, Msr);
- @endcode
- @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
-**/
#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719
+/// @}
/**
- Package. Uncore C-Box 2, counter 0 event select MSR.
+ Package. Uncore C-Box 2, counter n event select MSR.
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -2625,33 +2616,22 @@ typedef union {
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);
@endcode
@note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM.
+ @{
**/
#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720
-
-
-/**
- Package. Uncore C-Box 2, counter 1 event select MSR.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1, Msr);
- @endcode
- @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
-**/
#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723
+/// @}
/**
- Package. Uncore C-Box 2, performance counter 0.
+ Package. Uncore C-Box 2, performance counter n.
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 (0x00000726)
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -2663,33 +2643,22 @@ typedef union {
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);
@endcode
@note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM.
+ @{
**/
#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726
-
-
-/**
- Package. Uncore C-Box 2, performance counter 1.
-
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 (0x00000727)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1, Msr);
- @endcode
- @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
-**/
#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729
+/// @}
/**
- Package. Uncore C-Box 3, counter 0 event select MSR.
+ Package. Uncore C-Box 3, counter n event select MSR.
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -2701,14 +2670,22 @@ typedef union {
AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);
@endcode
@note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM.
+ @{
**/
#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733
+/// @}
/**
- Package. Uncore C-Box 3, counter 1 event select MSR.
+ Package. Uncore C-Box 3, performance counter n.
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -2716,18 +2693,26 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1, Msr);
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);
@endcode
- @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
+ @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM.
+ @{
**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739
+/// @}
/**
- Package. Uncore C-Box 3, performance counter 0.
+ Package. Uncore C-Box 4, counter n event select MSR.
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 (0x00000736)
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -2735,18 +2720,26 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0);
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr);
@endcode
- @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
+ @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM.
+ @{
**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743
+/// @}
/**
- Package. Uncore C-Box 3, performance counter 1.
+ Package. Uncore C-Box 4, performance counter n.
- @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 (0x00000737)
+ @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -2754,12 +2747,20 @@ typedef union {
@code
UINT64 Msr;
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1, Msr);
+ Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0);
+ AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr);
@endcode
- @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
+ @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM.
+ MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM.
+ @{
**/
-#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749
+/// @}
/**
@@ -2841,7 +2842,7 @@ typedef union {
///
/// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS
/// counting logic for specific events requiring additional configuration,
- /// see Table 19-9.
+ /// see Table 19-15.
///
UINT32 ENABLE_PEBS_NUM_ALT:1;
UINT32 Reserved1:31;
@@ -2859,202 +2860,6 @@ typedef union {
/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_SANDY_BRIDGE_MCi_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_CTL);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_CTL, Msr);
- @endcode
- @note MSR_SANDY_BRIDGE_MC5_CTL is defined as MSR_MC5_CTL in SDM.
- MSR_SANDY_BRIDGE_MC6_CTL is defined as MSR_MC6_CTL in SDM.
- MSR_SANDY_BRIDGE_MC7_CTL is defined as MSR_MC7_CTL in SDM.
- MSR_SANDY_BRIDGE_MC8_CTL is defined as MSR_MC8_CTL in SDM.
- MSR_SANDY_BRIDGE_MC9_CTL is defined as MSR_MC9_CTL in SDM.
- MSR_SANDY_BRIDGE_MC10_CTL is defined as MSR_MC10_CTL in SDM.
- MSR_SANDY_BRIDGE_MC11_CTL is defined as MSR_MC11_CTL in SDM.
- MSR_SANDY_BRIDGE_MC12_CTL is defined as MSR_MC12_CTL in SDM.
- MSR_SANDY_BRIDGE_MC13_CTL is defined as MSR_MC13_CTL in SDM.
- MSR_SANDY_BRIDGE_MC14_CTL is defined as MSR_MC14_CTL in SDM.
- MSR_SANDY_BRIDGE_MC15_CTL is defined as MSR_MC15_CTL in SDM.
- MSR_SANDY_BRIDGE_MC16_CTL is defined as MSR_MC16_CTL in SDM.
- MSR_SANDY_BRIDGE_MC17_CTL is defined as MSR_MC17_CTL in SDM.
- MSR_SANDY_BRIDGE_MC18_CTL is defined as MSR_MC18_CTL in SDM.
- MSR_SANDY_BRIDGE_MC19_CTL is defined as MSR_MC19_CTL in SDM.
- @{
-**/
-#define MSR_SANDY_BRIDGE_MC5_CTL 0x00000414
-#define MSR_SANDY_BRIDGE_MC6_CTL 0x00000418
-#define MSR_SANDY_BRIDGE_MC7_CTL 0x0000041C
-#define MSR_SANDY_BRIDGE_MC8_CTL 0x00000420
-#define MSR_SANDY_BRIDGE_MC9_CTL 0x00000424
-#define MSR_SANDY_BRIDGE_MC10_CTL 0x00000428
-#define MSR_SANDY_BRIDGE_MC11_CTL 0x0000042C
-#define MSR_SANDY_BRIDGE_MC12_CTL 0x00000430
-#define MSR_SANDY_BRIDGE_MC13_CTL 0x00000434
-#define MSR_SANDY_BRIDGE_MC14_CTL 0x00000438
-#define MSR_SANDY_BRIDGE_MC15_CTL 0x0000043C
-#define MSR_SANDY_BRIDGE_MC16_CTL 0x00000440
-#define MSR_SANDY_BRIDGE_MC17_CTL 0x00000444
-#define MSR_SANDY_BRIDGE_MC18_CTL 0x00000448
-#define MSR_SANDY_BRIDGE_MC19_CTL 0x0000044C
-/// @}
-
-
-/**
- Package. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS," and Chapter 16.
-
- @param ECX MSR_SANDY_BRIDGE_MCi_STATUS
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_STATUS, Msr);
- @endcode
- @note MSR_SANDY_BRIDGE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.
- MSR_SANDY_BRIDGE_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.
- @{
-**/
-#define MSR_SANDY_BRIDGE_MC5_STATUS 0x00000415
-#define MSR_SANDY_BRIDGE_MC6_STATUS 0x00000419
-#define MSR_SANDY_BRIDGE_MC7_STATUS 0x0000041D
-#define MSR_SANDY_BRIDGE_MC8_STATUS 0x00000421
-#define MSR_SANDY_BRIDGE_MC9_STATUS 0x00000425
-#define MSR_SANDY_BRIDGE_MC10_STATUS 0x00000429
-#define MSR_SANDY_BRIDGE_MC11_STATUS 0x0000042D
-#define MSR_SANDY_BRIDGE_MC12_STATUS 0x00000431
-#define MSR_SANDY_BRIDGE_MC13_STATUS 0x00000435
-#define MSR_SANDY_BRIDGE_MC14_STATUS 0x00000439
-#define MSR_SANDY_BRIDGE_MC15_STATUS 0x0000043D
-#define MSR_SANDY_BRIDGE_MC16_STATUS 0x00000441
-#define MSR_SANDY_BRIDGE_MC17_STATUS 0x00000445
-#define MSR_SANDY_BRIDGE_MC18_STATUS 0x00000449
-#define MSR_SANDY_BRIDGE_MC19_STATUS 0x0000044D
-/// @}
-
-
-/**
- Package. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".
-
- @param ECX MSR_SANDY_BRIDGE_MCi_ADDR
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_ADDR, Msr);
- @endcode
- @note MSR_SANDY_BRIDGE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.
- MSR_SANDY_BRIDGE_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.
- @{
-**/
-#define MSR_SANDY_BRIDGE_MC5_ADDR 0x00000416
-#define MSR_SANDY_BRIDGE_MC6_ADDR 0x0000041A
-#define MSR_SANDY_BRIDGE_MC7_ADDR 0x0000041E
-#define MSR_SANDY_BRIDGE_MC8_ADDR 0x00000422
-#define MSR_SANDY_BRIDGE_MC9_ADDR 0x00000426
-#define MSR_SANDY_BRIDGE_MC10_ADDR 0x0000042A
-#define MSR_SANDY_BRIDGE_MC11_ADDR 0x0000042E
-#define MSR_SANDY_BRIDGE_MC12_ADDR 0x00000432
-#define MSR_SANDY_BRIDGE_MC13_ADDR 0x00000436
-#define MSR_SANDY_BRIDGE_MC14_ADDR 0x0000043A
-#define MSR_SANDY_BRIDGE_MC15_ADDR 0x0000043E
-#define MSR_SANDY_BRIDGE_MC16_ADDR 0x00000442
-#define MSR_SANDY_BRIDGE_MC17_ADDR 0x00000446
-#define MSR_SANDY_BRIDGE_MC18_ADDR 0x0000044A
-#define MSR_SANDY_BRIDGE_MC19_ADDR 0x0000044E
-/// @}
-
-
-/**
- Package. See Section 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_SANDY_BRIDGE_MCi_MISC
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MC5_MISC);
- AsmWriteMsr64 (MSR_SANDY_BRIDGE_MC5_MISC, Msr);
- @endcode
- @note MSR_SANDY_BRIDGE_MC5_MISC is defined as MSR_MC5_MISC in SDM.
- MSR_SANDY_BRIDGE_MC6_MISC is defined as MSR_MC6_MISC in SDM.
- MSR_SANDY_BRIDGE_MC7_MISC is defined as MSR_MC7_MISC in SDM.
- MSR_SANDY_BRIDGE_MC8_MISC is defined as MSR_MC8_MISC in SDM.
- MSR_SANDY_BRIDGE_MC9_MISC is defined as MSR_MC9_MISC in SDM.
- MSR_SANDY_BRIDGE_MC10_MISC is defined as MSR_MC10_MISC in SDM.
- MSR_SANDY_BRIDGE_MC11_MISC is defined as MSR_MC11_MISC in SDM.
- MSR_SANDY_BRIDGE_MC12_MISC is defined as MSR_MC12_MISC in SDM.
- MSR_SANDY_BRIDGE_MC13_MISC is defined as MSR_MC13_MISC in SDM.
- MSR_SANDY_BRIDGE_MC14_MISC is defined as MSR_MC14_MISC in SDM.
- MSR_SANDY_BRIDGE_MC15_MISC is defined as MSR_MC15_MISC in SDM.
- MSR_SANDY_BRIDGE_MC16_MISC is defined as MSR_MC16_MISC in SDM.
- MSR_SANDY_BRIDGE_MC17_MISC is defined as MSR_MC17_MISC in SDM.
- MSR_SANDY_BRIDGE_MC18_MISC is defined as MSR_MC18_MISC in SDM.
- MSR_SANDY_BRIDGE_MC19_MISC is defined as MSR_MC19_MISC in SDM.
- @{
-**/
-#define MSR_SANDY_BRIDGE_MC5_MISC 0x00000417
-#define MSR_SANDY_BRIDGE_MC6_MISC 0x0000041B
-#define MSR_SANDY_BRIDGE_MC7_MISC 0x0000041F
-#define MSR_SANDY_BRIDGE_MC8_MISC 0x00000423
-#define MSR_SANDY_BRIDGE_MC9_MISC 0x00000427
-#define MSR_SANDY_BRIDGE_MC10_MISC 0x0000042B
-#define MSR_SANDY_BRIDGE_MC11_MISC 0x0000042F
-#define MSR_SANDY_BRIDGE_MC12_MISC 0x00000433
-#define MSR_SANDY_BRIDGE_MC13_MISC 0x00000437
-#define MSR_SANDY_BRIDGE_MC14_MISC 0x0000043B
-#define MSR_SANDY_BRIDGE_MC15_MISC 0x0000043F
-#define MSR_SANDY_BRIDGE_MC16_MISC 0x00000443
-#define MSR_SANDY_BRIDGE_MC17_MISC 0x00000447
-#define MSR_SANDY_BRIDGE_MC18_MISC 0x0000044B
-#define MSR_SANDY_BRIDGE_MC19_MISC 0x0000044F
-/// @}
-
-
-/**
Package. Package RAPL Perf Status (R/O).
@param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)
diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
index 335ebb2..b3b6b76 100644
--- a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.4.
**/
@@ -27,7 +27,7 @@
#include <Register/ArchitecturalMsr.h>
/**
- Shared. Model Specific Platform ID (R).
+ Module. Model Specific Platform ID (R).
@param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017)
@param EAX Lower 32-bits of MSR value.
@@ -74,8 +74,7 @@ typedef union {
/**
- Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
- processor features; (R) indicates current processor configuration.
+ Module. Processor Hard Power-On Configuration (R/W) Writes ignored.
@param ECX MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)
@param EAX Lower 32-bits of MSR value.
@@ -102,69 +101,8 @@ typedef union {
/// Individual bit fields
///
struct {
- UINT32 Reserved1:1;
- ///
- /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
- /// Always 0.
- ///
- UINT32 DataErrorCheckingEnable:1;
- ///
- /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
- /// Always 0.
- ///
- UINT32 ResponseErrorCheckingEnable:1;
- ///
- /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
- ///
- UINT32 AERR_DriveEnable:1;
- ///
- /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
- /// Disabled Always 0.
- ///
- UINT32 BERR_Enable:1;
- UINT32 Reserved2:1;
- UINT32 Reserved3:1;
- ///
- /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
- ///
- UINT32 BINIT_DriverEnable:1;
- UINT32 Reserved4:1;
- ///
- /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
- ///
- UINT32 ExecuteBIST:1;
- ///
- /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
- /// Always 0.
- ///
- UINT32 AERR_ObservationEnabled:1;
- UINT32 Reserved5:1;
- ///
- /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
- /// Always 0.
- ///
- UINT32 BINIT_ObservationEnabled:1;
- UINT32 Reserved6:1;
- ///
- /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
- ///
- UINT32 ResetVector:1;
- UINT32 Reserved7:1;
- ///
- /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
- ///
- UINT32 APICClusterID:2;
- UINT32 Reserved8:2;
- ///
- /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
- ///
- UINT32 SymmetricArbitrationID:2;
- ///
- /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
- ///
- UINT32 IntegerBusFrequencyRatio:5;
- UINT32 Reserved9:5;
- UINT32 Reserved10:32;
+ UINT32 Reserved1:32;
+ UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
@@ -223,12 +161,64 @@ typedef union {
/**
+ Core. Control Features in Intel 64 Processor (R/W). See Table 35-2.
+
+ @param ECX MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type
+ MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type
+ MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL);
+ AsmWriteMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL, Msr.Uint64);
+ @endcode
+ @note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
+**/
+#define MSR_SILVERMONT_IA32_FEATURE_CONTROL 0x0000003A
+
+/**
+ MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Lock (R/WL).
+ ///
+ UINT32 Lock:1;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bit 2] Enable VMX outside SMX operation (R/WL).
+ ///
+ UINT32 EnableVmxOutsideSmx:1;
+ UINT32 Reserved2:29;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER;
+
+
+/**
Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the source instruction for one of the last eight
- branches, exceptions, or interrupts taken by the processor. See also: -
- Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,
- Interrupt, and Exception Recording (Pentium M Processors).".
+ record registers on the last branch record stack. The From_IP part of the
+ stack contains pointers to the source instruction. See also: - Last Branch
+ Record Stack TOS at 1C9H - Section 17.5 and record format in Section
+ 17.4.8.1.
@param ECX MSR_SILVERMONT_LASTBRANCH_n_FROM_IP
@param EAX Lower 32-bits of MSR value.
@@ -264,9 +254,8 @@ typedef union {
/**
Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch
- record registers on the last branch record stack. This part of the stack
- contains pointers to the destination instruction for one of the last eight
- branches, exceptions, or interrupts taken by the processor.
+ record registers on the last branch record stack. The To_IP part of the
+ stack contains pointers to the destination instruction.
@param ECX MSR_SILVERMONT_LASTBRANCH_n_TO_IP
@param EAX Lower 32-bits of MSR value.
@@ -301,7 +290,7 @@ typedef union {
/**
- Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
+ Module. Scalable Bus Speed(RO) This field indicates the intended scalable
bus clock speed for processors based on Silvermont microarchitecture:.
@param ECX MSR_SILVERMONT_FSB_FREQ (0x000000CD)
@@ -367,7 +356,7 @@ typedef union {
/**
- Shared. C-State Configuration Control (R/W) Note: C-state values are
+ Module. C-State Configuration Control (R/W) Note: C-state values are
processor specific C-state code names, unrelated to MWAIT extension C-state
parameters or ACPI CStates. See http://biosbits.org.
@@ -433,7 +422,7 @@ typedef union {
/**
- Shared. Power Management IO Redirection in C-state (R/W) See
+ Module. Power Management IO Redirection in C-state (R/W) See
http://biosbits.org.
@param ECX MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)
@@ -493,7 +482,7 @@ typedef union {
/**
- Shared.
+ Module.
@param ECX MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)
@param EAX Lower 32-bits of MSR value.
@@ -639,8 +628,8 @@ typedef union {
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
- /// [Bit 3] Shared. Automatic Thermal Control Circuit Enable (R/W) See
- /// Table 35-2.
+ /// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See
+ /// Table 35-2. Default value is 0.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
@@ -654,13 +643,13 @@ typedef union {
///
UINT32 BTS:1;
///
- /// [Bit 12] Core. Precise Event Based Sampling Unavailable (RO) See Table
- /// 35-2.
+ /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
+ /// Table 35-2.
///
UINT32 PEBS:1;
UINT32 Reserved4:3;
///
- /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
+ /// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See
/// Table 35-2.
///
UINT32 EIST:1;
@@ -675,7 +664,7 @@ typedef union {
///
UINT32 LimitCpuidMaxval:1;
///
- /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
+ /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 35-2.
///
UINT32 xTPR_Message_Disable:1;
UINT32 Reserved7:8;
@@ -686,7 +675,7 @@ typedef union {
UINT32 XD:1;
UINT32 Reserved9:3;
///
- /// [Bit 38] Shared. Turbo Mode Disable (R/W) When set to 1 on processors
+ /// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors
/// that support Intel Turbo Boost Technology, the turbo mode feature is
/// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
/// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
@@ -763,7 +752,62 @@ typedef union {
/**
- Shared. Offcore Response Event Select Register (R/W).
+ Miscellaneous Feature Control (R/W).
+
+ @param ECX MSR_SILVERMONT_MISC_FEATURE_CONTROL (0x000001A4)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL);
+ AsmWriteMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL, Msr.Uint64);
+ @endcode
+ @note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
+**/
+#define MSR_SILVERMONT_MISC_FEATURE_CONTROL 0x000001A4
+
+/**
+ MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
+ /// L2 hardware prefetcher, which fetches additional lines of code or data
+ /// into the L2 cache.
+ ///
+ UINT32 L2HardwarePrefetcherDisable:1;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
+ /// the L1 data cache prefetcher, which fetches the next cache line into
+ /// L1 data cache.
+ ///
+ UINT32 DCUHardwarePrefetcherDisable:1;
+ UINT32 Reserved2:29;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER;
+
+
+/**
+ Module. Offcore Response Event Select Register (R/W).
@param ECX MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)
@param EAX Lower 32-bits of MSR value.
@@ -782,7 +826,7 @@ typedef union {
/**
- Shared. Offcore Response Event Select Register (R/W).
+ Module. Offcore Response Event Select Register (R/W).
@param ECX MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)
@param EAX Lower 32-bits of MSR value.
@@ -877,9 +921,88 @@ typedef union {
/**
+ Core. Last Branch Record Filtering Select Register (R/W) See Section
+ 17.7.2, "Filtering of Last Branch Records.".
+
+ @param ECX MSR_SILVERMONT_LBR_SELECT (0x000001C8)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SILVERMONT_LBR_SELECT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_LBR_SELECT);
+ AsmWriteMsr64 (MSR_SILVERMONT_LBR_SELECT, Msr.Uint64);
+ @endcode
+ @note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
+**/
+#define MSR_SILVERMONT_LBR_SELECT 0x000001C8
+
+/**
+ MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] CPL_EQ_0.
+ ///
+ UINT32 CPL_EQ_0:1;
+ ///
+ /// [Bit 1] CPL_NEQ_0.
+ ///
+ UINT32 CPL_NEQ_0:1;
+ ///
+ /// [Bit 2] JCC.
+ ///
+ UINT32 JCC:1;
+ ///
+ /// [Bit 3] NEAR_REL_CALL.
+ ///
+ UINT32 NEAR_REL_CALL:1;
+ ///
+ /// [Bit 4] NEAR_IND_CALL.
+ ///
+ UINT32 NEAR_IND_CALL:1;
+ ///
+ /// [Bit 5] NEAR_RET.
+ ///
+ UINT32 NEAR_RET:1;
+ ///
+ /// [Bit 6] NEAR_IND_JMP.
+ ///
+ UINT32 NEAR_IND_JMP:1;
+ ///
+ /// [Bit 7] NEAR_REL_JMP.
+ ///
+ UINT32 NEAR_REL_JMP:1;
+ ///
+ /// [Bit 8] FAR_BRANCH.
+ ///
+ UINT32 FAR_BRANCH:1;
+ UINT32 Reserved1:23;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SILVERMONT_LBR_SELECT_REGISTER;
+
+
+/**
Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that
points to the MSR containing the most recent branch record. See
- MSR_LASTBRANCH_0_FROM_IP (at 40H).
+ MSR_LASTBRANCH_0_FROM_IP.
@param ECX MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)
@param EAX Lower 32-bits of MSR value.
@@ -939,27 +1062,7 @@ typedef union {
/**
- Core. See Table 35-2. See Section 18.4.2, "Global Counter Control
- Facilities.".
-
- @param ECX MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS, Msr);
- @endcode
- @note MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
-**/
-#define MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS 0x0000038E
-
-
-/**
- Core. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling
+ Core. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
(PEBS).".
@param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)
@@ -988,7 +1091,7 @@ typedef union {
///
struct {
///
- /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
+ /// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).
///
UINT32 PEBS:1;
UINT32 Reserved1:31;
@@ -1050,84 +1153,6 @@ typedef union {
/**
- Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_SILVERMONT_MCi_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_CTL);
- AsmWriteMsr64 (MSR_SILVERMONT_MC3_CTL, Msr);
- @endcode
- @note MSR_SILVERMONT_MC3_CTL is defined as MSR_MC3_CTL in SDM.
- MSR_SILVERMONT_MC4_CTL is defined as MSR_MC4_CTL in SDM.
- MSR_SILVERMONT_MC5_CTL is defined as MSR_MC5_CTL in SDM.
- @{
-**/
-#define MSR_SILVERMONT_MC3_CTL 0x0000040C
-#define MSR_SILVERMONT_MC4_CTL 0x00000410
-#define MSR_SILVERMONT_MC5_CTL 0x00000414
-/// @}
-
-
-/**
- Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_SILVERMONT_MCi_STATUS
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_STATUS);
- AsmWriteMsr64 (MSR_SILVERMONT_MC3_STATUS, Msr);
- @endcode
- @note MSR_SILVERMONT_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
- MSR_SILVERMONT_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
- MSR_SILVERMONT_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
- @{
-**/
-#define MSR_SILVERMONT_MC3_STATUS 0x0000040D
-#define MSR_SILVERMONT_MC4_STATUS 0x00000411
-#define MSR_SILVERMONT_MC5_STATUS 0x00000415
-/// @}
-
-
-/**
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MCi_ADDR register
- is either not implemented or contains no address if the ADDRV flag in the
- MSR_MCi_STATUS register is clear. When not implemented in the processor, all
- reads and writes to this MSR will cause a general-protection exception.
-
- @param ECX MSR_SILVERMONT_MCi_ADDR
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_ADDR);
- AsmWriteMsr64 (MSR_SILVERMONT_MC3_ADDR, Msr);
- @endcode
- @note MSR_SILVERMONT_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
- MSR_SILVERMONT_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
- MSR_SILVERMONT_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
- @{
-**/
-#define MSR_SILVERMONT_MC3_ADDR 0x0000040E
-#define MSR_SILVERMONT_MC4_ADDR 0x00000412
-#define MSR_SILVERMONT_MC5_ADDR 0x00000416
-/// @}
-
-
-/**
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
@param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
@@ -1279,7 +1304,7 @@ typedef union {
struct {
///
/// [Bits 14:0] Package Power Limit #1. (R/W) See Section 14.9.3, "Package
- /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-7.
+ /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-8.
///
UINT32 Limit:15;
///
@@ -1313,7 +1338,7 @@ typedef union {
/**
Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."
- and MSR_RAPL_POWER_UNIT in Table 35-7.
+ and MSR_RAPL_POWER_UNIT in Table 35-8.
@param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)
@param EAX Lower 32-bits of MSR value.
@@ -1332,7 +1357,7 @@ typedef union {
/**
Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
- Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.
+ Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.
@param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)
@param EAX Lower 32-bits of MSR value.
@@ -1489,7 +1514,7 @@ typedef union {
struct {
///
/// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
- /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.
+ /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.
///
UINT32 Limit:15;
///
diff --git a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
index 504c76b..ea22e22 100644
--- a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.7.
**/
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
index 0a88eb0..5e7e13a 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.14.
**/
@@ -55,11 +55,11 @@ typedef union {
///
struct {
///
- /// [Bit 0] LockOut (R/WO) See Table 35-21.
+ /// [Bit 0] LockOut (R/WO) See Table 35-24.
///
UINT32 LockOut:1;
///
- /// [Bit 1] Enable_PPIN (R/W) See Table 35-21.
+ /// [Bit 1] Enable_PPIN (R/W) See Table 35-24.
///
UINT32 Enable_PPIN:1;
UINT32 Reserved1:30;
@@ -78,7 +78,7 @@ typedef union {
/**
Package. Protected Processor Inventory Number (R/O). Protected Processor
- Inventory Number (R/O) See Table 35-21.
+ Inventory Number (R/O) See Table 35-24.
@param ECX MSR_XEON_D_PPIN (0x0000004F)
@param EAX Lower 32-bits of MSR value.
@@ -125,33 +125,33 @@ typedef union {
struct {
UINT32 Reserved1:8;
///
- /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-21.
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-24.
///
UINT32 MaximumNonTurboRatio:8;
UINT32 Reserved2:7;
///
- /// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-21.
+ /// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-24.
///
UINT32 PPIN_CAP:1;
UINT32 Reserved3:4;
///
/// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
- /// Table 35-21.
+ /// Table 35-24.
///
UINT32 RatioLimit:1;
///
/// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
- /// Table 35-21.
+ /// Table 35-24.
///
UINT32 TDPLimit:1;
///
- /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-21.
+ /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-24.
///
UINT32 TJOFFSET:1;
UINT32 Reserved4:1;
UINT32 Reserved5:8;
///
- /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-21.
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-24.
///
UINT32 MaximumEfficiencyRatio:8;
UINT32 Reserved6:16;
@@ -417,11 +417,11 @@ typedef union {
struct {
UINT32 Reserved1:16;
///
- /// [Bits 23:16] Temperature Target (RO) See Table 35-21.
+ /// [Bits 23:16] Temperature Target (RO) See Table 35-24.
///
UINT32 TemperatureTarget:8;
///
- /// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-21.
+ /// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-24.
///
UINT32 TCCActivationOffset:4;
UINT32 Reserved2:4;
@@ -654,22 +654,49 @@ typedef union {
/**
- Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
+ Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.
@param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)
@param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.
@param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.
<b>Example usage</b>
@code
- UINT64 Msr;
+ MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr;
- Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);
@endcode
@note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
**/
#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619
+/**
+ MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
+ /// to enable DRAM RAPL mode 0 (Direct VR).
+ ///
+ UINT32 Energy:32;
+ UINT32 Reserved:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER;
+
/**
Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
@@ -710,6 +737,24 @@ typedef union {
/**
+ Package. Reserved (R/O) Reads return 0.
+
+ @param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS);
+ @endcode
+ @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639
+
+
+/**
Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
refers to processor core frequency).
@@ -891,7 +936,7 @@ typedef union {
/**
THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,
- ECX=0):EBX.PQM[bit 12] = 1.
+ ECX=0):EBX.RDT-M[bit 12] = 1.
@param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)
@param EAX Lower 32-bits of MSR value.
@@ -1110,385 +1155,6 @@ typedef union {
/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- * Bank MC5 reports MC error from the Intel QPI 0 module.
- * Bank MC6 reports MC error from the integrated I/O module.
- * Bank MC7 reports MC error from the home agent HA 0.
- * Bank MC8 reports MC error from the home agent HA 1.
- * Banks MC9 through MC16 report MC error from each channel of the integrated
- memory controllers.
- * Bank MC17 reports MC error from the following pair of CBo/L3 Slices
- (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.
- * Bank MC18 reports MC error from the following pair of CBo/L3 Slices
- (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.
- * Bank MC19 reports MC error from the following pair of CBo/L3 Slices
- (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.
- * Bank MC20 reports MC error from the Intel QPI 1 module.
- * Bank MC21 reports MC error from the Intel QPI 2 module.
-
- @param ECX MSR_XEON_D_MCi_CTL
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_D_MC5_CTL);
- AsmWriteMsr64 (MSR_XEON_D_MC5_CTL, Msr);
- @endcode
- @note MSR_XEON_D_MC5_CTL is defined as MSR_MC5_CTL in SDM.
- MSR_XEON_D_MC6_CTL is defined as MSR_MC6_CTL in SDM.
- MSR_XEON_D_MC7_CTL is defined as MSR_MC7_CTL in SDM.
- MSR_XEON_D_MC8_CTL is defined as MSR_MC8_CTL in SDM.
- MSR_XEON_D_MC9_CTL is defined as MSR_MC9_CTL in SDM.
- MSR_XEON_D_MC10_CTL is defined as MSR_MC10_CTL in SDM.
- MSR_XEON_D_MC11_CTL is defined as MSR_MC11_CTL in SDM.
- MSR_XEON_D_MC12_CTL is defined as MSR_MC12_CTL in SDM.
- MSR_XEON_D_MC13_CTL is defined as MSR_MC13_CTL in SDM.
- MSR_XEON_D_MC14_CTL is defined as MSR_MC14_CTL in SDM.
- MSR_XEON_D_MC15_CTL is defined as MSR_MC15_CTL in SDM.
- MSR_XEON_D_MC16_CTL is defined as MSR_MC16_CTL in SDM.
- MSR_XEON_D_MC17_CTL is defined as MSR_MC17_CTL in SDM.
- MSR_XEON_D_MC18_CTL is defined as MSR_MC18_CTL in SDM.
- MSR_XEON_D_MC19_CTL is defined as MSR_MC19_CTL in SDM.
- MSR_XEON_D_MC20_CTL is defined as MSR_MC20_CTL in SDM.
- MSR_XEON_D_MC21_CTL is defined as MSR_MC21_CTL in SDM.
- @{
-**/
-#define MSR_XEON_D_MC5_CTL 0x00000414
-#define MSR_XEON_D_MC6_CTL 0x00000418
-#define MSR_XEON_D_MC7_CTL 0x0000041C
-#define MSR_XEON_D_MC8_CTL 0x00000420
-#define MSR_XEON_D_MC9_CTL 0x00000424
-#define MSR_XEON_D_MC10_CTL 0x00000428
-#define MSR_XEON_D_MC11_CTL 0x0000042C
-#define MSR_XEON_D_MC12_CTL 0x00000430
-#define MSR_XEON_D_MC13_CTL 0x00000434
-#define MSR_XEON_D_MC14_CTL 0x00000438
-#define MSR_XEON_D_MC15_CTL 0x0000043C
-#define MSR_XEON_D_MC16_CTL 0x00000440
-#define MSR_XEON_D_MC17_CTL 0x00000444
-#define MSR_XEON_D_MC18_CTL 0x00000448
-#define MSR_XEON_D_MC19_CTL 0x0000044C
-#define MSR_XEON_D_MC20_CTL 0x00000450
-#define MSR_XEON_D_MC21_CTL 0x00000454
-/// @}
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_XEON_D_MCi_STATUS
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_D_MC6_STATUS);
- AsmWriteMsr64 (MSR_XEON_D_MC6_STATUS, Msr);
- @endcode
- @note MSR_XEON_D_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
- MSR_XEON_D_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.
- MSR_XEON_D_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.
- MSR_XEON_D_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.
- MSR_XEON_D_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.
- MSR_XEON_D_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.
- MSR_XEON_D_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.
- MSR_XEON_D_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.
- MSR_XEON_D_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.
- MSR_XEON_D_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.
- MSR_XEON_D_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.
- MSR_XEON_D_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.
- MSR_XEON_D_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.
- MSR_XEON_D_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.
- MSR_XEON_D_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.
- MSR_XEON_D_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.
- MSR_XEON_D_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.
- @{
-**/
-#define MSR_XEON_D_MC5_STATUS 0x00000415
-#define MSR_XEON_D_MC6_STATUS 0x00000419
-#define MSR_XEON_D_MC7_STATUS 0x0000041D
-#define MSR_XEON_D_MC8_STATUS 0x00000421
-#define MSR_XEON_D_MC9_STATUS 0x00000425
-#define MSR_XEON_D_MC10_STATUS 0x00000429
-#define MSR_XEON_D_MC11_STATUS 0x0000042D
-#define MSR_XEON_D_MC12_STATUS 0x00000431
-#define MSR_XEON_D_MC13_STATUS 0x00000435
-#define MSR_XEON_D_MC14_STATUS 0x00000439
-#define MSR_XEON_D_MC15_STATUS 0x0000043D
-#define MSR_XEON_D_MC16_STATUS 0x00000441
-#define MSR_XEON_D_MC17_STATUS 0x00000445
-#define MSR_XEON_D_MC18_STATUS 0x00000449
-#define MSR_XEON_D_MC19_STATUS 0x0000044D
-#define MSR_XEON_D_MC20_STATUS 0x00000451
-#define MSR_XEON_D_MC21_STATUS 0x00000455
-/// @}
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_XEON_D_MCi_ADDR
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_D_MC6_ADDR);
- AsmWriteMsr64 (MSR_XEON_D_MC6_ADDR, Msr);
- @endcode
- @note MSR_XEON_D_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
- MSR_XEON_D_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.
- MSR_XEON_D_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.
- MSR_XEON_D_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.
- MSR_XEON_D_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.
- MSR_XEON_D_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.
- MSR_XEON_D_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.
- MSR_XEON_D_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.
- MSR_XEON_D_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.
- MSR_XEON_D_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.
- MSR_XEON_D_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.
- MSR_XEON_D_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.
- MSR_XEON_D_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.
- MSR_XEON_D_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.
- MSR_XEON_D_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.
- MSR_XEON_D_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.
- MSR_XEON_D_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.
- @{
-**/
-#define MSR_XEON_D_MC5_ADDR 0x00000416
-#define MSR_XEON_D_MC6_ADDR 0x0000041A
-#define MSR_XEON_D_MC7_ADDR 0x0000041E
-#define MSR_XEON_D_MC8_ADDR 0x00000422
-#define MSR_XEON_D_MC9_ADDR 0x00000426
-#define MSR_XEON_D_MC10_ADDR 0x0000042A
-#define MSR_XEON_D_MC11_ADDR 0x0000042E
-#define MSR_XEON_D_MC12_ADDR 0x00000432
-#define MSR_XEON_D_MC13_ADDR 0x00000436
-#define MSR_XEON_D_MC14_ADDR 0x0000043A
-#define MSR_XEON_D_MC15_ADDR 0x0000043E
-#define MSR_XEON_D_MC16_ADDR 0x00000442
-#define MSR_XEON_D_MC17_ADDR 0x00000446
-#define MSR_XEON_D_MC18_ADDR 0x0000044A
-#define MSR_XEON_D_MC19_ADDR 0x0000044E
-#define MSR_XEON_D_MC20_ADDR 0x00000452
-#define MSR_XEON_D_MC21_ADDR 0x00000456
-/// @}
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
- 15.3.2.4, "IA32_MCi_MISC MSRs.".
-
- @param ECX MSR_XEON_D_MCi_MISC
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_D_MC6_MISC);
- AsmWriteMsr64 (MSR_XEON_D_MC6_MISC, Msr);
- @endcode
- @note MSR_XEON_D_MC5_MISC is defined as MSR_MC5_MISC in SDM.
- MSR_XEON_D_MC6_MISC is defined as MSR_MC6_MISC in SDM.
- MSR_XEON_D_MC7_MISC is defined as MSR_MC7_MISC in SDM.
- MSR_XEON_D_MC8_MISC is defined as MSR_MC8_MISC in SDM.
- MSR_XEON_D_MC9_MISC is defined as MSR_MC9_MISC in SDM.
- MSR_XEON_D_MC10_MISC is defined as MSR_MC10_MISC in SDM.
- MSR_XEON_D_MC11_MISC is defined as MSR_MC11_MISC in SDM.
- MSR_XEON_D_MC12_MISC is defined as MSR_MC12_MISC in SDM.
- MSR_XEON_D_MC13_MISC is defined as MSR_MC13_MISC in SDM.
- MSR_XEON_D_MC14_MISC is defined as MSR_MC14_MISC in SDM.
- MSR_XEON_D_MC15_MISC is defined as MSR_MC15_MISC in SDM.
- MSR_XEON_D_MC16_MISC is defined as MSR_MC16_MISC in SDM.
- MSR_XEON_D_MC17_MISC is defined as MSR_MC17_MISC in SDM.
- MSR_XEON_D_MC18_MISC is defined as MSR_MC18_MISC in SDM.
- MSR_XEON_D_MC19_MISC is defined as MSR_MC19_MISC in SDM.
- MSR_XEON_D_MC20_MISC is defined as MSR_MC20_MISC in SDM.
- MSR_XEON_D_MC21_MISC is defined as MSR_MC21_MISC in SDM.
- @{
-**/
-#define MSR_XEON_D_MC5_MISC 0x00000417
-#define MSR_XEON_D_MC6_MISC 0x0000041B
-#define MSR_XEON_D_MC7_MISC 0x0000041F
-#define MSR_XEON_D_MC8_MISC 0x00000423
-#define MSR_XEON_D_MC9_MISC 0x00000427
-#define MSR_XEON_D_MC10_MISC 0x0000042B
-#define MSR_XEON_D_MC11_MISC 0x0000042F
-#define MSR_XEON_D_MC12_MISC 0x00000433
-#define MSR_XEON_D_MC13_MISC 0x00000437
-#define MSR_XEON_D_MC14_MISC 0x0000043B
-#define MSR_XEON_D_MC15_MISC 0x0000043F
-#define MSR_XEON_D_MC16_MISC 0x00000443
-#define MSR_XEON_D_MC17_MISC 0x00000447
-#define MSR_XEON_D_MC18_MISC 0x0000044B
-#define MSR_XEON_D_MC19_MISC 0x0000044F
-#define MSR_XEON_D_MC20_MISC 0x00000453
-#define MSR_XEON_D_MC21_MISC 0x00000457
-/// @}
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI C-States.
-
- @param ECX MSR_XEON_D_PKG_C8_RESIDENCY (0x00000630)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY);
- AsmWriteMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY, Msr.Uint64);
- @endcode
- @note MSR_XEON_D_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.
-**/
-#define MSR_XEON_D_PKG_C8_RESIDENCY 0x00000630
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_PKG_C8_RESIDENCY
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset
- /// that this package is in processor-specific C8 states. Count at the
- /// same frequency as the TSC.
- ///
- UINT32 C8ResidencyCounter:32;
- ///
- /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last
- /// reset that this package is in processor-specific C8 states. Count at
- /// the same frequency as the TSC.
- ///
- UINT32 C8ResidencyCounterHi:28;
- UINT32 Reserved:4;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER;
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI C-States.
-
- @param ECX MSR_XEON_D_PKG_C9_RESIDENCY (0x00000631)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY);
- AsmWriteMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY, Msr.Uint64);
- @endcode
- @note MSR_XEON_D_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.
-**/
-#define MSR_XEON_D_PKG_C9_RESIDENCY 0x00000631
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_PKG_C9_RESIDENCY
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset
- /// that this package is in processor-specific C9 states. Count at the
- /// same frequency as the TSC.
- ///
- UINT32 C9ResidencyCounter:32;
- ///
- /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last
- /// reset that this package is in processor-specific C9 states. Count at
- /// the same frequency as the TSC.
- ///
- UINT32 C9ResidencyCounterHi:28;
- UINT32 Reserved:4;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER;
-
-
-/**
- Package. Note: C-state values are processor specific C-state code names,
- unrelated to MWAIT extension C-state parameters or ACPI C-States.
-
- @param ECX MSR_XEON_D_PKG_C10_RESIDENCY (0x00000632)
- @param EAX Lower 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.
- @param EDX Upper 32-bits of MSR value.
- Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.
-
- <b>Example usage</b>
- @code
- MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER Msr;
-
- Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY);
- AsmWriteMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY, Msr.Uint64);
- @endcode
- @note MSR_XEON_D_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
-**/
-#define MSR_XEON_D_PKG_C10_RESIDENCY 0x00000632
-
-/**
- MSR information returned for MSR index #MSR_XEON_D_PKG_C10_RESIDENCY
-**/
-typedef union {
- ///
- /// Individual bit fields
- ///
- struct {
- ///
- /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last
- /// reset that this package is in processor-specific C10 states. Count at
- /// the same frequency as the TSC.
- ///
- UINT32 C10ResidencyCounter:32;
- ///
- /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last
- /// reset that this package is in processor-specific C10 states. Count at
- /// the same frequency as the TSC.
- ///
- UINT32 C10ResidencyCounterHi:28;
- UINT32 Reserved:4;
- } Bits;
- ///
- /// All bit fields as a 64-bit value
- ///
- UINT64 Uint64;
-} MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER;
-
-
-/**
Package. Cache Allocation Technology Configuration (R/W).
@param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
index 3128c4b..d14ef21 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8.
**/
@@ -27,6 +27,78 @@
#include <Register/ArchitecturalMsr.h>
/**
+ Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
+ handler to handle unsuccessful read of this MSR.
+
+ @param ECX MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_XEON_E7_FEATURE_CONFIG_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);
+ AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);
+ @endcode
+ @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
+**/
+#define MSR_XEON_E7_FEATURE_CONFIG 0x0000013C
+
+/**
+ MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
+ /// MSR, the configuration of AES instruction set availability is as
+ /// follows: 11b: AES instructions are not available until next RESET.
+ /// otherwise, AES instructions are available. Note, AES instruction set
+ /// is not available if read is unsuccessful. If the configuration is not
+ /// 01b, AES instruction can be mis-configured if a privileged agent
+ /// unintentionally writes 11b.
+ ///
+ UINT32 AESConfiguration:2;
+ UINT32 Reserved1:30;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;
+
+
+/**
+ Thread. Offcore Response Event Select Register (R/W).
+
+ @param ECX MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);
+ AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);
+ @endcode
+ @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
+**/
+#define MSR_XEON_E7_OFFCORE_RSP_1 0x000001A7
+
+
+/**
Package. Reserved Attempt to read/write will cause #UD.
@param ECX MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index 75f2dce..853d83b 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.17.
**/
@@ -302,6 +302,58 @@ typedef union {
/**
+ THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
+ Enhancement. Accessible only while in SMM.
+
+ @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);
+ AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);
+ @endcode
+ @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
+**/
+#define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D
+
+/**
+ MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:32;
+ UINT32 Reserved2:26;
+ ///
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
+ /// SMM code access restriction is supported and a host-space interface
+ /// available to SMM handler.
+ ///
+ UINT32 SMM_Code_Access_Chk:1;
+ ///
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
+ /// SMM long flow indicator is supported and a host-space interface
+ /// available to SMM handler.
+ ///
+ UINT32 Long_Flow_Indication:1;
+ UINT32 Reserved3:4;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;
+
+
+/**
Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor
functions to be enabled and disabled.
@@ -336,7 +388,8 @@ typedef union {
UINT32 FastStrings:1;
UINT32 Reserved1:2;
///
- /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W).
+ /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value
+ /// is 1.
///
UINT32 AutomaticThermalControlCircuit:1;
UINT32 Reserved2:3;
@@ -350,7 +403,7 @@ typedef union {
///
UINT32 BTS:1;
///
- /// [Bit 12] Precise Event Based Sampling Unavailable (RO).
+ /// [Bit 12] Processor Event Based Sampling Unavailable (RO).
///
UINT32 PEBS:1;
UINT32 Reserved4:3;
@@ -444,6 +497,58 @@ typedef union {
/**
+ Miscellaneous Feature Control (R/W).
+
+ @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);
+ AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);
+ @endcode
+ @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
+**/
+#define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4
+
+/**
+ MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the
+ /// L1 data cache prefetcher.
+ ///
+ UINT32 DCUHardwarePrefetcherDisable:1;
+ ///
+ /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
+ /// L2 hardware prefetcher.
+ ///
+ UINT32 L2HardwarePrefetcherDisable:1;
+ UINT32 Reserved1:30;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;
+
+
+/**
Shared. Offcore Response Event Select Register (R/W).
@param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)
@@ -685,25 +790,6 @@ typedef union {
/**
Thread. See Table 35-2.
- @param ECX MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS (0x0000038E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS, Msr);
- @endcode
- @note MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
-**/
-#define MSR_XEON_PHI_IA32_PERF_GLOBAL_STAUS 0x0000038E
-
-
-/**
- Thread. See Table 35-2.
-
@param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
@@ -841,180 +927,6 @@ typedef union {
/**
- Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_XEON_PHI_MC3_CTL (0x0000040C)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_CTL);
- AsmWriteMsr64 (MSR_XEON_PHI_MC3_CTL, Msr);
- @endcode
- @note MSR_XEON_PHI_MC3_CTL is defined as MSR_MC3_CTL in SDM.
-**/
-#define MSR_XEON_PHI_MC3_CTL 0x0000040C
-
-
-/**
- Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_XEON_PHI_MC3_STATUS (0x0000040D)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_STATUS);
- AsmWriteMsr64 (MSR_XEON_PHI_MC3_STATUS, Msr);
- @endcode
- @note MSR_XEON_PHI_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
-**/
-#define MSR_XEON_PHI_MC3_STATUS 0x0000040D
-
-
-/**
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".
-
- @param ECX MSR_XEON_PHI_MC3_ADDR (0x0000040E)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC3_ADDR);
- AsmWriteMsr64 (MSR_XEON_PHI_MC3_ADDR, Msr);
- @endcode
- @note MSR_XEON_PHI_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
-**/
-#define MSR_XEON_PHI_MC3_ADDR 0x0000040E
-
-
-/**
- Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_XEON_PHI_MC4_CTL (0x00000410)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_CTL);
- AsmWriteMsr64 (MSR_XEON_PHI_MC4_CTL, Msr);
- @endcode
- @note MSR_XEON_PHI_MC4_CTL is defined as MSR_MC4_CTL in SDM.
-**/
-#define MSR_XEON_PHI_MC4_CTL 0x00000410
-
-
-/**
- Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_XEON_PHI_MC4_STATUS (0x00000411)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_STATUS);
- AsmWriteMsr64 (MSR_XEON_PHI_MC4_STATUS, Msr);
- @endcode
- @note MSR_XEON_PHI_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
-**/
-#define MSR_XEON_PHI_MC4_STATUS 0x00000411
-
-
-/**
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register
- is either not implemented or contains no address if the ADDRV flag in the
- MSR_MC4_STATUS register is clear. When not implemented in the processor, all
- reads and writes to this MSR will cause a general-protection exception.
-
- @param ECX MSR_XEON_PHI_MC4_ADDR (0x00000412)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC4_ADDR);
- AsmWriteMsr64 (MSR_XEON_PHI_MC4_ADDR, Msr);
- @endcode
- @note MSR_XEON_PHI_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
-**/
-#define MSR_XEON_PHI_MC4_ADDR 0x00000412
-
-
-/**
- Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
-
- @param ECX MSR_XEON_PHI_MC5_CTL (0x00000414)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_CTL);
- AsmWriteMsr64 (MSR_XEON_PHI_MC5_CTL, Msr);
- @endcode
- @note MSR_XEON_PHI_MC5_CTL is defined as MSR_MC5_CTL in SDM.
-**/
-#define MSR_XEON_PHI_MC5_CTL 0x00000414
-
-
-/**
- Package. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
-
- @param ECX MSR_XEON_PHI_MC5_STATUS (0x00000415)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_STATUS);
- AsmWriteMsr64 (MSR_XEON_PHI_MC5_STATUS, Msr);
- @endcode
- @note MSR_XEON_PHI_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
-**/
-#define MSR_XEON_PHI_MC5_STATUS 0x00000415
-
-
-/**
- Package. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs.".
-
- @param ECX MSR_XEON_PHI_MC5_ADDR (0x00000416)
- @param EAX Lower 32-bits of MSR value.
- @param EDX Upper 32-bits of MSR value.
-
- <b>Example usage</b>
- @code
- UINT64 Msr;
-
- Msr = AsmReadMsr64 (MSR_XEON_PHI_MC5_ADDR);
- AsmWriteMsr64 (MSR_XEON_PHI_MC5_ADDR, Msr);
- @endcode
- @note MSR_XEON_PHI_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
-**/
-#define MSR_XEON_PHI_MC5_ADDR 0x00000416
-
-
-/**
Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.
@param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
@@ -1323,7 +1235,7 @@ typedef union {
/**
- Package. Base TDP Ratio (R/O) See Table 35-20.
+ Package. Base TDP Ratio (R/O) See Table 35-23.
@param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
@param EAX Lower 32-bits of MSR value.
@@ -1341,7 +1253,7 @@ typedef union {
/**
- Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-20.
+ Package. ConfigTDP Level 1 ratio and power level (R/O). See Table 35-23.
@param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
@param EAX Lower 32-bits of MSR value.
@@ -1359,7 +1271,7 @@ typedef union {
/**
- Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-20.
+ Package. ConfigTDP Level 2 ratio and power level (R/O). See Table 35-23.
@param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
@param EAX Lower 32-bits of MSR value.
@@ -1377,7 +1289,7 @@ typedef union {
/**
- Package. ConfigTDP Control (R/W) See Table 35-20.
+ Package. ConfigTDP Control (R/W) See Table 35-23.
@param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
@param EAX Lower 32-bits of MSR value.
@@ -1396,7 +1308,7 @@ typedef union {
/**
- Package. ConfigTDP Control (R/W) See Table 35-20.
+ Package. ConfigTDP Control (R/W) See Table 35-23.
@param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
@param EAX Lower 32-bits of MSR value.
--
1.9.5.msysgit.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/4] UefiCpuPkg/Include: Update Skylake MSR header file with SDM (Sep.2016)
2016-12-14 8:33 [PATCH 0/4] Update CPUID & MSR header files with SDM (Sep.2016) Hao Wu
2016-12-14 8:33 ` [PATCH 1/4] UefiCpuPkg/Include: Update " Hao Wu
@ 2016-12-14 8:33 ` Hao Wu
2016-12-14 8:33 ` [PATCH 3/4] UefiCpuPkg/Include: Add Goldmont " Hao Wu
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Hao Wu @ 2016-12-14 8:33 UTC (permalink / raw)
To: edk2-devel; +Cc: Hao Wu, Michael Kinney, Jeff Fan
https://bugzilla.tianocore.org/show_bug.cgi?id=176
Update the MSR header file of Skylake processor according to Intel(R) 64
and IA-32 Architectures Software Developer's Manual, Volume 3, September
2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15.
Summary of incompatible changes:
1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS has been renamed to
IA32_PERF_GLOBAL_STATUS
Typo 'STAUS' has been fixed in SDM.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
---
UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1189 +++++++++++++++++++++++++-
1 file changed, 1169 insertions(+), 20 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 604b98f..23ca3e1 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-14.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15.
**/
@@ -146,28 +146,28 @@ typedef union {
/**
- See Table 35-2. See Section 18.2.2.3, "Full-Width Writes to Performance
- Counter Registers.".
+ See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring
+ Version 4.".
- @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS (0x0000038E)
+ @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
@param EAX Lower 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER.
+ Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.
@param EDX Upper 32-bits of MSR value.
- Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER.
+ Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.
<b>Example usage</b>
@code
- MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;
+ MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
- Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS);
- AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS);
+ AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
@endcode
- @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.
+ @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
**/
-#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS 0x0000038E
+#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E
/**
- MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS
**/
typedef union {
///
@@ -254,12 +254,12 @@ typedef union {
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
-} MSR_SKYLAKE_IA32_PERF_GLOBAL_STAUS_REGISTER;
+} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER;
/**
- See Table 35-2. See Section 18.2.2.3, "Full-Width Writes to Performance
- Counter Registers.".
+ See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring
+ Version 4.".
@param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
@param EAX Lower 32-bits of MSR value.
@@ -371,8 +371,8 @@ typedef union {
/**
- See Table 35-2. See Section 18.2.2.3, "Full-Width Writes to Performance
- Counter Registers.".
+ See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring
+ Version 4.".
@param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
@param EAX Lower 32-bits of MSR value.
@@ -541,6 +541,25 @@ typedef union {
/**
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
+ Domains.".
+
+ @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);
+ @endcode
+ @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639
+
+
+/**
Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both
platform vendor hardware implementation and BIOS enablement support it. This
MSR will read 0 if not valid.
@@ -611,6 +630,187 @@ typedef union {
/**
+ Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
+ refers to processor core frequency).
+
+ @param ECX MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS);
+ AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
+ @endcode
+ @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
+ /// operating system request due to assertion of external PROCHOT.
+ ///
+ UINT32 PROCHOT_Status:1;
+ ///
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+ /// operating system request due to a thermal event.
+ ///
+ UINT32 ThermalStatus:1;
+ UINT32 Reserved1:2;
+ ///
+ /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is
+ /// reduced below the operating system request due to residency state
+ /// regulation limit.
+ ///
+ UINT32 ResidencyStateRegulationStatus:1;
+ ///
+ /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
+ /// is reduced below the operating system request due to Running Average
+ /// Thermal Limit (RATL).
+ ///
+ UINT32 RunningAverageThermalLimitStatus:1;
+ ///
+ /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
+ /// below the operating system request due to a thermal alert from a
+ /// processor Voltage Regulator (VR).
+ ///
+ UINT32 VRThermAlertStatus:1;
+ ///
+ /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is
+ /// reduced below the operating system request due to VR thermal design
+ /// current limit.
+ ///
+ UINT32 VRThermDesignCurrentStatus:1;
+ ///
+ /// [Bit 8] Other Status (R0) When set, frequency is reduced below the
+ /// operating system request due to electrical or other constraints.
+ ///
+ UINT32 OtherStatus:1;
+ UINT32 Reserved2:1;
+ ///
+ /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
+ /// set, frequency is reduced below the operating system request due to
+ /// package/platform-level power limiting PL1.
+ ///
+ UINT32 PL1Status:1;
+ ///
+ /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
+ /// set, frequency is reduced below the operating system request due to
+ /// package/platform-level power limiting PL2/PL3.
+ ///
+ UINT32 PL2Status:1;
+ ///
+ /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced
+ /// below the operating system request due to multi-core turbo limits.
+ ///
+ UINT32 MaxTurboLimitStatus:1;
+ ///
+ /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
+ /// is reduced below the operating system request due to Turbo transition
+ /// attenuation. This prevents performance degradation due to frequent
+ /// operating ratio changes.
+ ///
+ UINT32 TurboTransitionAttenuationStatus:1;
+ UINT32 Reserved3:2;
+ ///
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
+ /// has asserted since the log bit was last cleared. This log bit will
+ /// remain set until cleared by software writing 0.
+ ///
+ UINT32 PROCHOT_Log:1;
+ ///
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
+ /// has asserted since the log bit was last cleared. This log bit will
+ /// remain set until cleared by software writing 0.
+ ///
+ UINT32 ThermalLog:1;
+ UINT32 Reserved4:2;
+ ///
+ /// [Bit 20] Residency State Regulation Log When set, indicates that the
+ /// Residency State Regulation Status bit has asserted since the log bit
+ /// was last cleared. This log bit will remain set until cleared by
+ /// software writing 0.
+ ///
+ UINT32 ResidencyStateRegulationLog:1;
+ ///
+ /// [Bit 21] Running Average Thermal Limit Log When set, indicates that
+ /// the RATL Status bit has asserted since the log bit was last cleared.
+ /// This log bit will remain set until cleared by software writing 0.
+ ///
+ UINT32 RunningAverageThermalLimitLog:1;
+ ///
+ /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
+ /// Alert Status bit has asserted since the log bit was last cleared. This
+ /// log bit will remain set until cleared by software writing 0.
+ ///
+ UINT32 VRThermAlertLog:1;
+ ///
+ /// [Bit 23] VR Thermal Design Current Log When set, indicates that the
+ /// VR TDC Status bit has asserted since the log bit was last cleared.
+ /// This log bit will remain set until cleared by software writing 0.
+ ///
+ UINT32 VRThermalDesignCurrentLog:1;
+ ///
+ /// [Bit 24] Other Log When set, indicates that the Other Status bit has
+ /// asserted since the log bit was last cleared. This log bit will remain
+ /// set until cleared by software writing 0.
+ ///
+ UINT32 OtherLog:1;
+ UINT32 Reserved5:1;
+ ///
+ /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,
+ /// indicates that the Package or Platform Level PL1 Power Limiting Status
+ /// bit has asserted since the log bit was last cleared. This log bit will
+ /// remain set until cleared by software writing 0.
+ ///
+ UINT32 PL1Log:1;
+ ///
+ /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
+ /// indicates that the Package or Platform Level PL2/PL3 Power Limiting
+ /// Status bit has asserted since the log bit was last cleared. This log
+ /// bit will remain set until cleared by software writing 0.
+ ///
+ UINT32 PL2Log:1;
+ ///
+ /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
+ /// Limit Status bit has asserted since the log bit was last cleared. This
+ /// log bit will remain set until cleared by software writing 0.
+ ///
+ UINT32 MaxTurboLimitLog:1;
+ ///
+ /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
+ /// Turbo Transition Attenuation Status bit has asserted since the log bit
+ /// was last cleared. This log bit will remain set until cleared by
+ /// software writing 0.
+ ///
+ UINT32 TurboTransitionAttenuationLog:1;
+ UINT32 Reserved6:2;
+ UINT32 Reserved7:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
Package. HDC Configuration (R/W)..
@param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)
@@ -899,7 +1099,7 @@ typedef union {
Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last
branch record registers on the last branch record stack. This part of the
stack contains pointers to the source instruction. See also: - Last Branch
- Record Stack TOS at 1C9H - Section 17.9.
+ Record Stack TOS at 1C9H - Section 17.10.
@param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP
@param EAX Lower 32-bits of MSR value.
@@ -948,11 +1148,307 @@ typedef union {
#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F
/// @}
+
+/**
+ Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)
+ (frequency refers to processor graphics frequency).
+
+ @param ECX MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS);
+ AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);
+ @endcode
+ @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0
+
+/**
+ MSR information returned for MSR index
+ #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to
+ /// assertion of external PROCHOT.
+ ///
+ UINT32 PROCHOT_Status:1;
+ ///
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a
+ /// thermal event.
+ ///
+ UINT32 ThermalStatus:1;
+ UINT32 Reserved1:3;
+ ///
+ /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
+ /// is reduced due to running average thermal limit.
+ ///
+ UINT32 RunningAverageThermalLimitStatus:1;
+ ///
+ /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due
+ /// to a thermal alert from a processor Voltage Regulator.
+ ///
+ UINT32 VRThermAlertStatus:1;
+ ///
+ /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is
+ /// reduced due to VR TDC limit.
+ ///
+ UINT32 VRThermalDesignCurrentStatus:1;
+ ///
+ /// [Bit 8] Other Status (R0) When set, frequency is reduced due to
+ /// electrical or other constraints.
+ ///
+ UINT32 OtherStatus:1;
+ UINT32 Reserved2:1;
+ ///
+ /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
+ /// set, frequency is reduced due to package/platform-level power limiting
+ /// PL1.
+ ///
+ UINT32 PL1Status:1;
+ ///
+ /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
+ /// set, frequency is reduced due to package/platform-level power limiting
+ /// PL2/PL3.
+ ///
+ UINT32 PL2Status:1;
+ ///
+ /// [Bit 12] Inefficient Operation Status (R0) When set, processor
+ /// graphics frequency is operating below target frequency.
+ ///
+ UINT32 InefficientOperationStatus:1;
+ UINT32 Reserved3:3;
+ ///
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
+ /// has asserted since the log bit was last cleared. This log bit will
+ /// remain set until cleared by software writing 0.
+ ///
+ UINT32 PROCHOT_Log:1;
+ ///
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
+ /// has asserted since the log bit was last cleared. This log bit will
+ /// remain set until cleared by software writing 0.
+ ///
+ UINT32 ThermalLog:1;
+ UINT32 Reserved4:3;
+ ///
+ /// [Bit 21] Running Average Thermal Limit Log When set, indicates that
+ /// the RATL Status bit has asserted since the log bit was last cleared.
+ /// This log bit will remain set until cleared by software writing 0.
+ ///
+ UINT32 RunningAverageThermalLimitLog:1;
+ ///
+ /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
+ /// Alert Status bit has asserted since the log bit was last cleared. This
+ /// log bit will remain set until cleared by software writing 0.
+ ///
+ UINT32 VRThermAlertLog:1;
+ ///
+ /// [Bit 23] VR Thermal Design Current Log When set, indicates that the
+ /// VR Therm Alert Status bit has asserted since the log bit was last
+ /// cleared. This log bit will remain set until cleared by software
+ /// writing 0.
+ ///
+ UINT32 VRThermalDesignCurrentLog:1;
+ ///
+ /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has
+ /// asserted since the log bit was last cleared. This log bit will remain
+ /// set until cleared by software writing 0.
+ ///
+ UINT32 OtherLog:1;
+ UINT32 Reserved5:1;
+ ///
+ /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,
+ /// indicates that the Package/Platform Level PL1 Power Limiting Status
+ /// bit has asserted since the log bit was last cleared. This log bit will
+ /// remain set until cleared by software writing 0.
+ ///
+ UINT32 PL1Log:1;
+ ///
+ /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
+ /// indicates that the Package/Platform Level PL2 Power Limiting Status
+ /// bit has asserted since the log bit was last cleared. This log bit will
+ /// remain set until cleared by software writing 0.
+ ///
+ UINT32 PL2Log:1;
+ ///
+ /// [Bit 28] Inefficient Operation Log When set, indicates that the
+ /// Inefficient Operation Status bit has asserted since the log bit was
+ /// last cleared. This log bit will remain set until cleared by software
+ /// writing 0.
+ ///
+ UINT32 InefficientOperationLog:1;
+ UINT32 Reserved6:3;
+ UINT32 Reserved7:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+ Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)
+ (frequency refers to ring interconnect in the uncore).
+
+ @param ECX MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS);
+ AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64);
+ @endcode
+ @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to
+ /// assertion of external PROCHOT.
+ ///
+ UINT32 PROCHOT_Status:1;
+ ///
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a
+ /// thermal event.
+ ///
+ UINT32 ThermalStatus:1;
+ UINT32 Reserved1:3;
+ ///
+ /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
+ /// is reduced due to running average thermal limit.
+ ///
+ UINT32 RunningAverageThermalLimitStatus:1;
+ ///
+ /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due
+ /// to a thermal alert from a processor Voltage Regulator.
+ ///
+ UINT32 VRThermAlertStatus:1;
+ ///
+ /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is
+ /// reduced due to VR TDC limit.
+ ///
+ UINT32 VRThermalDesignCurrentStatus:1;
+ ///
+ /// [Bit 8] Other Status (R0) When set, frequency is reduced due to
+ /// electrical or other constraints.
+ ///
+ UINT32 OtherStatus:1;
+ UINT32 Reserved2:1;
+ ///
+ /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
+ /// set, frequency is reduced due to package/Platform-level power limiting
+ /// PL1.
+ ///
+ UINT32 PL1Status:1;
+ ///
+ /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
+ /// set, frequency is reduced due to package/Platform-level power limiting
+ /// PL2/PL3.
+ ///
+ UINT32 PL2Status:1;
+ UINT32 Reserved3:4;
+ ///
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
+ /// has asserted since the log bit was last cleared. This log bit will
+ /// remain set until cleared by software writing 0.
+ ///
+ UINT32 PROCHOT_Log:1;
+ ///
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
+ /// has asserted since the log bit was last cleared. This log bit will
+ /// remain set until cleared by software writing 0.
+ ///
+ UINT32 ThermalLog:1;
+ UINT32 Reserved4:3;
+ ///
+ /// [Bit 21] Running Average Thermal Limit Log When set, indicates that
+ /// the RATL Status bit has asserted since the log bit was last cleared.
+ /// This log bit will remain set until cleared by software writing 0.
+ ///
+ UINT32 RunningAverageThermalLimitLog:1;
+ ///
+ /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
+ /// Alert Status bit has asserted since the log bit was last cleared. This
+ /// log bit will remain set until cleared by software writing 0.
+ ///
+ UINT32 VRThermAlertLog:1;
+ ///
+ /// [Bit 23] VR Thermal Design Current Log When set, indicates that the
+ /// VR Therm Alert Status bit has asserted since the log bit was last
+ /// cleared. This log bit will remain set until cleared by software
+ /// writing 0.
+ ///
+ UINT32 VRThermalDesignCurrentLog:1;
+ ///
+ /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has
+ /// asserted since the log bit was last cleared. This log bit will remain
+ /// set until cleared by software writing 0.
+ ///
+ UINT32 OtherLog:1;
+ UINT32 Reserved5:1;
+ ///
+ /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,
+ /// indicates that the Package/Platform Level PL1 Power Limiting Status
+ /// bit has asserted since the log bit was last cleared. This log bit will
+ /// remain set until cleared by software writing 0.
+ ///
+ UINT32 PL1Log:1;
+ ///
+ /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
+ /// indicates that the Package/Platform Level PL2 Power Limiting Status
+ /// bit has asserted since the log bit was last cleared. This log bit will
+ /// remain set until cleared by software writing 0.
+ ///
+ UINT32 PL2Log:1;
+ UINT32 Reserved6:4;
+ UINT32 Reserved7:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER;
+
+
/**
Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch
record registers on the last branch record stack. This part of the stack
contains pointers to the destination instruction. See also: - Last Branch
- Record Stack TOS at 1C9H - Section 17.9.
+ Record Stack TOS at 1C9H - Section 17.10.
@param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP
@param EAX Lower 32-bits of MSR value.
@@ -1006,7 +1502,7 @@ typedef union {
Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet
of last branch record registers on the last branch record stack. This part
of the stack contains flag, TSX-related and elapsed cycle information. See
- also: - Last Branch Record Stack TOS at 1C9H - Section 17.6.1, "LBR
+ also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR
Stack.".
@param ECX MSR_SKYLAKE_LBR_INFO_n
@@ -1088,4 +1584,657 @@ typedef union {
#define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF
/// @}
+
+/**
+ Package. Uncore fixed counter control (R/W).
+
+ @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
+ @endcode
+ @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
+**/
+#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:20;
+ ///
+ /// [Bit 20] Enable overflow propagation.
+ ///
+ UINT32 EnableOverflow:1;
+ UINT32 Reserved2:1;
+ ///
+ /// [Bit 22] Enable counting.
+ ///
+ UINT32 EnableCounting:1;
+ UINT32 Reserved3:9;
+ UINT32 Reserved4:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER;
+
+
+/**
+ Package. Uncore fixed counter.
+
+ @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64);
+ @endcode
+ @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
+**/
+#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 31:0] Current count.
+ ///
+ UINT32 CurrentCount:32;
+ ///
+ /// [Bits 43:32] Current count.
+ ///
+ UINT32 CurrentCountHi:12;
+ UINT32 Reserved:20;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER;
+
+
+/**
+ Package. Uncore C-Box configuration information (R/O).
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 3:0] Specifies the number of C-Box units with programmable
+ /// counters (including processor cores and processor graphics),.
+ ///
+ UINT32 CBox:4;
+ UINT32 Reserved1:28;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER;
+
+
+/**
+ Package. Uncore Arb unit, performance counter 0.
+
+ @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0
+
+
+/**
+ Package. Uncore Arb unit, performance counter 1.
+
+ @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1
+
+
+/**
+ Package. Uncore Arb unit, counter 0 event select MSR.
+
+ @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2
+
+
+/**
+ Package. Uncore Arb unit, counter 1 event select MSR.
+
+ @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3
+
+
+/**
+ Package. Uncore C-Box 0, counter 0 event select MSR.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700
+
+
+/**
+ Package. Uncore C-Box 0, counter 1 event select MSR.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701
+
+
+/**
+ Package. Uncore C-Box 0, performance counter 0.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706
+
+
+/**
+ Package. Uncore C-Box 0, performance counter 1.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707
+
+
+/**
+ Package. Uncore C-Box 1, counter 0 event select MSR.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710
+
+
+/**
+ Package. Uncore C-Box 1, counter 1 event select MSR.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711
+
+
+/**
+ Package. Uncore C-Box 1, performance counter 0.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716
+
+
+/**
+ Package. Uncore C-Box 1, performance counter 1.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717
+
+
+/**
+ Package. Uncore C-Box 2, counter 0 event select MSR.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720
+
+
+/**
+ Package. Uncore C-Box 2, counter 1 event select MSR.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721
+
+
+/**
+ Package. Uncore C-Box 2, performance counter 0.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726
+
+
+/**
+ Package. Uncore C-Box 2, performance counter 1.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727
+
+
+/**
+ Package. Uncore C-Box 3, counter 0 event select MSR.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730
+
+
+/**
+ Package. Uncore C-Box 3, counter 1 event select MSR.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731
+
+
+/**
+ Package. Uncore C-Box 3, performance counter 0.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736
+
+
+/**
+ Package. Uncore C-Box 3, performance counter 1.
+
+ @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr);
+ @endcode
+ @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737
+
+
+/**
+ Package. Uncore PMU global control.
+
+ @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
+ @endcode
+ @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
+**/
+#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Slice 0 select.
+ ///
+ UINT32 PMI_Sel_Slice0:1;
+ ///
+ /// [Bit 1] Slice 1 select.
+ ///
+ UINT32 PMI_Sel_Slice1:1;
+ ///
+ /// [Bit 2] Slice 2 select.
+ ///
+ UINT32 PMI_Sel_Slice2:1;
+ ///
+ /// [Bit 3] Slice 3 select.
+ ///
+ UINT32 PMI_Sel_Slice3:1;
+ ///
+ /// [Bit 4] Slice 4select.
+ ///
+ UINT32 PMI_Sel_Slice4:1;
+ UINT32 Reserved1:14;
+ UINT32 Reserved2:10;
+ ///
+ /// [Bit 29] Enable all uncore counters.
+ ///
+ UINT32 EN:1;
+ ///
+ /// [Bit 30] Enable wake on PMI.
+ ///
+ UINT32 WakePMI:1;
+ ///
+ /// [Bit 31] Enable Freezing counter when overflow.
+ ///
+ UINT32 FREEZE:1;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER;
+
+
+/**
+ Package. Uncore PMU main status.
+
+ @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS);
+ AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
+ @endcode
+ @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02
+
+/**
+ MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Fixed counter overflowed.
+ ///
+ UINT32 Fixed:1;
+ ///
+ /// [Bit 1] An ARB counter overflowed.
+ ///
+ UINT32 ARB:1;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bit 3] A CBox counter overflowed (on any slice).
+ ///
+ UINT32 CBox:1;
+ UINT32 Reserved2:28;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;
+
#endif
--
1.9.5.msysgit.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/4] UefiCpuPkg/Include: Add Goldmont MSR header file with SDM (Sep.2016)
2016-12-14 8:33 [PATCH 0/4] Update CPUID & MSR header files with SDM (Sep.2016) Hao Wu
2016-12-14 8:33 ` [PATCH 1/4] UefiCpuPkg/Include: Update " Hao Wu
2016-12-14 8:33 ` [PATCH 2/4] UefiCpuPkg/Include: Update Skylake MSR header file " Hao Wu
@ 2016-12-14 8:33 ` Hao Wu
2016-12-14 8:33 ` [PATCH 4/4] UefiCpuPkg/Cpuid.h: Update CPUID definitions " Hao Wu
2016-12-15 18:16 ` [PATCH 0/4] Update CPUID & MSR header files " Kinney, Michael D
4 siblings, 0 replies; 6+ messages in thread
From: Hao Wu @ 2016-12-14 8:33 UTC (permalink / raw)
To: edk2-devel; +Cc: Hao Wu, Michael Kinney, Jeff Fan
https://bugzilla.tianocore.org/show_bug.cgi?id=176
Add the MSR header file of Goldmont processor according to Intel(R) 64 and
IA-32 Architectures Software Developer's Manual, Volume 3, September 2016,
Chapter 35 Model-Specific-Registers (MSR), Section 35.5.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
---
UefiCpuPkg/Include/Register/Msr.h | 3 +-
UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 2515 +++++++++++++++++++++++++
2 files changed, 2517 insertions(+), 1 deletion(-)
create mode 100644 UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
diff --git a/UefiCpuPkg/Include/Register/Msr.h b/UefiCpuPkg/Include/Register/Msr.h
index ffa6d44..0ac8d5b 100644
--- a/UefiCpuPkg/Include/Register/Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Chapter 35.
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Chapter 35.
**/
@@ -28,6 +28,7 @@
#include <Register/Msr/Core2Msr.h>
#include <Register/Msr/AtomMsr.h>
#include <Register/Msr/SilvermontMsr.h>
+#include <Register/Msr/GoldmontMsr.h>
#include <Register/Msr/NehalemMsr.h>
#include <Register/Msr/Xeon5600Msr.h>
#include <Register/Msr/XeonE7Msr.h>
diff --git a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
new file mode 100644
index 0000000..58b9c57
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
@@ -0,0 +1,2515 @@
+/** @file
+ MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture.
+
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+ are provided for MSRs that contain one or more bit fields. If the MSR value
+ returned is a single 32-bit or 64-bit value, then a data structure is not
+ provided for that MSR.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ @par Specification Reference:
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.5.
+
+**/
+
+#ifndef __GOLDMONT_MSR_H__
+#define __GOLDMONT_MSR_H__
+
+#include <Register/ArchitecturalMsr.h>
+
+/**
+ Core. Control Features in Intel 64Processor (R/W).
+
+ @param ECX MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_FEATURE_CONTROL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_FEATURE_CONTROL);
+ AsmWriteMsr64 (MSR_GOLDMONT_FEATURE_CONTROL, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
+**/
+#define MSR_GOLDMONT_FEATURE_CONTROL 0x0000003A
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Lock bit (R/WL)
+ ///
+ UINT32 Lock:1;
+ ///
+ /// [Bit 1] Enable VMX inside SMX operation (R/WL)
+ ///
+ UINT32 EnableVmxInsideSmx:1;
+ ///
+ /// [Bit 2] Enable VMX outside SMX operation (R/WL)
+ ///
+ UINT32 EnableVmxOutsideSmx:1;
+ UINT32 Reserved1:5;
+ ///
+ /// [Bits 14:8] SENTER local function enables (R/WL)
+ ///
+ UINT32 SenterLocalFunctionEnables:7;
+ ///
+ /// [Bit 15] SENTER global functions enable (R/WL)
+ ///
+ UINT32 SenterGlobalEnable:1;
+ UINT32 Reserved2:2;
+ ///
+ /// [Bit 18] SGX global functions enable (R/WL)
+ ///
+ UINT32 SgxEnable:1;
+ UINT32 Reserved3:13;
+ UINT32 Reserved4:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_FEATURE_CONTROL_REGISTER;
+
+
+/**
+ Package. See http://biosbits.org.
+
+ @param ECX MSR_GOLDMONT_PLATFORM_INFO (0x000000CE)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_PLATFORM_INFO_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLATFORM_INFO);
+ AsmWriteMsr64 (MSR_GOLDMONT_PLATFORM_INFO, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
+**/
+#define MSR_GOLDMONT_PLATFORM_INFO 0x000000CE
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:8;
+ ///
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
+ /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+ /// MHz.
+ ///
+ UINT32 MaximumNonTurboRatio:8;
+ UINT32 Reserved2:12;
+ ///
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
+ /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+ /// enabled, and when set to 0, indicates Programmable Ratio Limits for
+ /// Turbo mode is disabled.
+ ///
+ UINT32 RatioLimit:1;
+ ///
+ /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
+ /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+ /// and when set to 0, indicates TDP Limit for Turbo mode is not
+ /// programmable.
+ ///
+ UINT32 TDPLimit:1;
+ ///
+ /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,
+ /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
+ /// specify an temperature offset.
+ ///
+ UINT32 TJOFFSET:1;
+ UINT32 Reserved3:1;
+ UINT32 Reserved4:8;
+ ///
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
+ /// minimum ratio (maximum efficiency) that the processor can operates, in
+ /// units of 100MHz.
+ ///
+ UINT32 MaximumEfficiencyRatio:8;
+ UINT32 Reserved5:16;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_PLATFORM_INFO_REGISTER;
+
+
+/**
+ Core. C-State Configuration Control (R/W) Note: C-state values are
+ processor specific C-state code names, unrelated to MWAIT extension C-state
+ parameters or ACPI CStates. See http://biosbits.org.
+
+ @param ECX MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type
+ MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type
+ MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL);
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 0x000000E2
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
+ /// processor-specific C-state code name (consuming the least power). for
+ /// the package. The default is set as factory-configured package C-state
+ /// limit. The following C-state code name encodings are supported: 0000b:
+ /// No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8
+ /// 0111b: C9 1000b: C10.
+ ///
+ UINT32 Limit:4;
+ UINT32 Reserved1:6;
+ ///
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
+ /// IO_read instructions sent to IO register specified by
+ /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
+ ///
+ UINT32 IO_MWAIT:1;
+ UINT32 Reserved2:4;
+ ///
+ /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
+ /// until next reset.
+ ///
+ UINT32 CFGLock:1;
+ UINT32 Reserved3:16;
+ UINT32 Reserved4:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+ Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement.
+ Accessible only while in SMM.
+
+ @param ECX MSR_GOLDMONT_SMM_MCA_CAP (0x0000017D)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_SMM_MCA_CAP_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_MCA_CAP);
+ AsmWriteMsr64 (MSR_GOLDMONT_SMM_MCA_CAP, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
+**/
+#define MSR_GOLDMONT_SMM_MCA_CAP 0x0000017D
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:32;
+ UINT32 Reserved2:26;
+ ///
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
+ /// SMM code access restriction is supported and the
+ /// MSR_SMM_FEATURE_CONTROL is supported.
+ ///
+ UINT32 SMM_Code_Access_Chk:1;
+ ///
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
+ /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is
+ /// supported.
+ ///
+ UINT32 Long_Flow_Indication:1;
+ UINT32 Reserved3:4;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_SMM_MCA_CAP_REGISTER;
+
+
+/**
+ Enable Misc. Processor Features (R/W) Allows a variety of processor
+ functions to be enabled and disabled.
+
+ @param ECX MSR_GOLDMONT_IA32_MISC_ENABLE (0x000001A0)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE);
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_GOLDMONT_IA32_MISC_ENABLE 0x000001A0
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Core. Fast-Strings Enable See Table 35-2.
+ ///
+ UINT32 FastStrings:1;
+ UINT32 Reserved1:2;
+ ///
+ /// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See
+ /// Table 35-2. Default value is 1.
+ ///
+ UINT32 AutomaticThermalControlCircuit:1;
+ UINT32 Reserved2:3;
+ ///
+ /// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.
+ ///
+ UINT32 PerformanceMonitoring:1;
+ UINT32 Reserved3:3;
+ ///
+ /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.
+ ///
+ UINT32 BTS:1;
+ ///
+ /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
+ /// Table 35-2.
+ ///
+ UINT32 PEBS:1;
+ UINT32 Reserved4:3;
+ ///
+ /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
+ /// Table 35-2.
+ ///
+ UINT32 EIST:1;
+ UINT32 Reserved5:1;
+ ///
+ /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.
+ ///
+ UINT32 MONITOR:1;
+ UINT32 Reserved6:3;
+ ///
+ /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.
+ ///
+ UINT32 LimitCpuidMaxval:1;
+ ///
+ /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 35-2.
+ ///
+ UINT32 xTPR_Message_Disable:1;
+ UINT32 Reserved7:8;
+ UINT32 Reserved8:2;
+ ///
+ /// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.
+ ///
+ UINT32 XD:1;
+ UINT32 Reserved9:3;
+ ///
+ /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
+ /// that support Intel Turbo Boost Technology, the turbo mode feature is
+ /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
+ /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
+ /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
+ /// the power-on default value is used by BIOS to detect hardware support
+ /// of turbo mode. If power-on default value is 1, turbo mode is available
+ /// in the processor. If power-on default value is 0, turbo mode is not
+ /// available.
+ ///
+ UINT32 TurboModeDisable:1;
+ UINT32 Reserved10:25;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+ Miscellaneous Feature Control (R/W).
+
+ @param ECX MSR_GOLDMONT_MISC_FEATURE_CONTROL (0x000001A4)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL);
+ AsmWriteMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
+**/
+#define MSR_GOLDMONT_MISC_FEATURE_CONTROL 0x000001A4
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
+ /// L2 hardware prefetcher, which fetches additional lines of code or data
+ /// into the L2 cache.
+ ///
+ UINT32 L2HardwarePrefetcherDisable:1;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
+ /// the L1 data cache prefetcher, which fetches the next cache line into
+ /// L1 data cache.
+ ///
+ UINT32 DCUHardwarePrefetcherDisable:1;
+ UINT32 Reserved2:29;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER;
+
+
+/**
+ Package. See http://biosbits.org.
+
+ @param ECX MSR_GOLDMONT_MISC_PWR_MGMT (0x000001AA)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT);
+ AsmWriteMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
+**/
+#define MSR_GOLDMONT_MISC_PWR_MGMT 0x000001AA
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] EIST Hardware Coordination Disable (R/W) When 0, enables
+ /// hardware coordination of Enhanced Intel Speedstep Technology request
+ /// from processor cores; When 1, disables hardware coordination of
+ /// Enhanced Intel Speedstep Technology requests.
+ ///
+ UINT32 EISTHardwareCoordinationDisable:1;
+ UINT32 Reserved1:21;
+ ///
+ /// [Bit 22] Thermal Interrupt Coordination Enable (R/W) If set, then
+ /// thermal interrupt on one core is routed to all cores.
+ ///
+ UINT32 ThermalInterruptCoordinationEnable:1;
+ UINT32 Reserved2:9;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER;
+
+
+/**
+ Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies
+ Maximum Ratio Limit for each Core Group. Max ratio for groups with more
+ cores must decrease monotonically. For groups with less than 4 cores, the
+ max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must
+ be 22 or less. For groups with more than 5 cores, the max ratio must be 16
+ or less..
+
+ @param ECX MSR_GOLDMONT_TURBO_RATIO_LIMIT (0x000001AD)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT);
+ AsmWriteMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_GOLDMONT_TURBO_RATIO_LIMIT 0x000001AD
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] Package. Maximum Ratio Limit for Active cores in Group 0
+ /// Maximum turbo ratio limit when number of active cores is less or equal
+ /// to Group 0 threshold.
+ ///
+ UINT32 MaxRatioLimitGroup0:8;
+ ///
+ /// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1
+ /// Maximum turbo ratio limit when number of active cores is less or equal
+ /// to Group 1 threshold and greater than Group 0 threshold.
+ ///
+ UINT32 MaxRatioLimitGroup1:8;
+ ///
+ /// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2
+ /// Maximum turbo ratio limit when number of active cores is less or equal
+ /// to Group 2 threshold and greater than Group 1 threshold.
+ ///
+ UINT32 MaxRatioLimitGroup2:8;
+ ///
+ /// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3
+ /// Maximum turbo ratio limit when number of active cores is less or equal
+ /// to Group 3 threshold and greater than Group 2 threshold.
+ ///
+ UINT32 MaxRatioLimitGroup3:8;
+ ///
+ /// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4
+ /// Maximum turbo ratio limit when number of active cores is less or equal
+ /// to Group 4 threshold and greater than Group 3 threshold.
+ ///
+ UINT32 MaxRatioLimitGroup4:8;
+ ///
+ /// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5
+ /// Maximum turbo ratio limit when number of active cores is less or equal
+ /// to Group 5 threshold and greater than Group 4 threshold.
+ ///
+ UINT32 MaxRatioLimitGroup5:8;
+ ///
+ /// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6
+ /// Maximum turbo ratio limit when number of active cores is less or equal
+ /// to Group 6 threshold and greater than Group 5 threshold.
+ ///
+ UINT32 MaxRatioLimitGroup6:8;
+ ///
+ /// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7
+ /// Maximum turbo ratio limit when number of active cores is less or equal
+ /// to Group 7 threshold and greater than Group 6 threshold.
+ ///
+ UINT32 MaxRatioLimitGroup7:8;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+ Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of
+ 0 threshold is ignored.
+
+ @param ECX MSR_GOLDMONT_TURBO_GROUP_CORECNT (0x000001AE)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT);
+ AsmWriteMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM.
+**/
+#define MSR_GOLDMONT_TURBO_GROUP_CORECNT 0x000001AE
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of
+ /// active cores to operate under Group 0 Max Turbo Ratio limit.
+ ///
+ UINT32 CoreCountThresholdGroup0:8;
+ ///
+ /// [Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of
+ /// active cores to operate under Group 1 Max Turbo Ratio limit. Must be
+ /// greater than Group 0 Core Count.
+ ///
+ UINT32 CoreCountThresholdGroup1:8;
+ ///
+ /// [Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of
+ /// active cores to operate under Group 2 Max Turbo Ratio limit. Must be
+ /// greater than Group 1 Core Count.
+ ///
+ UINT32 CoreCountThresholdGroup2:8;
+ ///
+ /// [Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of
+ /// active cores to operate under Group 3 Max Turbo Ratio limit. Must be
+ /// greater than Group 2 Core Count.
+ ///
+ UINT32 CoreCountThresholdGroup3:8;
+ ///
+ /// [Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of
+ /// active cores to operate under Group 4 Max Turbo Ratio limit. Must be
+ /// greater than Group 3 Core Count.
+ ///
+ UINT32 CoreCountThresholdGroup4:8;
+ ///
+ /// [Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of
+ /// active cores to operate under Group 5 Max Turbo Ratio limit. Must be
+ /// greater than Group 4 Core Count.
+ ///
+ UINT32 CoreCountThresholdGroup5:8;
+ ///
+ /// [Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of
+ /// active cores to operate under Group 6 Max Turbo Ratio limit. Must be
+ /// greater than Group 5 Core Count.
+ ///
+ UINT32 CoreCountThresholdGroup6:8;
+ ///
+ /// [Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of
+ /// active cores to operate under Group 7 Max Turbo Ratio limit. Must be
+ /// greater than Group 6 Core Count and not less than the total number of
+ /// processor cores in the package. E.g. specify 255.
+ ///
+ UINT32 CoreCountThresholdGroup7:8;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER;
+
+
+/**
+ Core. Last Branch Record Filtering Select Register (R/W) See Section
+ 17.7.2, "Filtering of Last Branch Records.".
+
+ @param ECX MSR_GOLDMONT_LBR_SELECT (0x000001C8)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_LBR_SELECT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LBR_SELECT);
+ AsmWriteMsr64 (MSR_GOLDMONT_LBR_SELECT, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
+**/
+#define MSR_GOLDMONT_LBR_SELECT 0x000001C8
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] CPL_EQ_0.
+ ///
+ UINT32 CPL_EQ_0:1;
+ ///
+ /// [Bit 1] CPL_NEQ_0.
+ ///
+ UINT32 CPL_NEQ_0:1;
+ ///
+ /// [Bit 2] JCC.
+ ///
+ UINT32 JCC:1;
+ ///
+ /// [Bit 3] NEAR_REL_CALL.
+ ///
+ UINT32 NEAR_REL_CALL:1;
+ ///
+ /// [Bit 4] NEAR_IND_CALL.
+ ///
+ UINT32 NEAR_IND_CALL:1;
+ ///
+ /// [Bit 5] NEAR_RET.
+ ///
+ UINT32 NEAR_RET:1;
+ ///
+ /// [Bit 6] NEAR_IND_JMP.
+ ///
+ UINT32 NEAR_IND_JMP:1;
+ ///
+ /// [Bit 7] NEAR_REL_JMP.
+ ///
+ UINT32 NEAR_REL_JMP:1;
+ ///
+ /// [Bit 8] FAR_BRANCH.
+ ///
+ UINT32 FAR_BRANCH:1;
+ ///
+ /// [Bit 9] EN_CALL_STACK.
+ ///
+ UINT32 EN_CALL_STACK:1;
+ UINT32 Reserved1:22;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_LBR_SELECT_REGISTER;
+
+
+/**
+ Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that
+ points to the MSR containing the most recent branch record. See
+ MSR_LASTBRANCH_0_FROM_IP.
+
+ @param ECX MSR_GOLDMONT_LASTBRANCH_TOS (0x000001C9)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS);
+ AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS, Msr);
+ @endcode
+ @note MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_GOLDMONT_LASTBRANCH_TOS 0x000001C9
+
+
+/**
+ Core. Power Control Register. See http://biosbits.org.
+
+ @param ECX MSR_GOLDMONT_POWER_CTL (0x000001FC)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_POWER_CTL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_POWER_CTL);
+ AsmWriteMsr64 (MSR_GOLDMONT_POWER_CTL, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM.
+**/
+#define MSR_GOLDMONT_POWER_CTL 0x000001FC
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:1;
+ ///
+ /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the
+ /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology
+ /// operating point when all execution cores enter MWAIT (C1).
+ ///
+ UINT32 C1EEnable:1;
+ UINT32 Reserved2:30;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_POWER_CTL_REGISTER;
+
+
+/**
+ Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
+ an 128-bit external entropy value for key derivation of an enclave.
+
+ @param ECX MSR_GOLDMONT_SGXOWNER0 (0x00000300)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNER0);
+ @endcode
+ @note MSR_GOLDMONT_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.
+**/
+#define MSR_GOLDMONT_SGXOWNER0 0x00000300
+
+
+/**
+ Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
+ an 128-bit external entropy value for key derivation of an enclave.
+
+ @param ECX MSR_GOLDMONT_SGXOWNER1 (0x00000301)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNER1);
+ @endcode
+ @note MSR_GOLDMONT_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.
+**/
+#define MSR_GOLDMONT_SGXOWNER1 0x00000301
+
+
+/**
+ Core. See Table 35-2. See Section 18.2.4, "Architectural Performance
+ Monitoring Version 4.".
+
+ @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET);
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
+**/
+#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
+
+/**
+ MSR information returned for MSR index
+ #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Set 1 to clear Ovf_PMC0.
+ ///
+ UINT32 Ovf_PMC0:1;
+ ///
+ /// [Bit 1] Set 1 to clear Ovf_PMC1.
+ ///
+ UINT32 Ovf_PMC1:1;
+ ///
+ /// [Bit 2] Set 1 to clear Ovf_PMC2.
+ ///
+ UINT32 Ovf_PMC2:1;
+ ///
+ /// [Bit 3] Set 1 to clear Ovf_PMC3.
+ ///
+ UINT32 Ovf_PMC3:1;
+ UINT32 Reserved1:28;
+ ///
+ /// [Bit 32] Set 1 to clear Ovf_FixedCtr0.
+ ///
+ UINT32 Ovf_FixedCtr0:1;
+ ///
+ /// [Bit 33] Set 1 to clear Ovf_FixedCtr1.
+ ///
+ UINT32 Ovf_FixedCtr1:1;
+ ///
+ /// [Bit 34] Set 1 to clear Ovf_FixedCtr2.
+ ///
+ UINT32 Ovf_FixedCtr2:1;
+ UINT32 Reserved2:20;
+ ///
+ /// [Bit 55] Set 1 to clear Trace_ToPA_PMI.
+ ///
+ UINT32 Trace_ToPA_PMI:1;
+ UINT32 Reserved3:2;
+ ///
+ /// [Bit 58] Set 1 to clear LBR_Frz.
+ ///
+ UINT32 LBR_Frz:1;
+ ///
+ /// [Bit 59] Set 1 to clear CTR_Frz.
+ ///
+ UINT32 CTR_Frz:1;
+ ///
+ /// [Bit 60] Set 1 to clear ASCI.
+ ///
+ UINT32 ASCI:1;
+ ///
+ /// [Bit 61] Set 1 to clear Ovf_Uncore.
+ ///
+ UINT32 Ovf_Uncore:1;
+ ///
+ /// [Bit 62] Set 1 to clear Ovf_BufDSSAVE.
+ ///
+ UINT32 Ovf_BufDSSAVE:1;
+ ///
+ /// [Bit 63] Set 1 to clear CondChgd.
+ ///
+ UINT32 CondChgd:1;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
+
+
+/**
+ Core. See Table 35-2. See Section 18.2.4, "Architectural Performance
+ Monitoring Version 4.".
+
+ @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET);
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
+**/
+#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
+
+/**
+ MSR information returned for MSR index
+ #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Set 1 to cause Ovf_PMC0 = 1.
+ ///
+ UINT32 Ovf_PMC0:1;
+ ///
+ /// [Bit 1] Set 1 to cause Ovf_PMC1 = 1.
+ ///
+ UINT32 Ovf_PMC1:1;
+ ///
+ /// [Bit 2] Set 1 to cause Ovf_PMC2 = 1.
+ ///
+ UINT32 Ovf_PMC2:1;
+ ///
+ /// [Bit 3] Set 1 to cause Ovf_PMC3 = 1.
+ ///
+ UINT32 Ovf_PMC3:1;
+ UINT32 Reserved1:28;
+ ///
+ /// [Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1.
+ ///
+ UINT32 Ovf_FixedCtr0:1;
+ ///
+ /// [Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1.
+ ///
+ UINT32 Ovf_FixedCtr1:1;
+ ///
+ /// [Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1.
+ ///
+ UINT32 Ovf_FixedCtr2:1;
+ UINT32 Reserved2:20;
+ ///
+ /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1.
+ ///
+ UINT32 Trace_ToPA_PMI:1;
+ UINT32 Reserved3:2;
+ ///
+ /// [Bit 58] Set 1 to cause LBR_Frz = 1.
+ ///
+ UINT32 LBR_Frz:1;
+ ///
+ /// [Bit 59] Set 1 to cause CTR_Frz = 1.
+ ///
+ UINT32 CTR_Frz:1;
+ ///
+ /// [Bit 60] Set 1 to cause ASCI = 1.
+ ///
+ UINT32 ASCI:1;
+ ///
+ /// [Bit 61] Set 1 to cause Ovf_Uncore.
+ ///
+ UINT32 Ovf_Uncore:1;
+ ///
+ /// [Bit 62] Set 1 to cause Ovf_BufDSSAVE.
+ ///
+ UINT32 Ovf_BufDSSAVE:1;
+ UINT32 Reserved4:1;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
+
+
+/**
+ Core. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
+ (PEBS).".
+
+ @param ECX MSR_GOLDMONT_PEBS_ENABLE (0x000003F1)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_PEBS_ENABLE_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PEBS_ENABLE);
+ AsmWriteMsr64 (MSR_GOLDMONT_PEBS_ENABLE, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_GOLDMONT_PEBS_ENABLE 0x000003F1
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Enable PEBS trigger and recording for the programmed event
+ /// (precise or otherwise) on IA32_PMC0. (R/W).
+ ///
+ UINT32 Enable:1;
+ UINT32 Reserved1:31;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_PEBS_ENABLE_REGISTER;
+
+
+/**
+ Package. Note: C-state values are processor specific C-state code names,
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
+ Residency Counter. (R/O) Value since last reset that this package is in
+ processor-specific C3 states. Count at the same frequency as the TSC.
+
+ @param ECX MSR_GOLDMONT_PKG_C3_RESIDENCY (0x000003F8)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY);
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY, Msr);
+ @endcode
+ @note MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_PKG_C3_RESIDENCY 0x000003F8
+
+
+/**
+ Package. Note: C-state values are processor specific C-state code names,
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
+ Residency Counter. (R/O) Value since last reset that this package is in
+ processor-specific C6 states. Count at the same frequency as the TSC.
+
+ @param ECX MSR_GOLDMONT_PKG_C6_RESIDENCY (0x000003F9)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY);
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY, Msr);
+ @endcode
+ @note MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_PKG_C6_RESIDENCY 0x000003F9
+
+
+/**
+ Core. Note: C-state values are processor specific C-state code names,
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
+ Residency Counter. (R/O) Value since last reset that this core is in
+ processor-specific C3 states. Count at the same frequency as the TSC.
+
+ @param ECX MSR_GOLDMONT_CORE_C3_RESIDENCY (0x000003FC)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY);
+ AsmWriteMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY, Msr);
+ @endcode
+ @note MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_CORE_C3_RESIDENCY 0x000003FC
+
+
+/**
+ Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability
+ Enhancement. Accessible only while in SMM.
+
+ @param ECX MSR_GOLDMONT_SMM_FEATURE_CONTROL (0x000004E0)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL);
+ AsmWriteMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.
+**/
+#define MSR_GOLDMONT_SMM_FEATURE_CONTROL 0x000004E0
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from
+ /// further changes.
+ ///
+ UINT32 Lock:1;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if
+ /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the
+ /// logical processors are prevented from executing SMM code outside the
+ /// ranges defined by the SMRR. When set to '1' any logical processor in
+ /// the package that attempts to execute SMM code not within the ranges
+ /// defined by the SMRR will assert an unrecoverable MCE.
+ ///
+ UINT32 SMM_Code_Chk_En:1;
+ UINT32 Reserved2:29;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER;
+
+
+/**
+ Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical
+ processors in the package. Available only while in SMM and
+ MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
+
+ @param ECX MSR_GOLDMONT_SMM_DELAYED (0x000004E2)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_SMM_DELAYED_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_DELAYED);
+ AsmWriteMsr64 (MSR_GOLDMONT_SMM_DELAYED, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.
+**/
+#define MSR_GOLDMONT_SMM_DELAYED 0x000004E2
+
+
+/**
+ Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical
+ processors in the package. Available only while in SMM.
+
+ @param ECX MSR_GOLDMONT_SMM_BLOCKED (0x000004E3)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_SMM_BLOCKED_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_BLOCKED);
+ AsmWriteMsr64 (MSR_GOLDMONT_SMM_BLOCKED, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.
+**/
+#define MSR_GOLDMONT_SMM_BLOCKED 0x000004E3
+
+
+/**
+ Core. Trace Control Register (R/W).
+
+ @param ECX MSR_GOLDMONT_IA32_RTIT_CTL (0x00000570)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL);
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
+**/
+#define MSR_IA32_RTIT_CTL 0x00000570
+
+/**
+ MSR information returned for MSR index #MSR_IA32_RTIT_CTL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] TraceEn.
+ ///
+ UINT32 TraceEn:1;
+ ///
+ /// [Bit 1] CYCEn.
+ ///
+ UINT32 CYCEn:1;
+ ///
+ /// [Bit 2] OS.
+ ///
+ UINT32 OS:1;
+ ///
+ /// [Bit 3] User.
+ ///
+ UINT32 User:1;
+ UINT32 Reserved1:3;
+ ///
+ /// [Bit 7] CR3 filter.
+ ///
+ UINT32 CR3:1;
+ ///
+ /// [Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn.
+ ///
+ UINT32 ToPA:1;
+ ///
+ /// [Bit 9] MTCEn.
+ ///
+ UINT32 MTCEn:1;
+ ///
+ /// [Bit 10] TSCEn.
+ ///
+ UINT32 TSCEn:1;
+ ///
+ /// [Bit 11] DisRETC.
+ ///
+ UINT32 DisRETC:1;
+ UINT32 Reserved2:1;
+ ///
+ /// [Bit 13] BranchEn.
+ ///
+ UINT32 BranchEn:1;
+ ///
+ /// [Bits 17:14] MTCFreq.
+ ///
+ UINT32 MTCFreq:4;
+ UINT32 Reserved3:1;
+ ///
+ /// [Bits 22:19] CYCThresh.
+ ///
+ UINT32 CYCThresh:4;
+ UINT32 Reserved4:1;
+ ///
+ /// [Bits 27:24] PSBFreq.
+ ///
+ UINT32 PSBFreq:4;
+ UINT32 Reserved5:4;
+ ///
+ /// [Bits 35:32] ADDR0_CFG.
+ ///
+ UINT32 ADDR0_CFG:4;
+ ///
+ /// [Bits 39:36] ADDR1_CFG.
+ ///
+ UINT32 ADDR1_CFG:4;
+ UINT32 Reserved6:24;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER;
+
+
+/**
+ Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
+ "RAPL Interfaces.".
+
+ @param ECX MSR_GOLDMONT_RAPL_POWER_UNIT (0x00000606)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_RAPL_POWER_UNIT);
+ @endcode
+ @note MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
+**/
+#define MSR_GOLDMONT_RAPL_POWER_UNIT 0x00000606
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 3:0] Power Units. Power related information (in Watts) is in
+ /// unit of, 1W/2^PU; where PU is an unsigned integer represented by bits
+ /// 3:0. Default value is 1000b, indicating power unit is in 3.9
+ /// milliWatts increment.
+ ///
+ UINT32 PowerUnits:4;
+ UINT32 Reserved1:4;
+ ///
+ /// [Bits 12:8] Energy Status Units. Energy related information (in
+ /// Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned
+ /// integer represented by bits 12:8. Default value is 01110b, indicating
+ /// energy unit is in 61 microJoules.
+ ///
+ UINT32 EnergyStatusUnits:5;
+ UINT32 Reserved2:3;
+ ///
+ /// [Bits 19:16] Time Unit. Time related information (in seconds) is in
+ /// unit of, 1S/2^TU; where TU is an unsigned integer represented by bits
+ /// 19:16. Default value is 1010b, indicating power unit is in 0.977
+ /// millisecond.
+ ///
+ UINT32 TimeUnit:4;
+ UINT32 Reserved3:12;
+ UINT32 Reserved4:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER;
+
+
+/**
+ Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are
+ processor specific C-state code names, unrelated to MWAIT extension C-state
+ parameters or ACPI CStates.
+
+ @param ECX MSR_GOLDMONT_PKGC3_IRTL (0x0000060A)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_PKGC3_IRTL_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC3_IRTL);
+ AsmWriteMsr64 (MSR_GOLDMONT_PKGC3_IRTL, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.
+**/
+#define MSR_GOLDMONT_PKGC3_IRTL 0x0000060A
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
+ /// that should be used to decide if the package should be put into a
+ /// package C3 state.
+ ///
+ UINT32 InterruptResponseTimeLimit:10;
+ ///
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
+ /// unit of the interrupt response time limit. See Table 35-18 for
+ /// supported time unit encodings.
+ ///
+ UINT32 TimeUnit:3;
+ UINT32 Reserved1:2;
+ ///
+ /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
+ /// valid and can be used by the processor for package C-sate management.
+ ///
+ UINT32 Valid:1;
+ UINT32 Reserved2:16;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_PKGC3_IRTL_REGISTER;
+
+
+/**
+ Package. Package C6/C7S Interrupt Response Limit 1 (R/W) This MSR defines
+ the interrupt response time limit used by the processor to manage transition
+ to package C6 or C7S state. Note: C-state values are processor specific
+ C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
+ CStates.
+
+ @param ECX MSR_GOLDMONT_PKGC_IRTL1 (0x0000060B)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_PKGC_IRTL1_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL1);
+ AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL1, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.
+**/
+#define MSR_GOLDMONT_PKGC_IRTL1 0x0000060B
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
+ /// that should be used to decide if the package should be put into a
+ /// package C6 or C7S state.
+ ///
+ UINT32 InterruptResponseTimeLimit:10;
+ ///
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
+ /// unit of the interrupt response time limit. See Table 35-18 for
+ /// supported time unit encodings.
+ ///
+ UINT32 TimeUnit:3;
+ UINT32 Reserved1:2;
+ ///
+ /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
+ /// valid and can be used by the processor for package C-sate management.
+ ///
+ UINT32 Valid:1;
+ UINT32 Reserved2:16;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_PKGC_IRTL1_REGISTER;
+
+
+/**
+ Package. Package C7 Interrupt Response Limit 2 (R/W) This MSR defines the
+ interrupt response time limit used by the processor to manage transition to
+ package C7 state. Note: C-state values are processor specific C-state code
+ names, unrelated to MWAIT extension C-state parameters or ACPI CStates.
+
+ @param ECX MSR_GOLDMONT_PKGC_IRTL2 (0x0000060C)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_PKGC_IRTL2_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL2);
+ AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL2, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.
+**/
+#define MSR_GOLDMONT_PKGC_IRTL2 0x0000060C
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
+ /// that should be used to decide if the package should be put into a
+ /// package C7 state.
+ ///
+ UINT32 InterruptResponseTimeLimit:10;
+ ///
+ /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
+ /// unit of the interrupt response time limit. See Table 35-18 for
+ /// supported time unit encodings.
+ ///
+ UINT32 TimeUnit:3;
+ UINT32 Reserved1:2;
+ ///
+ /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
+ /// valid and can be used by the processor for package C-sate management.
+ ///
+ UINT32 Valid:1;
+ UINT32 Reserved2:16;
+ UINT32 Reserved3:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_PKGC_IRTL2_REGISTER;
+
+
+/**
+ Package. Note: C-state values are processor specific C-state code names,
+ unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2
+ Residency Counter. (R/O) Value since last reset that this package is in
+ processor-specific C2 states. Count at the same frequency as the TSC.
+
+ @param ECX MSR_GOLDMONT_PKG_C2_RESIDENCY (0x0000060D)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY);
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY, Msr);
+ @endcode
+ @note MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_PKG_C2_RESIDENCY 0x0000060D
+
+
+/**
+ Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
+ RAPL Domain.".
+
+ @param ECX MSR_GOLDMONT_PKG_POWER_LIMIT (0x00000610)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT);
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT, Msr);
+ @endcode
+ @note MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
+**/
+#define MSR_GOLDMONT_PKG_POWER_LIMIT 0x00000610
+
+
+/**
+ Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
+
+ @param ECX MSR_GOLDMONT_PKG_ENERGY_STATUS (0x00000611)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_ENERGY_STATUS);
+ @endcode
+ @note MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_PKG_ENERGY_STATUS 0x00000611
+
+
+/**
+ Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
+
+ @param ECX MSR_GOLDMONT_PKG_PERF_STATUS (0x00000613)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_PERF_STATUS);
+ @endcode
+ @note MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_PKG_PERF_STATUS 0x00000613
+
+
+/**
+ Package. PKG RAPL Parameters (R/W).
+
+ @param ECX MSR_GOLDMONT_PKG_POWER_INFO (0x00000614)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_PKG_POWER_INFO_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_INFO);
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_INFO, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
+**/
+#define MSR_GOLDMONT_PKG_POWER_INFO 0x00000614
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 14:0] Thermal Spec Power (R/W) See Section 14.9.3, "Package
+ /// RAPL Domain.".
+ ///
+ UINT32 ThermalSpecPower:15;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bits 30:16] Minimum Power (R/W) See Section 14.9.3, "Package RAPL
+ /// Domain.".
+ ///
+ UINT32 MinimumPower:15;
+ UINT32 Reserved2:1;
+ ///
+ /// [Bits 46:32] Maximum Power (R/W) See Section 14.9.3, "Package RAPL
+ /// Domain.".
+ ///
+ UINT32 MaximumPower:15;
+ UINT32 Reserved3:1;
+ ///
+ /// [Bits 54:48] Maximum Time Window (R/W) Specified by 2^Y * (1.0 +
+ /// Z/4.0) * Time_Unit, where "Y" is the unsigned integer value
+ /// represented. by bits 52:48, "Z" is an unsigned integer represented by
+ /// bits 54:53. "Time_Unit" is specified by the "Time Units" field of
+ /// MSR_RAPL_POWER_UNIT.
+ ///
+ UINT32 MaximumTimeWindow:7;
+ UINT32 Reserved4:9;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_PKG_POWER_INFO_REGISTER;
+
+
+/**
+ Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
+ Domain.".
+
+ @param ECX MSR_GOLDMONT_DRAM_POWER_LIMIT (0x00000618)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT);
+ AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT, Msr);
+ @endcode
+ @note MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
+**/
+#define MSR_GOLDMONT_DRAM_POWER_LIMIT 0x00000618
+
+
+/**
+ Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
+
+ @param ECX MSR_GOLDMONT_DRAM_ENERGY_STATUS (0x00000619)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_ENERGY_STATUS);
+ @endcode
+ @note MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_DRAM_ENERGY_STATUS 0x00000619
+
+
+/**
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+ RAPL Domain.".
+
+ @param ECX MSR_GOLDMONT_DRAM_PERF_STATUS (0x0000061B)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_PERF_STATUS);
+ @endcode
+ @note MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_DRAM_PERF_STATUS 0x0000061B
+
+
+/**
+ Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
+
+ @param ECX MSR_GOLDMONT_DRAM_POWER_INFO (0x0000061C)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO);
+ AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO, Msr);
+ @endcode
+ @note MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
+**/
+#define MSR_GOLDMONT_DRAM_POWER_INFO 0x0000061C
+
+
+/**
+ Package. Note: C-state values are processor specific C-state code names,.
+ Package C10 Residency Counter. (R/O) Value since last reset that the entire
+ SOC is in an S0i3 state. Count at the same frequency as the TSC.
+
+ @param ECX MSR_GOLDMONT_PKG_C10_RESIDENCY (0x00000632)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY);
+ AsmWriteMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY, Msr);
+ @endcode
+ @note MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_PKG_C10_RESIDENCY 0x00000632
+
+
+/**
+ Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
+ Domains.".
+
+ @param ECX MSR_GOLDMONT_PP0_ENERGY_STATUS (0x00000639)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PP0_ENERGY_STATUS);
+ @endcode
+ @note MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_PP0_ENERGY_STATUS 0x00000639
+
+
+/**
+ Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
+ Domains.".
+
+ @param ECX MSR_GOLDMONT_PP1_ENERGY_STATUS (0x00000641)
+ @param EAX Lower 32-bits of MSR value.
+ @param EDX Upper 32-bits of MSR value.
+
+ <b>Example usage</b>
+ @code
+ UINT64 Msr;
+
+ Msr = AsmReadMsr64 (MSR_GOLDMONT_PP1_ENERGY_STATUS);
+ @endcode
+ @note MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_PP1_ENERGY_STATUS 0x00000641
+
+
+/**
+ Package. ConfigTDP Control (R/W).
+
+ @param ECX MSR_GOLDMONT_TURBO_ACTIVATION_RATIO (0x0000064C)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO);
+ AsmWriteMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
+**/
+#define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 0x0000064C
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
+ /// field.
+ ///
+ UINT32 MAX_NON_TURBO_RATIO:8;
+ UINT32 Reserved1:23;
+ ///
+ /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
+ /// content of this register is locked until a reset.
+ ///
+ UINT32 TURBO_ACTIVATION_RATIO_Lock:1;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER;
+
+
+/**
+ Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
+ refers to processor core frequency).
+
+ @param ECX MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS (0x0000064F)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS);
+ AsmWriteMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 0x0000064F
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
+ /// reduced below the operating system request due to assertion of
+ /// external PROCHOT.
+ ///
+ UINT32 PROCHOTStatus:1;
+ ///
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+ /// operating system request due to a thermal event.
+ ///
+ UINT32 ThermalStatus:1;
+ ///
+ /// [Bit 2] Package-Level Power Limiting PL1 Status (R0) When set,
+ /// frequency is reduced below the operating system request due to
+ /// package-level power limiting PL1.
+ ///
+ UINT32 PL1Status:1;
+ ///
+ /// [Bit 3] Package-Level PL2 Power Limiting Status (R0) When set,
+ /// frequency is reduced below the operating system request due to
+ /// package-level power limiting PL2.
+ ///
+ UINT32 PL2Status:1;
+ UINT32 Reserved1:5;
+ ///
+ /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced
+ /// below the operating system request due to domain-level power limiting.
+ ///
+ UINT32 PowerLimitingStatus:1;
+ ///
+ /// [Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced
+ /// below the operating system request due to a thermal alert from the
+ /// Voltage Regulator.
+ ///
+ UINT32 VRThermAlertStatus:1;
+ ///
+ /// [Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced
+ /// below the operating system request due to multi-core turbo limits.
+ ///
+ UINT32 MaxTurboLimitStatus:1;
+ ///
+ /// [Bit 12] Electrical Design Point Status (R0) When set, frequency is
+ /// reduced below the operating system request due to electrical design
+ /// point constraints (e.g. maximum electrical current consumption).
+ ///
+ UINT32 ElectricalDesignPointStatus:1;
+ ///
+ /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
+ /// is reduced below the operating system request due to Turbo transition
+ /// attenuation. This prevents performance degradation due to frequent
+ /// operating ratio changes.
+ ///
+ UINT32 TurboTransitionAttenuationStatus:1;
+ ///
+ /// [Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency
+ /// is reduced below the maximum efficiency frequency.
+ ///
+ UINT32 MaximumEfficiencyFrequencyStatus:1;
+ UINT32 Reserved2:1;
+ ///
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
+ /// has asserted since the log bit was last cleared. This log bit will
+ /// remain set until cleared by software writing 0.
+ ///
+ UINT32 PROCHOT:1;
+ ///
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
+ /// has asserted since the log bit was last cleared. This log bit will
+ /// remain set until cleared by software writing 0.
+ ///
+ UINT32 ThermalLog:1;
+ ///
+ /// [Bit 18] Package-Level PL1 Power Limiting Log When set, indicates
+ /// that the Package Level PL1 Power Limiting Status bit has asserted
+ /// since the log bit was last cleared. This log bit will remain set until
+ /// cleared by software writing 0.
+ ///
+ UINT32 PL1Log:1;
+ ///
+ /// [Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that
+ /// the Package Level PL2 Power Limiting Status bit has asserted since the
+ /// log bit was last cleared. This log bit will remain set until cleared
+ /// by software writing 0.
+ ///
+ UINT32 PL2Log:1;
+ UINT32 Reserved3:5;
+ ///
+ /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
+ /// Power Limiting Status bit has asserted since the log bit was last
+ /// cleared. This log bit will remain set until cleared by software
+ /// writing 0.
+ ///
+ UINT32 CorePowerLimitingLog:1;
+ ///
+ /// [Bit 26] VR Therm Alert Log When set, indicates that the VR Therm
+ /// Alert Status bit has asserted since the log bit was last cleared. This
+ /// log bit will remain set until cleared by software writing 0.
+ ///
+ UINT32 VRThermAlertLog:1;
+ ///
+ /// [Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo
+ /// Limit Status bit has asserted since the log bit was last cleared. This
+ /// log bit will remain set until cleared by software writing 0.
+ ///
+ UINT32 MaxTurboLimitLog:1;
+ ///
+ /// [Bit 28] Electrical Design Point Log When set, indicates that the EDP
+ /// Status bit has asserted since the log bit was last cleared. This log
+ /// bit will remain set until cleared by software writing 0.
+ ///
+ UINT32 ElectricalDesignPointLog:1;
+ ///
+ /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
+ /// Turbo Transition Attenuation Status bit has asserted since the log bit
+ /// was last cleared. This log bit will remain set until cleared by
+ /// software writing 0.
+ ///
+ UINT32 TurboTransitionAttenuationLog:1;
+ ///
+ /// [Bit 30] Maximum Efficiency Frequency Log When set, indicates that
+ /// the Maximum Efficiency Frequency Status bit has asserted since the log
+ /// bit was last cleared. This log bit will remain set until cleared by
+ /// software writing 0.
+ ///
+ UINT32 MaximumEfficiencyFrequencyLog:1;
+ UINT32 Reserved4:1;
+ UINT32 Reserved5:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+ Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch
+ record registers on the last branch record stack. The From_IP part of the
+ stack contains pointers to the source instruction . See also: - Last Branch
+ Record Stack TOS at 1C9H - Section 17.6 and record format in Section
+ 17.4.8.1.
+
+ @param ECX MSR_GOLDMONT_LASTBRANCH_n_FROM_IP
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP);
+ AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.
+ @{
+**/
+#define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 0x00000680
+#define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP 0x00000681
+#define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP 0x00000682
+#define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP 0x00000683
+#define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP 0x00000684
+#define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP 0x00000685
+#define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP 0x00000686
+#define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP 0x00000687
+#define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP 0x00000688
+#define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP 0x00000689
+#define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP 0x0000068A
+#define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP 0x0000068B
+#define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP 0x0000068C
+#define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP 0x0000068D
+#define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP 0x0000068E
+#define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP 0x0000068F
+#define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP 0x00000690
+#define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP 0x00000691
+#define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP 0x00000692
+#define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP 0x00000693
+#define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP 0x00000694
+#define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP 0x00000695
+#define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP 0x00000696
+#define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP 0x00000697
+#define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP 0x00000698
+#define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP 0x00000699
+#define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP 0x0000069A
+#define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP 0x0000069B
+#define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP 0x0000069C
+#define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP 0x0000069D
+#define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP 0x0000069E
+#define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP 0x0000069F
+/// @}
+
+/**
+ MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_FROM_IP
+ to #MSR_GOLDMONT_LASTBRANCH_31_FROM_IP.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 31:0] From Linear Address (R/W).
+ ///
+ UINT32 FromLinearAddress:32;
+ ///
+ /// [Bit 47:32] From Linear Address (R/W).
+ ///
+ UINT32 FromLinearAddressHi:16;
+ ///
+ /// [Bits 62:48] Signed extension of bits 47:0.
+ ///
+ UINT32 SignedExtension:15;
+ ///
+ /// [Bit 63] Mispred.
+ ///
+ UINT32 Mispred:1;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER;
+
+
+/**
+ Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record
+ registers on the last branch record stack. The To_IP part of the stack
+ contains pointers to the Destination instruction and elapsed cycles from
+ last LBR update. See also: - Section 17.6.
+
+ @param ECX MSR_GOLDMONT_LASTBRANCH_n_TO_IP
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP);
+ AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.
+ MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.
+ @{
+**/
+#define MSR_GOLDMONT_LASTBRANCH_0_TO_IP 0x000006C0
+#define MSR_GOLDMONT_LASTBRANCH_1_TO_IP 0x000006C1
+#define MSR_GOLDMONT_LASTBRANCH_2_TO_IP 0x000006C2
+#define MSR_GOLDMONT_LASTBRANCH_3_TO_IP 0x000006C3
+#define MSR_GOLDMONT_LASTBRANCH_4_TO_IP 0x000006C4
+#define MSR_GOLDMONT_LASTBRANCH_5_TO_IP 0x000006C5
+#define MSR_GOLDMONT_LASTBRANCH_6_TO_IP 0x000006C6
+#define MSR_GOLDMONT_LASTBRANCH_7_TO_IP 0x000006C7
+#define MSR_GOLDMONT_LASTBRANCH_8_TO_IP 0x000006C8
+#define MSR_GOLDMONT_LASTBRANCH_9_TO_IP 0x000006C9
+#define MSR_GOLDMONT_LASTBRANCH_10_TO_IP 0x000006CA
+#define MSR_GOLDMONT_LASTBRANCH_11_TO_IP 0x000006CB
+#define MSR_GOLDMONT_LASTBRANCH_12_TO_IP 0x000006CC
+#define MSR_GOLDMONT_LASTBRANCH_13_TO_IP 0x000006CD
+#define MSR_GOLDMONT_LASTBRANCH_14_TO_IP 0x000006CE
+#define MSR_GOLDMONT_LASTBRANCH_15_TO_IP 0x000006CF
+#define MSR_GOLDMONT_LASTBRANCH_16_TO_IP 0x000006D0
+#define MSR_GOLDMONT_LASTBRANCH_17_TO_IP 0x000006D1
+#define MSR_GOLDMONT_LASTBRANCH_18_TO_IP 0x000006D2
+#define MSR_GOLDMONT_LASTBRANCH_19_TO_IP 0x000006D3
+#define MSR_GOLDMONT_LASTBRANCH_20_TO_IP 0x000006D4
+#define MSR_GOLDMONT_LASTBRANCH_21_TO_IP 0x000006D5
+#define MSR_GOLDMONT_LASTBRANCH_22_TO_IP 0x000006D6
+#define MSR_GOLDMONT_LASTBRANCH_23_TO_IP 0x000006D7
+#define MSR_GOLDMONT_LASTBRANCH_24_TO_IP 0x000006D8
+#define MSR_GOLDMONT_LASTBRANCH_25_TO_IP 0x000006D9
+#define MSR_GOLDMONT_LASTBRANCH_26_TO_IP 0x000006DA
+#define MSR_GOLDMONT_LASTBRANCH_27_TO_IP 0x000006DB
+#define MSR_GOLDMONT_LASTBRANCH_28_TO_IP 0x000006DC
+#define MSR_GOLDMONT_LASTBRANCH_29_TO_IP 0x000006DD
+#define MSR_GOLDMONT_LASTBRANCH_30_TO_IP 0x000006DE
+#define MSR_GOLDMONT_LASTBRANCH_31_TO_IP 0x000006DF
+/// @}
+
+/**
+ MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_TO_IP to
+ #MSR_GOLDMONT_LASTBRANCH_31_TO_IP.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 31:0] Target Linear Address (R/W).
+ ///
+ UINT32 TargetLinearAddress:32;
+ ///
+ /// [Bit 47:32] Target Linear Address (R/W).
+ ///
+ UINT32 TargetLinearAddressHi:16;
+ ///
+ /// [Bits 63:48] Elapsed cycles from last update to the LBR.
+ ///
+ UINT32 ElapsedCycles:16;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER;
+
+
+/**
+ Core. Resource Association Register (R/W).
+
+ @param ECX MSR_GOLDMONT_IA32_PQR_ASSOC (0x00000C8F)
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC);
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
+**/
+#define MSR_GOLDMONT_IA32_PQR_ASSOC 0x00000C8F
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ UINT32 Reserved1:32;
+ ///
+ /// [Bits 33:32] COS (R/W).
+ ///
+ UINT32 COS:2;
+ UINT32 Reserved2:30;
+ } Bits;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER;
+
+
+/**
+ Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,
+ ECX=1):EDX.COS_MAX[15:0] >=n.
+
+ @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_n
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n);
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_IA32_L2_QOS_MASK_0 is defined as IA32_L2_QOS_MASK_0 in SDM.
+ MSR_GOLDMONT_IA32_L2_QOS_MASK_1 is defined as IA32_L2_QOS_MASK_1 in SDM.
+ MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM.
+ @{
+**/
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_0 0x00000D10
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_1 0x00000D11
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_2 0x00000D12
+/// @}
+
+/**
+ MSR information returned for MSR indexes #MSR_GOLDMONT_IA32_L2_QOS_MASK_0 to
+ #MSR_GOLDMONT_IA32_L2_QOS_MASK_2.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement
+ ///
+ UINT32 CBM:8;
+ UINT32 Reserved1:24;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER;
+
+
+/**
+ Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H,
+ ECX=1):EDX.COS_MAX[15:0] >=3.
+
+ @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_3
+ @param EAX Lower 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.
+ @param EDX Upper 32-bits of MSR value.
+ Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.
+
+ <b>Example usage</b>
+ @code
+ MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3);
+ AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3, Msr.Uint64);
+ @endcode
+ @note MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM.
+**/
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_3 0x00000D13
+
+/**
+ MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement
+ ///
+ UINT32 CBM:20;
+ UINT32 Reserved1:12;
+ UINT32 Reserved2:32;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+ ///
+ /// All bit fields as a 64-bit value
+ ///
+ UINT64 Uint64;
+} MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER;
+
+
+#endif
--
1.9.5.msysgit.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/4] UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016)
2016-12-14 8:33 [PATCH 0/4] Update CPUID & MSR header files with SDM (Sep.2016) Hao Wu
` (2 preceding siblings ...)
2016-12-14 8:33 ` [PATCH 3/4] UefiCpuPkg/Include: Add Goldmont " Hao Wu
@ 2016-12-14 8:33 ` Hao Wu
2016-12-15 18:16 ` [PATCH 0/4] Update CPUID & MSR header files " Kinney, Michael D
4 siblings, 0 replies; 6+ messages in thread
From: Hao Wu @ 2016-12-14 8:33 UTC (permalink / raw)
To: edk2-devel; +Cc: Hao Wu, Michael Kinney, Jeff Fan
https://bugzilla.tianocore.org/show_bug.cgi?id=176
Update CPUID leaf and sub-leaf indexes and structures as described by
Intel(R) 64 and IA-32 Architectures Software Developer's Manual,
Volume 2A, September 2016, CPUID instruction.
Summary of incompatible changes:
1. Field name changes in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
Bit 12 has been renamed from 'PQM' to 'RDT_M' and bit 15 has been renamed
from 'PQE' to 'RDT_A'.
2. Stucture and filed name changes for 'CPUID Platform QoS Monitoring
Information' related definitions
Definition 'CPUID_PLATFORM_QOS_MONITORING' has been renamed to
'CPUID_INTEL_RDT_MONITORING'.
Definition 'CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF' has been
renamed to 'CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF'.
Definition 'CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF' has been
renamed to 'CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF'.
3. Stucture and filed name changes for 'CPUID Platform QoS Enforcement
Information' related definitions
Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT' has been renamed to
'CPUID_INTEL_RDT_ALLOCATION'.
Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF' has been renamed to
'CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF'.
Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF' has been
renamed to 'CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF'.
This commit also updates the relating codes in
UefiCpuPkg/Application/Cpuid to reflect the changes.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
---
UefiCpuPkg/Application/Cpuid/Cpuid.c | 115 +++++++----
UefiCpuPkg/Include/Register/Cpuid.h | 363 ++++++++++++++++++++++++-----------
2 files changed, 325 insertions(+), 153 deletions(-)
diff --git a/UefiCpuPkg/Application/Cpuid/Cpuid.c b/UefiCpuPkg/Application/Cpuid/Cpuid.c
index ac14c41..2efad68 100644
--- a/UefiCpuPkg/Application/Cpuid/Cpuid.c
+++ b/UefiCpuPkg/Application/Cpuid/Cpuid.c
@@ -88,13 +88,14 @@ CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = {
{ 0x56 , "TLB" , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },
{ 0x57 , "TLB" , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },
{ 0x59 , "TLB" , "Data TLB0: 4 KByte pages, fully associative, 16 entries" },
- { 0x5A , "TLB" , "Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries" },
+ { 0x5A , "TLB" , "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },
{ 0x5B , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },
{ 0x5C , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,128 entries" },
{ 0x5D , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,256 entries" },
{ 0x60 , "Cache" , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },
{ 0x61 , "TLB" , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },
- { 0x63 , "TLB" , "Data TLB: 1 GByte pages, 4-way set associative, 4 entries" },
+ { 0x63 , "TLB" , "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },
+ { 0x64 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },
{ 0x66 , "Cache" , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },
{ 0x67 , "Cache" , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },
{ 0x68 , "Cache" , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },
@@ -133,6 +134,7 @@ CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = {
{ 0xC1 , "STLB" , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },
{ 0xC2 , "DTLB" , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },
{ 0xC3 , "STLB" , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },
+ { 0xC4 , "DTLB" , "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },
{ 0xCA , "STLB" , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },
{ 0xD0 , "Cache" , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },
{ 0xD1 , "Cache" , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },
@@ -604,18 +606,24 @@ CpuidStructuredExtendedFeatureFlags (
PRINT_BIT_FIELD (Ebx, EnhancedRepMovsbStosb);
PRINT_BIT_FIELD (Ebx, INVPCID);
PRINT_BIT_FIELD (Ebx, RTM);
- PRINT_BIT_FIELD (Ebx, PQM);
+ PRINT_BIT_FIELD (Ebx, RDT_M);
PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs);
PRINT_BIT_FIELD (Ebx, MPX);
- PRINT_BIT_FIELD (Ebx, PQE);
+ PRINT_BIT_FIELD (Ebx, RDT_A);
PRINT_BIT_FIELD (Ebx, RDSEED);
PRINT_BIT_FIELD (Ebx, ADX);
PRINT_BIT_FIELD (Ebx, SMAP);
PRINT_BIT_FIELD (Ebx, CLFLUSHOPT);
+ PRINT_BIT_FIELD (Ebx, CLWB);
PRINT_BIT_FIELD (Ebx, IntelProcessorTrace);
+ PRINT_BIT_FIELD (Ebx, SHA);
PRINT_BIT_FIELD (Ecx, PREFETCHWT1);
+ PRINT_BIT_FIELD (Ecx, UMIP);
PRINT_BIT_FIELD (Ecx, PKU);
PRINT_BIT_FIELD (Ecx, OSPKE);
+ PRINT_BIT_FIELD (Ecx, MAWAU);
+ PRINT_BIT_FIELD (Ecx, RDPID);
+ PRINT_BIT_FIELD (Ecx, SGX_LC);
}
}
}
@@ -815,78 +823,81 @@ CpuidExtendedStateMainLeaf (
}
/**
- Display CPUID_PLATFORM_QOS_MONITORING enumeration sub-leaf.
+ Display CPUID_INTEL_RDT_MONITORING enumeration sub-leaf.
**/
VOID
-CpuidPlatformQosMonitoringEnumerationSubLeaf (
+CpuidIntelRdtMonitoringEnumerationSubLeaf (
VOID
)
{
UINT32 Ebx;
- CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
+ CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
- if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) {
+ if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {
return;
}
AsmCpuidEx (
- CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,
+ CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
NULL, &Ebx, NULL, &Edx.Uint32
);
- Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF);
+ Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);
PRINT_VALUE (Ebx, Maximum_RMID_Range);
- PRINT_BIT_FIELD (Edx, L3CacheQosEnforcement);
+ PRINT_BIT_FIELD (Edx, L3CacheRDT_M);
}
/**
- Display CPUID_PLATFORM_QOS_MONITORING capability sub-leaf.
+ Display CPUID_INTEL_RDT_MONITORING L3 cache capability sub-leaf.
**/
VOID
-CpuidPlatformQosMonitoringCapabilitySubLeaf (
+CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (
VOID
)
{
UINT32 Ebx;
UINT32 Ecx;
- CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;
+ CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;
- if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) {
+ if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {
return;
}
AsmCpuidEx (
- CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,
+ CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
NULL, &Ebx, &Ecx, &Edx.Uint32
);
- Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF);
+ Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);
PRINT_VALUE (Ebx, OccupancyConversionFactor);
PRINT_VALUE (Ecx, Maximum_RMID_Range);
PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);
+ PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring);
+ PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring);
}
/**
- Display CPUID_PLATFORM_QOS_ENFORCEMENT sub-leaf.
+ Display CPUID_INTEL_RDT_ALLOCATION L3 cache allocation technology enumeration
+ sub-leaf.
**/
VOID
-CpuidPlatformQosEnforcementResidSubLeaf (
+CpuidIntelRdtAllocationL3CacheSubLeaf (
VOID
)
{
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;
UINT32 Ebx;
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
AsmCpuidEx (
- CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
);
- Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF);
+ Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);
PRINT_BIT_FIELD (Eax, CapacityLength);
PRINT_VALUE (Ebx, AllocationUnitBitMap);
@@ -896,29 +907,56 @@ CpuidPlatformQosEnforcementResidSubLeaf (
}
/**
- Display CPUID_PLATFORM_QOS_ENFORCEMENT main leaf and sub-leaf.
+ Display CPUID_INTEL_RDT_ALLOCATION L2 cache allocation technology enumeration
+ sub-leaf.
**/
VOID
-CpuidPlatformQosEnforcementMainLeaf (
+CpuidIntelRdtAllocationL2CacheSubLeaf (
VOID
)
{
- CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;
+ UINT32 Ebx;
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
+
+ AsmCpuidEx (
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
+ &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
+ );
+ Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);
+ Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);
+ PRINT_BIT_FIELD (Eax, CapacityLength);
+ PRINT_VALUE (Ebx, AllocationUnitBitMap);
+ PRINT_BIT_FIELD (Edx, HighestCosNumber);
+}
+
+/**
+ Display CPUID_INTEL_RDT_ALLOCATION main leaf and sub-leaves.
+
+**/
+VOID
+CpuidIntelRdtAllocationMainLeaf (
+ VOID
+ )
+{
+ CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;
- if (CPUID_PLATFORM_QOS_ENFORCEMENT > gMaximumBasicFunction) {
+ if (CPUID_INTEL_RDT_ALLOCATION > gMaximumBasicFunction) {
return;
}
AsmCpuidEx (
- CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
NULL, &Ebx.Uint32, NULL, NULL
);
- Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF);
+ Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0);
- PRINT_BIT_FIELD (Ebx, L3CacheQosEnforcement);
+ PRINT_BIT_FIELD (Ebx, L3CacheAllocation);
+ PRINT_BIT_FIELD (Ebx, L2CacheAllocation);
- CpuidPlatformQosEnforcementResidSubLeaf ();
+ CpuidIntelRdtAllocationL3CacheSubLeaf ();
+ CpuidIntelRdtAllocationL2CacheSubLeaf ();
}
/**
@@ -1093,6 +1131,8 @@ CpuidIntelProcessorTraceMainLeaf (
PRINT_BIT_FIELD (Ebx, ConfigurablePsb);
PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);
PRINT_BIT_FIELD (Ebx, Mtc);
+ PRINT_BIT_FIELD (Ebx, PTWrite);
+ PRINT_BIT_FIELD (Ebx, PowerEventTrace);
PRINT_BIT_FIELD (Ecx, RTIT);
PRINT_BIT_FIELD (Ecx, ToPA);
PRINT_BIT_FIELD (Ecx, SingleRangeOutput);
@@ -1113,14 +1153,15 @@ CpuidTimeStampCounter (
{
UINT32 Eax;
UINT32 Ebx;
+ UINT32 Ecx;
if (CPUID_TIME_STAMP_COUNTER > gMaximumBasicFunction) {
return;
}
- AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);
+ AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
Print (L"CPUID_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_TIME_STAMP_COUNTER);
- Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, 0, 0);
+ Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, 0);
}
/**
@@ -1446,9 +1487,9 @@ UefiMain (
CpuidArchitecturalPerformanceMonitoring ();
CpuidExtendedTopology ();
CpuidExtendedStateMainLeaf ();
- CpuidPlatformQosMonitoringEnumerationSubLeaf ();
- CpuidPlatformQosMonitoringCapabilitySubLeaf ();
- CpuidPlatformQosEnforcementMainLeaf ();
+ CpuidIntelRdtMonitoringEnumerationSubLeaf ();
+ CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf ();
+ CpuidIntelRdtAllocationMainLeaf ();
CpuidEnumerationOfIntelSgx ();
CpuidIntelProcessorTraceMainLeaf ();
CpuidTimeStampCounter ();
diff --git a/UefiCpuPkg/Include/Register/Cpuid.h b/UefiCpuPkg/Include/Register/Cpuid.h
index 864108d..5eb9650 100644
--- a/UefiCpuPkg/Include/Register/Cpuid.h
+++ b/UefiCpuPkg/Include/Register/Cpuid.h
@@ -17,7 +17,7 @@
@par Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
- December 2015, CPUID instruction.
+ September 2016, CPUID instruction.
**/
@@ -433,11 +433,10 @@ typedef union {
///
UINT32 PGE:1;
///
- /// [Bit 14] Machine Check Architecture. The Machine Check Architecture,
- /// which provides a compatible mechanism for error reporting in P6 family,
- /// Pentium 4, Intel Xeon processors, and future processors, is supported.
- /// The MCG_CAP MSR contains feature bits describing how many banks of error
- /// reporting MSRs are supported.
+ /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine
+ /// Check Architecture of reporting machine errors is supported. The MCG_CAP
+ /// MSR contains feature bits describing how many banks of error reporting
+ /// MSRs are supported.
///
UINT32 MCA:1;
///
@@ -634,13 +633,16 @@ typedef union {
<tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>
<tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>
<tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>
- <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
+ <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
<tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>
<tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>
<tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>
<tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>
<tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>
- <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 1 GByte pages, 4-way set associative, 4 entries</td></tr>
+ <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative,
+ 32 entries and a separate array with 1 GByte pages, 4-way set associative,
+ 4 entries</td></tr>
+ <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>
<tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>
<tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>
<tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>
@@ -686,6 +688,7 @@ typedef union {
<tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>
<tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,
1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>
+ <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>
<tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>
<tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
<tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>
@@ -1349,10 +1352,10 @@ typedef union {
///
UINT32 RTM:1;
///
- /// [Bit 12] Supports Platform Quality of Service Monitoring (PQM)
- /// capability if 1.
+ /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
+ /// Monitoring capability if 1.
///
- UINT32 PQM:1;
+ UINT32 RDT_M:1;
///
/// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
///
@@ -1362,10 +1365,10 @@ typedef union {
///
UINT32 MPX:1;
///
- /// [Bit 15] Supports Platform Quality of Service Enforcement (PQE)
- /// capability if 1.
+ /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
+ /// Allocation capability if 1.
///
- UINT32 PQE:1;
+ UINT32 RDT_A:1;
UINT32 Reserved2:2;
///
/// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
@@ -1386,13 +1389,22 @@ typedef union {
/// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
///
UINT32 CLFLUSHOPT:1;
- UINT32 Reserved4:1;
+ ///
+ /// [Bit 24] If 1 indicates the processor supports the CLWB instruction.
+ ///
+ UINT32 CLWB:1;
///
/// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
/// extensions.
///
UINT32 IntelProcessorTrace:1;
- UINT32 Reserved5:6;
+ UINT32 Reserved4:3;
+ ///
+ /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)
+ /// SHA Extensions) if 1.
+ ///
+ UINT32 SHA:1;
+ UINT32 Reserved5:2;
} Bits;
///
/// All bit fields as a 32-bit value
@@ -1414,7 +1426,11 @@ typedef union {
/// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
///
UINT32 PREFETCHWT1:1;
- UINT32 Reserved1:2;
+ UINT32 Reserved1:1;
+ ///
+ /// [Bit 2] Supports user-mode instruction prevention if 1.
+ ///
+ UINT32 UMIP:1;
///
/// [Bit 3] Supports protection keys for user-mode pages if 1.
///
@@ -1424,7 +1440,22 @@ typedef union {
/// RDPKRU/WRPKRU instructions).
///
UINT32 OSPKE:1;
- UINT32 Reserved2:27;
+ UINT32 Reserved2:12;
+ ///
+ /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
+ /// in 64-bit mode.
+ ///
+ UINT32 MAWAU:5;
+ ///
+ /// [Bit 22] Supports Read Processor ID if 1.
+ ///
+ UINT32 RDPID:1;
+ UINT32 Reserved3:7;
+ ///
+ /// [Bit 30] Supports SGX Launch Configuration if 1.
+ ///
+ UINT32 SGX_LC:1;
+ UINT32 Reserved4:1;
} Bits;
///
/// All bit fields as a 32-bit value
@@ -1756,7 +1787,7 @@ typedef union {
enabled.
@retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
area) of the XSAVE/XRSTOR save area required by all supported
- features in the processor, i.e all the valid bit fields in XCR0.
+ features in the processor, i.e., all the valid bit fields in XCR0.
@retval EDX Reports the supported bits of the upper 32 bits of XCR0.
XCR0[n+32] can be set to 1 only if EDX[n] is 1.
@@ -1991,45 +2022,46 @@ typedef union {
/**
- CPUID Platform QoS Monitoring Information
+ CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
- @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
- @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00).
- CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01).
+ @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
+ @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).
+ CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).
**/
-#define CPUID_PLATFORM_QOS_MONITORING 0x0F
+#define CPUID_INTEL_RDT_MONITORING 0x0F
/**
- CPUID Platform QoS Monitoring Information Enumeration Sub-leaf
+ CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
+ Enumeration Sub-leaf
- @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
- @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00)
+ @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
+ @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)
@retval EAX Reserved.
@retval EBX Maximum range (zero-based) of RMID within this physical
processor of all types.
@retval ECX Reserved.
- @retval EDX L3 Cache QoS Monitoring Information Enumeration described by the
- type CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX.
+ @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by
+ the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.
<b>Example usage</b>
@code
UINT32 Ebx;
- CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
+ CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
AsmCpuidEx (
- CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,
+ CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
NULL, &Ebx, NULL, &Edx.Uint32
);
@endcode
**/
-#define CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF 0x00
+#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00
/**
- CPUID Platform QoS Monitoring Information EDX for CPUID leaf
- #CPUID_PLATFORM_QOS_MONITORING, sub-leaf
- #CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF.
+ CPUID Intel RDT Monitoring Information EDX for CPUID leaf
+ #CPUID_INTEL_RDT_MONITORING, sub-leaf
+ #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.
**/
typedef union {
///
@@ -2038,47 +2070,47 @@ typedef union {
struct {
UINT32 Reserved1:1;
///
- /// [Bit 1] Supports L3 Cache QoS Monitoring if 1.
+ /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.
///
- UINT32 L3CacheQosEnforcement:1;
+ UINT32 L3CacheRDT_M:1;
UINT32 Reserved2:30;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
-} CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX;
+} CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;
/**
- CPUID Platform QoS Monitoring Information Capability Sub-leaf
+ CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf
- @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)
- @param ECX CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01)
+ @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
+ @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)
@retval EAX Reserved.
@retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
@retval ECX Maximum range (zero-based) of RMID of this resource type.
- @retval EDX L3 Cache QoS Monitoring Capability information described by the
- type CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX.
+ @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the
+ type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.
<b>Example usage</b>
@code
- UINT32 Ebx;
- UINT32 Ecx;
- CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;
+ UINT32 Ebx;
+ UINT32 Ecx;
+ CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;
AsmCpuidEx (
- CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,
+ CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
NULL, &Ebx, &Ecx, &Edx.Uint32
);
@endcode
**/
-#define CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF 0x01
+#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01
/**
- CPUID Platform QoS Monitoring Information Capability EDX for CPUID leaf
- #CPUID_PLATFORM_QOS_MONITORING, sub-leaf
- #CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF.
+ CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf
+ #CPUID_INTEL_RDT_MONITORING, sub-leaf
+ #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.
**/
typedef union {
///
@@ -2089,53 +2121,61 @@ typedef union {
/// [Bit 0] Supports L3 occupancy monitoring if 1.
///
UINT32 L3CacheOccupancyMonitoring:1;
- UINT32 Reserved:31;
+ ///
+ /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.
+ ///
+ UINT32 L3CacheTotalBandwidthMonitoring:1;
+ ///
+ /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.
+ ///
+ UINT32 L3CacheLocalBandwidthMonitoring:1;
+ UINT32 Reserved:29;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
-} CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX;
+} CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;
/**
- CPUID Platform QoS Enforcement Information
+ CPUID Intel Resource Director Technology (Intel RDT) Allocation Information
- @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10).
- @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x01).
- Additional sub leafs 1..n based in RESID from sub leaf 0x00.
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10).
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).
**/
-#define CPUID_PLATFORM_QOS_ENFORCEMENT 0x10
+#define CPUID_INTEL_RDT_ALLOCATION 0x10
/**
- CPUID Platform QoS Enforcement Information
+ Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf
- @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)
- @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
@retval EAX Reserved.
- @retval EBX L3 Cache QoS Enforcement information described by the
- type CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX.
+ @retval EBX L3 and L2 Cache Allocation Technology information described by
+ the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.
@retval ECX Reserved.
@retval EDX Reserved.
<b>Example usage</b>
@code
- CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;
+ CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;
AsmCpuidEx (
- CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
NULL, &Ebx.Uint32, NULL, NULL
);
@endcode
**/
-#define CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF 0x00
+#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00
/**
- CPUID Platform QoS Enforcement Information EBX for CPUID leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF.
+ CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+ #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.
**/
typedef union {
///
@@ -2144,52 +2184,55 @@ typedef union {
struct {
UINT32 Reserved1:1;
///
- /// [Bit 1] Supports L3 Cache QoS Enforcement if 1.
+ /// [Bit 1] Supports L3 Cache Allocation Technology if 1.
///
- UINT32 L3CacheQosEnforcement:1;
- UINT32 Reserved2:30;
+ UINT32 L3CacheAllocation:1;
+ ///
+ /// [Bit 2] Supports L2 Cache Allocation Technology if 1.
+ ///
+ UINT32 L2CacheAllocation:1;
+ UINT32 Reserved2:29;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
-} CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX;
+} CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;
/**
- CPUID Platform QoS Enforcement Information
+ L3 Cache Allocation Technology Enumeration Sub-leaf
- @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)
- @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x00)
- Additional sub leafs 1..n based in RESID from sub leaf 0x00.
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)
- @retval EAX RESID L3 Cache3 QoS Enforcement information described by the
- type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX.
+ @retval EAX RESID L3 Cache Allocation Technology information described by
+ the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.
@retval EBX Bit-granular map of isolation/contention of allocation units.
- @retval ECX RESID L3 Cache3 QoS Enforcement information described by the
- type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX.
- @retval EDX RESID L3 Cache3 QoS Enforcement information described by the
- type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX.
+ @retval ECX RESID L3 Cache Allocation Technology information described by
+ the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.
+ @retval EDX RESID L3 Cache Allocation Technology information described by
+ the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.
<b>Example usage</b>
@code
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;
UINT32 Ebx;
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;
- CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;
+ CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
AsmCpuidEx (
- CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
);
@endcode
**/
-#define CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF 0x01
+#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01
/**
- CPUID Platform QoS Enforcement Information EAX for CPUID leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
+ CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+ #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
**/
typedef union {
///
@@ -2197,21 +2240,22 @@ typedef union {
///
struct {
///
- /// [Bits 3:0] Length of the capacity bit mask for the corresponding ResID.
+ /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
+ /// using minus-one notation.
///
- UINT32 CapacityLength:4;
- UINT32 Reserved:28;
+ UINT32 CapacityLength:5;
+ UINT32 Reserved:27;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX;
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;
/**
- CPUID Platform QoS Enforcement Information ECX for CPUID leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
+ CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+ #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
**/
typedef union {
///
@@ -2233,12 +2277,12 @@ typedef union {
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX;
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;
/**
- CPUID Platform QoS Enforcement Information EDX for CPUID leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf
- #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.
+ CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+ #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
**/
typedef union {
///
@@ -2255,7 +2299,79 @@ typedef union {
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
-} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX;
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;
+
+/**
+ L2 Cache Allocation Technology Enumeration Sub-leaf
+
+ @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
+ @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)
+
+ @retval EAX RESID L2 Cache Allocation Technology information described by
+ the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.
+ @retval EBX Bit-granular map of isolation/contention of allocation units.
+ @retval ECX Reserved.
+ @retval EDX RESID L2 Cache Allocation Technology information described by
+ the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.
+
+ <b>Example usage</b>
+ @code
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;
+ UINT32 Ebx;
+ CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
+
+ AsmCpuidEx (
+ CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
+ &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
+ );
+ @endcode
+**/
+#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02
+
+/**
+ CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+ #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
+ /// using minus-one notation.
+ ///
+ UINT32 CapacityLength:5;
+ UINT32 Reserved:27;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;
+
+/**
+ CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf
+ #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+ #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 15:0] Highest COS number supported for this ResID.
+ ///
+ UINT32 HighestCosNumber:16;
+ UINT32 Reserved:16;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;
/**
@@ -2580,26 +2696,38 @@ typedef union {
///
struct {
///
- /// [Bit 0] If 1, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
+ /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
/// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
///
UINT32 Cr3Filter:1;
///
- /// [Bit 1] If 1, Indicates support of Configurable PSB and Cycle-Accurate
+ /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate
/// Mode.
///
UINT32 ConfigurablePsb:1;
///
- /// [Bit 2] If 1, Indicates support of IP Filtering, TraceStop filtering,
+ /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,
/// and preservation of Intel PT MSRs across warm reset.
///
UINT32 IpTraceStopFiltering:1;
///
- /// [Bit 3] If 1, Indicates support of MTC timing packet and suppression of
+ /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of
/// COFI-based packets.
///
UINT32 Mtc:1;
- UINT32 Reserved:28;
+ ///
+ /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set
+ /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE
+ /// can generate packets.
+ ///
+ UINT32 PTWrite:1;
+ ///
+ /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set
+ /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet
+ /// generation.
+ ///
+ UINT32 PowerEventTrace:1;
+ UINT32 Reserved:26;
} Bits;
///
/// All bit fields as a 32-bit value
@@ -2629,16 +2757,16 @@ typedef union {
///
UINT32 ToPA:1;
///
- /// [Bit 2] If 1, Indicates support of Single-Range Output scheme.
+ /// [Bit 2] If 1, indicates support of Single-Range Output scheme.
///
UINT32 SingleRangeOutput:1;
///
- /// [Bit 3] If 1, Indicates support of output to Trace Transport subsystem.
+ /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.
///
UINT32 TraceTransportSubsystem:1;
UINT32 Reserved:27;
///
- /// [Bit 31] If 1, Generated packets which contain IP payloads have LIP
+ /// [Bit 31] If 1, generated packets which contain IP payloads have LIP
/// values, which include the CS base component.
///
UINT32 LIP:1;
@@ -2738,13 +2866,14 @@ typedef union {
/**
- CPUID Time Stamp Counter Information
+ CPUID Time Stamp Counter and Nominal Core Crystal Clock Information
@note
If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core
crystal clock frequency.
- "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
+ If ECX is 0, the nominal core crystal clock frequency is not enumerated.
+ "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
The core crystal clock may differ from the reference clock, bus clock, or core
clock frequencies.
@@ -2754,15 +2883,17 @@ typedef union {
TSC/"core crystal clock" ratio
@retval EBX An unsigned integer which is the numerator of the
TSC/"core crystal clock" ratio.
- @retval ECX Reserved.
+ @retval ECX An unsigned integer which is the nominal frequency
+ of the core crystal clock in Hz.
@retval EDX Reserved.
<b>Example usage</b>
@code
UINT32 Eax;
UINT32 Ebx;
+ UINT32 Ecx;
- AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);
+ AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
@endcode
**/
#define CPUID_TIME_STAMP_COUNTER 0x15
--
1.9.5.msysgit.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 0/4] Update CPUID & MSR header files with SDM (Sep.2016)
2016-12-14 8:33 [PATCH 0/4] Update CPUID & MSR header files with SDM (Sep.2016) Hao Wu
` (3 preceding siblings ...)
2016-12-14 8:33 ` [PATCH 4/4] UefiCpuPkg/Cpuid.h: Update CPUID definitions " Hao Wu
@ 2016-12-15 18:16 ` Kinney, Michael D
4 siblings, 0 replies; 6+ messages in thread
From: Kinney, Michael D @ 2016-12-15 18:16 UTC (permalink / raw)
To: Wu, Hao A, edk2-devel@lists.01.org, Kinney, Michael D; +Cc: Fan, Jeff
Series
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Mike
> -----Original Message-----
> From: Wu, Hao A
> Sent: Wednesday, December 14, 2016 12:33 AM
> To: edk2-devel@lists.01.org
> Cc: Wu, Hao A <hao.a.wu@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>;
> Fan, Jeff <jeff.fan@intel.com>
> Subject: [PATCH 0/4] Update CPUID & MSR header files with SDM (Sep.2016)
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=176
>
> According to the latest version (Sep.'16) of Intel(R) 64 and IA-32
> Architectures Software Developer's Manual (SDM), this patch series will
> update the MSR and CPUID related definitions in .h files under
> UefiCpuPkg/Include/Register.
>
> Cc: Michael Kinney <michael.d.kinney@intel.com>
> Cc: Jeff Fan <jeff.fan@intel.com>
>
> Hao Wu (4):
> UefiCpuPkg/Include: Update MSR header files with SDM (Sep.2016)
> UefiCpuPkg/Include: Update Skylake MSR header file with SDM (Sep.2016)
> UefiCpuPkg/Include: Add Goldmont MSR header file with SDM (Sep.2016)
> UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016)
>
> UefiCpuPkg/Application/Cpuid/Cpuid.c | 115 +-
> UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 159 +-
> UefiCpuPkg/Include/Register/Cpuid.h | 363 +++-
> UefiCpuPkg/Include/Register/Msr.h | 3 +-
> UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 167 +-
> UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 43 +-
> UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 286 +--
> UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 64 +-
> UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 2515 ++++++++++++++++++++++
> UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 451 ++--
> UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 62 +-
> UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 416 ++--
> UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 340 +--
> UefiCpuPkg/Include/Register/Msr/P6Msr.h | 6 +-
> UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 146 +-
> UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 26 +-
> UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 8 +-
> UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 537 ++---
> UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 411 ++--
> UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1189 +++++++++-
> UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 2 +-
> UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 456 +---
> UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 74 +-
> UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 314 +--
> 24 files changed, 5323 insertions(+), 2830 deletions(-)
> create mode 100644 UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
>
> --
> 1.9.5.msysgit.0
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-12-15 18:16 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2016-12-14 8:33 [PATCH 0/4] Update CPUID & MSR header files with SDM (Sep.2016) Hao Wu
2016-12-14 8:33 ` [PATCH 1/4] UefiCpuPkg/Include: Update " Hao Wu
2016-12-14 8:33 ` [PATCH 2/4] UefiCpuPkg/Include: Update Skylake MSR header file " Hao Wu
2016-12-14 8:33 ` [PATCH 3/4] UefiCpuPkg/Include: Add Goldmont " Hao Wu
2016-12-14 8:33 ` [PATCH 4/4] UefiCpuPkg/Cpuid.h: Update CPUID definitions " Hao Wu
2016-12-15 18:16 ` [PATCH 0/4] Update CPUID & MSR header files " Kinney, Michael D
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