From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 32EF081C5A for ; Wed, 14 Dec 2016 00:33:39 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP; 14 Dec 2016 00:33:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,346,1477983600"; d="scan'208";a="1081627774" Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.34]) by fmsmga001.fm.intel.com with ESMTP; 14 Dec 2016 00:33:37 -0800 From: Hao Wu To: edk2-devel@lists.01.org Cc: Hao Wu , Michael Kinney , Jeff Fan Date: Wed, 14 Dec 2016 16:33:20 +0800 Message-Id: <1481704400-12044-5-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 In-Reply-To: <1481704400-12044-1-git-send-email-hao.a.wu@intel.com> References: <1481704400-12044-1-git-send-email-hao.a.wu@intel.com> Subject: [PATCH 4/4] UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016) X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Dec 2016 08:33:39 -0000 https://bugzilla.tianocore.org/show_bug.cgi?id=176 Update CPUID leaf and sub-leaf indexes and structures as described by Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, September 2016, CPUID instruction. Summary of incompatible changes: 1. Field name changes in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Bit 12 has been renamed from 'PQM' to 'RDT_M' and bit 15 has been renamed from 'PQE' to 'RDT_A'. 2. Stucture and filed name changes for 'CPUID Platform QoS Monitoring Information' related definitions Definition 'CPUID_PLATFORM_QOS_MONITORING' has been renamed to 'CPUID_INTEL_RDT_MONITORING'. Definition 'CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF'. Definition 'CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF'. 3. Stucture and filed name changes for 'CPUID Platform QoS Enforcement Information' related definitions Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION'. Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF'. Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF'. This commit also updates the relating codes in UefiCpuPkg/Application/Cpuid to reflect the changes. Cc: Michael Kinney Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu Reviewed-by: Jeff Fan --- UefiCpuPkg/Application/Cpuid/Cpuid.c | 115 +++++++---- UefiCpuPkg/Include/Register/Cpuid.h | 363 ++++++++++++++++++++++++----------- 2 files changed, 325 insertions(+), 153 deletions(-) diff --git a/UefiCpuPkg/Application/Cpuid/Cpuid.c b/UefiCpuPkg/Application/Cpuid/Cpuid.c index ac14c41..2efad68 100644 --- a/UefiCpuPkg/Application/Cpuid/Cpuid.c +++ b/UefiCpuPkg/Application/Cpuid/Cpuid.c @@ -88,13 +88,14 @@ CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = { { 0x56 , "TLB" , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" }, { 0x57 , "TLB" , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" }, { 0x59 , "TLB" , "Data TLB0: 4 KByte pages, fully associative, 16 entries" }, - { 0x5A , "TLB" , "Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries" }, + { 0x5A , "TLB" , "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" }, { 0x5B , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" }, { 0x5C , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,128 entries" }, { 0x5D , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,256 entries" }, { 0x60 , "Cache" , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" }, { 0x61 , "TLB" , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" }, - { 0x63 , "TLB" , "Data TLB: 1 GByte pages, 4-way set associative, 4 entries" }, + { 0x63 , "TLB" , "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" }, + { 0x64 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" }, { 0x66 , "Cache" , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" }, { 0x67 , "Cache" , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" }, { 0x68 , "Cache" , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" }, @@ -133,6 +134,7 @@ CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = { { 0xC1 , "STLB" , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" }, { 0xC2 , "DTLB" , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" }, { 0xC3 , "STLB" , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." }, + { 0xC4 , "DTLB" , "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" }, { 0xCA , "STLB" , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" }, { 0xD0 , "Cache" , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" }, { 0xD1 , "Cache" , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" }, @@ -604,18 +606,24 @@ CpuidStructuredExtendedFeatureFlags ( PRINT_BIT_FIELD (Ebx, EnhancedRepMovsbStosb); PRINT_BIT_FIELD (Ebx, INVPCID); PRINT_BIT_FIELD (Ebx, RTM); - PRINT_BIT_FIELD (Ebx, PQM); + PRINT_BIT_FIELD (Ebx, RDT_M); PRINT_BIT_FIELD (Ebx, DeprecateFpuCsDs); PRINT_BIT_FIELD (Ebx, MPX); - PRINT_BIT_FIELD (Ebx, PQE); + PRINT_BIT_FIELD (Ebx, RDT_A); PRINT_BIT_FIELD (Ebx, RDSEED); PRINT_BIT_FIELD (Ebx, ADX); PRINT_BIT_FIELD (Ebx, SMAP); PRINT_BIT_FIELD (Ebx, CLFLUSHOPT); + PRINT_BIT_FIELD (Ebx, CLWB); PRINT_BIT_FIELD (Ebx, IntelProcessorTrace); + PRINT_BIT_FIELD (Ebx, SHA); PRINT_BIT_FIELD (Ecx, PREFETCHWT1); + PRINT_BIT_FIELD (Ecx, UMIP); PRINT_BIT_FIELD (Ecx, PKU); PRINT_BIT_FIELD (Ecx, OSPKE); + PRINT_BIT_FIELD (Ecx, MAWAU); + PRINT_BIT_FIELD (Ecx, RDPID); + PRINT_BIT_FIELD (Ecx, SGX_LC); } } } @@ -815,78 +823,81 @@ CpuidExtendedStateMainLeaf ( } /** - Display CPUID_PLATFORM_QOS_MONITORING enumeration sub-leaf. + Display CPUID_INTEL_RDT_MONITORING enumeration sub-leaf. **/ VOID -CpuidPlatformQosMonitoringEnumerationSubLeaf ( +CpuidIntelRdtMonitoringEnumerationSubLeaf ( VOID ) { UINT32 Ebx; - CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx; + CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx; - if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) { + if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) { return; } AsmCpuidEx ( - CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF, + CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF, NULL, &Ebx, NULL, &Edx.Uint32 ); - Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF); + Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32); PRINT_VALUE (Ebx, Maximum_RMID_Range); - PRINT_BIT_FIELD (Edx, L3CacheQosEnforcement); + PRINT_BIT_FIELD (Edx, L3CacheRDT_M); } /** - Display CPUID_PLATFORM_QOS_MONITORING capability sub-leaf. + Display CPUID_INTEL_RDT_MONITORING L3 cache capability sub-leaf. **/ VOID -CpuidPlatformQosMonitoringCapabilitySubLeaf ( +CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf ( VOID ) { UINT32 Ebx; UINT32 Ecx; - CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx; + CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx; - if (CPUID_PLATFORM_QOS_MONITORING > gMaximumBasicFunction) { + if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) { return; } AsmCpuidEx ( - CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF, + CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF, NULL, &Ebx, &Ecx, &Edx.Uint32 ); - Print (L"CPUID_PLATFORM_QOS_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF); + Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32); PRINT_VALUE (Ebx, OccupancyConversionFactor); PRINT_VALUE (Ecx, Maximum_RMID_Range); PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring); + PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring); + PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring); } /** - Display CPUID_PLATFORM_QOS_ENFORCEMENT sub-leaf. + Display CPUID_INTEL_RDT_ALLOCATION L3 cache allocation technology enumeration + sub-leaf. **/ VOID -CpuidPlatformQosEnforcementResidSubLeaf ( +CpuidIntelRdtAllocationL3CacheSubLeaf ( VOID ) { - CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax; + CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax; UINT32 Ebx; - CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx; - CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx; + CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx; + CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx; AsmCpuidEx ( - CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF, + CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF, &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32 ); - Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF); + Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32); PRINT_BIT_FIELD (Eax, CapacityLength); PRINT_VALUE (Ebx, AllocationUnitBitMap); @@ -896,29 +907,56 @@ CpuidPlatformQosEnforcementResidSubLeaf ( } /** - Display CPUID_PLATFORM_QOS_ENFORCEMENT main leaf and sub-leaf. + Display CPUID_INTEL_RDT_ALLOCATION L2 cache allocation technology enumeration + sub-leaf. **/ VOID -CpuidPlatformQosEnforcementMainLeaf ( +CpuidIntelRdtAllocationL2CacheSubLeaf ( VOID ) { - CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx; + CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax; + UINT32 Ebx; + CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx; + + AsmCpuidEx ( + CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF, + &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 + ); + Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF); + Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32); + PRINT_BIT_FIELD (Eax, CapacityLength); + PRINT_VALUE (Ebx, AllocationUnitBitMap); + PRINT_BIT_FIELD (Edx, HighestCosNumber); +} + +/** + Display CPUID_INTEL_RDT_ALLOCATION main leaf and sub-leaves. + +**/ +VOID +CpuidIntelRdtAllocationMainLeaf ( + VOID + ) +{ + CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx; - if (CPUID_PLATFORM_QOS_ENFORCEMENT > gMaximumBasicFunction) { + if (CPUID_INTEL_RDT_ALLOCATION > gMaximumBasicFunction) { return; } AsmCpuidEx ( - CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF, + CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF, NULL, &Ebx.Uint32, NULL, NULL ); - Print (L"CPUID_PLATFORM_QOS_ENFORCEMENT (Leaf %08x, Sub-Leaf %08x)\n", CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF); + Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0); - PRINT_BIT_FIELD (Ebx, L3CacheQosEnforcement); + PRINT_BIT_FIELD (Ebx, L3CacheAllocation); + PRINT_BIT_FIELD (Ebx, L2CacheAllocation); - CpuidPlatformQosEnforcementResidSubLeaf (); + CpuidIntelRdtAllocationL3CacheSubLeaf (); + CpuidIntelRdtAllocationL2CacheSubLeaf (); } /** @@ -1093,6 +1131,8 @@ CpuidIntelProcessorTraceMainLeaf ( PRINT_BIT_FIELD (Ebx, ConfigurablePsb); PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering); PRINT_BIT_FIELD (Ebx, Mtc); + PRINT_BIT_FIELD (Ebx, PTWrite); + PRINT_BIT_FIELD (Ebx, PowerEventTrace); PRINT_BIT_FIELD (Ecx, RTIT); PRINT_BIT_FIELD (Ecx, ToPA); PRINT_BIT_FIELD (Ecx, SingleRangeOutput); @@ -1113,14 +1153,15 @@ CpuidTimeStampCounter ( { UINT32 Eax; UINT32 Ebx; + UINT32 Ecx; if (CPUID_TIME_STAMP_COUNTER > gMaximumBasicFunction) { return; } - AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL); + AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL); Print (L"CPUID_TIME_STAMP_COUNTER (Leaf %08x)\n", CPUID_TIME_STAMP_COUNTER); - Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, 0, 0); + Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, 0); } /** @@ -1446,9 +1487,9 @@ UefiMain ( CpuidArchitecturalPerformanceMonitoring (); CpuidExtendedTopology (); CpuidExtendedStateMainLeaf (); - CpuidPlatformQosMonitoringEnumerationSubLeaf (); - CpuidPlatformQosMonitoringCapabilitySubLeaf (); - CpuidPlatformQosEnforcementMainLeaf (); + CpuidIntelRdtMonitoringEnumerationSubLeaf (); + CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (); + CpuidIntelRdtAllocationMainLeaf (); CpuidEnumerationOfIntelSgx (); CpuidIntelProcessorTraceMainLeaf (); CpuidTimeStampCounter (); diff --git a/UefiCpuPkg/Include/Register/Cpuid.h b/UefiCpuPkg/Include/Register/Cpuid.h index 864108d..5eb9650 100644 --- a/UefiCpuPkg/Include/Register/Cpuid.h +++ b/UefiCpuPkg/Include/Register/Cpuid.h @@ -17,7 +17,7 @@ @par Specification Reference: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, - December 2015, CPUID instruction. + September 2016, CPUID instruction. **/ @@ -433,11 +433,10 @@ typedef union { /// UINT32 PGE:1; /// - /// [Bit 14] Machine Check Architecture. The Machine Check Architecture, - /// which provides a compatible mechanism for error reporting in P6 family, - /// Pentium 4, Intel Xeon processors, and future processors, is supported. - /// The MCG_CAP MSR contains feature bits describing how many banks of error - /// reporting MSRs are supported. + /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine + /// Check Architecture of reporting machine errors is supported. The MCG_CAP + /// MSR contains feature bits describing how many banks of error reporting + /// MSRs are supported. /// UINT32 MCA:1; /// @@ -634,13 +633,16 @@ typedef union { 0x56 TLB Data TLB0: 4 MByte pages, 4-way set associative, 16 entries 0x57 TLB Data TLB0: 4 KByte pages, 4-way associative, 16 entries 0x59 TLB Data TLB0: 4 KByte pages, fully associative, 16 entries - 0x5A TLB Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries + 0x5A TLB Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries 0x5B TLB Data TLB: 4 KByte and 4 MByte pages, 64 entries 0x5C TLB Data TLB: 4 KByte and 4 MByte pages,128 entries 0x5D TLB Data TLB: 4 KByte and 4 MByte pages,256 entries 0x60 Cache 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size 0x61 TLB Instruction TLB: 4 KByte pages, fully associative, 48 entries - 0x63 TLB Data TLB: 1 GByte pages, 4-way set associative, 4 entries + 0x63 TLB Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, + 32 entries and a separate array with 1 GByte pages, 4-way set associative, + 4 entries + 0x64 TLB Data TLB: 4 KByte pages, 4-way set associative, 512 entries 0x66 Cache 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size 0x67 Cache 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size 0x68 Cache 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size @@ -686,6 +688,7 @@ typedef union { 0xC2 DTLB DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries 0xC3 STLB Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries. + 0xC4 DTLB DTLB: 2M/4M Byte pages, 4-way associative, 32 entries 0xCA STLB Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries 0xD0 Cache 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size 0xD1 Cache 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size @@ -1349,10 +1352,10 @@ typedef union { /// UINT32 RTM:1; /// - /// [Bit 12] Supports Platform Quality of Service Monitoring (PQM) - /// capability if 1. + /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT) + /// Monitoring capability if 1. /// - UINT32 PQM:1; + UINT32 RDT_M:1; /// /// [Bit 13] Deprecates FPU CS and FPU DS values if 1. /// @@ -1362,10 +1365,10 @@ typedef union { /// UINT32 MPX:1; /// - /// [Bit 15] Supports Platform Quality of Service Enforcement (PQE) - /// capability if 1. + /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT) + /// Allocation capability if 1. /// - UINT32 PQE:1; + UINT32 RDT_A:1; UINT32 Reserved2:2; /// /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction. @@ -1386,13 +1389,22 @@ typedef union { /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction. /// UINT32 CLFLUSHOPT:1; - UINT32 Reserved4:1; + /// + /// [Bit 24] If 1 indicates the processor supports the CLWB instruction. + /// + UINT32 CLWB:1; /// /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace /// extensions. /// UINT32 IntelProcessorTrace:1; - UINT32 Reserved5:6; + UINT32 Reserved4:3; + /// + /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R) + /// SHA Extensions) if 1. + /// + UINT32 SHA:1; + UINT32 Reserved5:2; } Bits; /// /// All bit fields as a 32-bit value @@ -1414,7 +1426,11 @@ typedef union { /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction. /// UINT32 PREFETCHWT1:1; - UINT32 Reserved1:2; + UINT32 Reserved1:1; + /// + /// [Bit 2] Supports user-mode instruction prevention if 1. + /// + UINT32 UMIP:1; /// /// [Bit 3] Supports protection keys for user-mode pages if 1. /// @@ -1424,7 +1440,22 @@ typedef union { /// RDPKRU/WRPKRU instructions). /// UINT32 OSPKE:1; - UINT32 Reserved2:27; + UINT32 Reserved2:12; + /// + /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions + /// in 64-bit mode. + /// + UINT32 MAWAU:5; + /// + /// [Bit 22] Supports Read Processor ID if 1. + /// + UINT32 RDPID:1; + UINT32 Reserved3:7; + /// + /// [Bit 30] Supports SGX Launch Configuration if 1. + /// + UINT32 SGX_LC:1; + UINT32 Reserved4:1; } Bits; /// /// All bit fields as a 32-bit value @@ -1756,7 +1787,7 @@ typedef union { enabled. @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the XSAVE/XRSTOR save area required by all supported - features in the processor, i.e all the valid bit fields in XCR0. + features in the processor, i.e., all the valid bit fields in XCR0. @retval EDX Reports the supported bits of the upper 32 bits of XCR0. XCR0[n+32] can be set to 1 only if EDX[n] is 1. @@ -1991,45 +2022,46 @@ typedef union { /** - CPUID Platform QoS Monitoring Information + CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information - @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F) - @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00). - CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01). + @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) + @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00). + CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01). **/ -#define CPUID_PLATFORM_QOS_MONITORING 0x0F +#define CPUID_INTEL_RDT_MONITORING 0x0F /** - CPUID Platform QoS Monitoring Information Enumeration Sub-leaf + CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information + Enumeration Sub-leaf - @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F) - @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00) + @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) + @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00) @retval EAX Reserved. @retval EBX Maximum range (zero-based) of RMID within this physical processor of all types. @retval ECX Reserved. - @retval EDX L3 Cache QoS Monitoring Information Enumeration described by the - type CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX. + @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by + the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX. Example usage @code UINT32 Ebx; - CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx; + CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx; AsmCpuidEx ( - CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF, + CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF, NULL, &Ebx, NULL, &Edx.Uint32 ); @endcode **/ -#define CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF 0x00 +#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00 /** - CPUID Platform QoS Monitoring Information EDX for CPUID leaf - #CPUID_PLATFORM_QOS_MONITORING, sub-leaf - #CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF. + CPUID Intel RDT Monitoring Information EDX for CPUID leaf + #CPUID_INTEL_RDT_MONITORING, sub-leaf + #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF. **/ typedef union { /// @@ -2038,47 +2070,47 @@ typedef union { struct { UINT32 Reserved1:1; /// - /// [Bit 1] Supports L3 Cache QoS Monitoring if 1. + /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1. /// - UINT32 L3CacheQosEnforcement:1; + UINT32 L3CacheRDT_M:1; UINT32 Reserved2:30; } Bits; /// /// All bit fields as a 32-bit value /// UINT32 Uint32; -} CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX; +} CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX; /** - CPUID Platform QoS Monitoring Information Capability Sub-leaf + CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf - @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F) - @param ECX CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01) + @param EAX CPUID_INTEL_RDT_MONITORING (0x0F) + @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01) @retval EAX Reserved. @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes). @retval ECX Maximum range (zero-based) of RMID of this resource type. - @retval EDX L3 Cache QoS Monitoring Capability information described by the - type CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX. + @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the + type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX. Example usage @code - UINT32 Ebx; - UINT32 Ecx; - CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx; + UINT32 Ebx; + UINT32 Ecx; + CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx; AsmCpuidEx ( - CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF, + CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF, NULL, &Ebx, &Ecx, &Edx.Uint32 ); @endcode **/ -#define CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF 0x01 +#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01 /** - CPUID Platform QoS Monitoring Information Capability EDX for CPUID leaf - #CPUID_PLATFORM_QOS_MONITORING, sub-leaf - #CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF. + CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf + #CPUID_INTEL_RDT_MONITORING, sub-leaf + #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF. **/ typedef union { /// @@ -2089,53 +2121,61 @@ typedef union { /// [Bit 0] Supports L3 occupancy monitoring if 1. /// UINT32 L3CacheOccupancyMonitoring:1; - UINT32 Reserved:31; + /// + /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1. + /// + UINT32 L3CacheTotalBandwidthMonitoring:1; + /// + /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1. + /// + UINT32 L3CacheLocalBandwidthMonitoring:1; + UINT32 Reserved:29; } Bits; /// /// All bit fields as a 32-bit value /// UINT32 Uint32; -} CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX; +} CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX; /** - CPUID Platform QoS Enforcement Information + CPUID Intel Resource Director Technology (Intel RDT) Allocation Information - @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10). - @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00). - CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x01). - Additional sub leafs 1..n based in RESID from sub leaf 0x00. + @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10). + @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00). + CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01). + CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02). **/ -#define CPUID_PLATFORM_QOS_ENFORCEMENT 0x10 +#define CPUID_INTEL_RDT_ALLOCATION 0x10 /** - CPUID Platform QoS Enforcement Information + Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf - @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10) - @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00). + @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) + @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00). @retval EAX Reserved. - @retval EBX L3 Cache QoS Enforcement information described by the - type CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX. + @retval EBX L3 and L2 Cache Allocation Technology information described by + the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX. @retval ECX Reserved. @retval EDX Reserved. Example usage @code - CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx; + CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx; AsmCpuidEx ( - CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF, + CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF, NULL, &Ebx.Uint32, NULL, NULL ); @endcode **/ -#define CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF 0x00 +#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00 /** - CPUID Platform QoS Enforcement Information EBX for CPUID leaf - #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf - #CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF. + CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF. **/ typedef union { /// @@ -2144,52 +2184,55 @@ typedef union { struct { UINT32 Reserved1:1; /// - /// [Bit 1] Supports L3 Cache QoS Enforcement if 1. + /// [Bit 1] Supports L3 Cache Allocation Technology if 1. /// - UINT32 L3CacheQosEnforcement:1; - UINT32 Reserved2:30; + UINT32 L3CacheAllocation:1; + /// + /// [Bit 2] Supports L2 Cache Allocation Technology if 1. + /// + UINT32 L2CacheAllocation:1; + UINT32 Reserved2:29; } Bits; /// /// All bit fields as a 32-bit value /// UINT32 Uint32; -} CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX; +} CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX; /** - CPUID Platform QoS Enforcement Information + L3 Cache Allocation Technology Enumeration Sub-leaf - @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10) - @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x00) - Additional sub leafs 1..n based in RESID from sub leaf 0x00. + @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) + @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01) - @retval EAX RESID L3 Cache3 QoS Enforcement information described by the - type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX. + @retval EAX RESID L3 Cache Allocation Technology information described by + the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX. @retval EBX Bit-granular map of isolation/contention of allocation units. - @retval ECX RESID L3 Cache3 QoS Enforcement information described by the - type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX. - @retval EDX RESID L3 Cache3 QoS Enforcement information described by the - type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX. + @retval ECX RESID L3 Cache Allocation Technology information described by + the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX. + @retval EDX RESID L3 Cache Allocation Technology information described by + the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX. Example usage @code - CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax; + CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax; UINT32 Ebx; - CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx; - CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx; + CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx; + CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx; AsmCpuidEx ( - CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF, + CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF, &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32 ); @endcode **/ -#define CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF 0x01 +#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01 /** - CPUID Platform QoS Enforcement Information EAX for CPUID leaf - #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf - #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF. + CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. **/ typedef union { /// @@ -2197,21 +2240,22 @@ typedef union { /// struct { /// - /// [Bits 3:0] Length of the capacity bit mask for the corresponding ResID. + /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID + /// using minus-one notation. /// - UINT32 CapacityLength:4; - UINT32 Reserved:28; + UINT32 CapacityLength:5; + UINT32 Reserved:27; } Bits; /// /// All bit fields as a 32-bit value /// UINT32 Uint32; -} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX; +} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX; /** - CPUID Platform QoS Enforcement Information ECX for CPUID leaf - #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf - #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF. + CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. **/ typedef union { /// @@ -2233,12 +2277,12 @@ typedef union { /// All bit fields as a 32-bit value /// UINT32 Uint32; -} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX; +} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX; /** - CPUID Platform QoS Enforcement Information EDX for CPUID leaf - #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf - #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF. + CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF. **/ typedef union { /// @@ -2255,7 +2299,79 @@ typedef union { /// All bit fields as a 32-bit value /// UINT32 Uint32; -} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX; +} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX; + +/** + L2 Cache Allocation Technology Enumeration Sub-leaf + + @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10) + @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02) + + @retval EAX RESID L2 Cache Allocation Technology information described by + the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX. + @retval EBX Bit-granular map of isolation/contention of allocation units. + @retval ECX Reserved. + @retval EDX RESID L2 Cache Allocation Technology information described by + the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX. + + Example usage + @code + CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax; + UINT32 Ebx; + CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx; + + AsmCpuidEx ( + CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF, + &Eax.Uint32, &Ebx, NULL, &Edx.Uint32 + ); + @endcode +**/ +#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02 + +/** + CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID + /// using minus-one notation. + /// + UINT32 CapacityLength:5; + UINT32 Reserved:27; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX; + +/** + CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf + #CPUID_INTEL_RDT_ALLOCATION, sub-leaf + #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 15:0] Highest COS number supported for this ResID. + /// + UINT32 HighestCosNumber:16; + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX; /** @@ -2580,26 +2696,38 @@ typedef union { /// struct { /// - /// [Bit 0] If 1, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, + /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, /// and that IA32_RTIT_CR3_MATCH MSR can be accessed. /// UINT32 Cr3Filter:1; /// - /// [Bit 1] If 1, Indicates support of Configurable PSB and Cycle-Accurate + /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate /// Mode. /// UINT32 ConfigurablePsb:1; /// - /// [Bit 2] If 1, Indicates support of IP Filtering, TraceStop filtering, + /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering, /// and preservation of Intel PT MSRs across warm reset. /// UINT32 IpTraceStopFiltering:1; /// - /// [Bit 3] If 1, Indicates support of MTC timing packet and suppression of + /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of /// COFI-based packets. /// UINT32 Mtc:1; - UINT32 Reserved:28; + /// + /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set + /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE + /// can generate packets. + /// + UINT32 PTWrite:1; + /// + /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set + /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet + /// generation. + /// + UINT32 PowerEventTrace:1; + UINT32 Reserved:26; } Bits; /// /// All bit fields as a 32-bit value @@ -2629,16 +2757,16 @@ typedef union { /// UINT32 ToPA:1; /// - /// [Bit 2] If 1, Indicates support of Single-Range Output scheme. + /// [Bit 2] If 1, indicates support of Single-Range Output scheme. /// UINT32 SingleRangeOutput:1; /// - /// [Bit 3] If 1, Indicates support of output to Trace Transport subsystem. + /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem. /// UINT32 TraceTransportSubsystem:1; UINT32 Reserved:27; /// - /// [Bit 31] If 1, Generated packets which contain IP payloads have LIP + /// [Bit 31] If 1, generated packets which contain IP payloads have LIP /// values, which include the CS base component. /// UINT32 LIP:1; @@ -2738,13 +2866,14 @@ typedef union { /** - CPUID Time Stamp Counter Information + CPUID Time Stamp Counter and Nominal Core Crystal Clock Information @note If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated. EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core crystal clock frequency. - "TSC frequency" = "core crystal clock frequency" * EBX/EAX. + If ECX is 0, the nominal core crystal clock frequency is not enumerated. + "TSC frequency" = "core crystal clock frequency" * EBX/EAX. The core crystal clock may differ from the reference clock, bus clock, or core clock frequencies. @@ -2754,15 +2883,17 @@ typedef union { TSC/"core crystal clock" ratio @retval EBX An unsigned integer which is the numerator of the TSC/"core crystal clock" ratio. - @retval ECX Reserved. + @retval ECX An unsigned integer which is the nominal frequency + of the core crystal clock in Hz. @retval EDX Reserved. Example usage @code UINT32 Eax; UINT32 Ebx; + UINT32 Ecx; - AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL); + AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL); @endcode **/ #define CPUID_TIME_STAMP_COUNTER 0x15 -- 1.9.5.msysgit.0