From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6600F82136 for ; Mon, 19 Dec 2016 17:48:01 -0800 (PST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP; 19 Dec 2016 17:48:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,376,1477983600"; d="scan'208";a="44971216" Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.13]) by fmsmga006.fm.intel.com with ESMTP; 19 Dec 2016 17:47:59 -0800 From: Hao Wu To: edk2-devel@lists.01.org Cc: Hao Wu , Jeff Fan , Michael Kinney Date: Tue, 20 Dec 2016 09:47:57 +0800 Message-Id: <1482198477-13620-1-git-send-email-hao.a.wu@intel.com> X-Mailer: git-send-email 1.9.5.msysgit.0 MIME-Version: 1.0 Subject: [PATCH] UefiCpuPkg/ArchitecturalMsr.h: Remove non-Ascii characters X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Dec 2016 01:48:01 -0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Jeff Fan Cc: Michael Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu --- UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h index 633e54d..4f9c103 100644 --- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h +++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h @@ -4014,7 +4014,7 @@ typedef union { /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used /// in VMX operation. If the processor supports Intel PT but does not allow /// it to be used in VMX operation, execution of VMXON clears - /// IA32_RTIT_CTL.TraceEn (see “VMXON—Enter VMX Operation” in Chapter 30); + /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30); /// any attempt to set that bit while in VMX operation (including VMX root /// operation) using the WRMSR instruction causes a general-protection /// exception. -- 1.9.5.msysgit.0