* [PATCH] FVP: ACPI Add iort and GICv3 ITS support
@ 2016-12-21 9:43 Dennis Chen
0 siblings, 0 replies; only message in thread
From: Dennis Chen @ 2016-12-21 9:43 UTC (permalink / raw)
To: linaro-uefi
Cc: nd, edk2-devel, Dennis Chen, Leif Lindholm, Ard Biesheuvel,
Lorenzo Pieralisi, Steve Capper
Since ARM VExpress FVP platform will support some PCIe devices
(e.g, SMMU Test Engine) behind the PCIe Root Complex and SMMUv3 which
can generate PCI ITS-MSI/memory transaction to the core. Moreover, the
IORT based SMMU patch has been merged into the linux kernel, in order
to ease the testing/verification effort of those features, we need to
integrate those ACPI tables (mcfg, iort...) into the FVP UEFI binary.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dennis Chen <dennis.chen@arm.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Steve Capper <steve.capper@arm.com>
---
Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf | 4 +
Platforms/ARM/VExpress/AcpiTables/Madt.aslc | 54 ++++++------
Platforms/ARM/VExpress/AcpiTables/iort-smmuv3.asl | 89 ++++++++++++++++++++
Platforms/ARM/VExpress/AcpiTables/mcfg.asl | 25 ++++++
Platforms/ARM/VExpress/AcpiTables/ssdt.asl | 98 ++++++++++++++++++++++
Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc | 1 +
6 files changed, 247 insertions(+), 24 deletions(-)
create mode 100644 Platforms/ARM/VExpress/AcpiTables/iort-smmuv3.asl
create mode 100644 Platforms/ARM/VExpress/AcpiTables/mcfg.asl
create mode 100644 Platforms/ARM/VExpress/AcpiTables/ssdt.asl
diff --git a/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf b/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf
index 59d3238..000e83d 100644
--- a/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf
+++ b/Platforms/ARM/VExpress/AcpiTables/AcpiTables.inf
@@ -27,6 +27,9 @@
Fadt.aslc
Gtdt.aslc
Madt.aslc
+ mcfg.asl
+ ssdt.asl
+ iort-smmuv3.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -41,3 +44,4 @@
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdGicItsBase
diff --git a/Platforms/ARM/VExpress/AcpiTables/Madt.aslc b/Platforms/ARM/VExpress/AcpiTables/Madt.aslc
index bf90a9f..d2d9d9a 100644
--- a/Platforms/ARM/VExpress/AcpiTables/Madt.aslc
+++ b/Platforms/ARM/VExpress/AcpiTables/Madt.aslc
@@ -30,8 +30,15 @@ typedef struct {
EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[8];
EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
EFI_ACPI_6_1_GICR_STRUCTURE Gicr;
+ EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicIts;
} FVP_MULTIPLE_APIC_DESCRIPTION_TABLE;
+#define FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr) \
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT( \
+ GicId, AcpiCpuUid, Mpidr, \
+ EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),\
+ 0x2C02F000, 0x2C010000, 0x19, 0, 0)
+
#pragma pack ()
FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
@@ -47,33 +54,22 @@ FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
0, // LocalApicAddress
0, // Flags
},
+
+ /* Gic Interfaces array */
{
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 1, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 2, 2, GET_MPID(0, 2), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 3, 3, GET_MPID(0, 3), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 4, 4, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 5, 5, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 6, 6, GET_MPID(1, 2), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 7, 7, GET_MPID(1, 3), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
+ FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(0, 0, GET_MPID(0, 0)),
+ FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(1, 1, GET_MPID(0, 1)),
+ FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(2, 2, GET_MPID(0, 2)),
+ FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(3, 3, GET_MPID(0, 3)),
+ FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(4, 4, GET_MPID(1, 0)),
+ FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(5, 5, GET_MPID(1, 1)),
+ FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(6, 6, GET_MPID(1, 2)),
+ FVP_EFI_ACPI_6_0_GICC_STRUCTURE_INIT(7, 7, GET_MPID(1, 3)),
},
+
+ /* GIC Distributor */
EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 3),
+
/* GIC Redistributor */
{
EFI_ACPI_6_1_GICR, // UINT8 Type
@@ -81,6 +77,16 @@ FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
EFI_ACPI_RESERVED_WORD, // UINT16 Reserved
FixedPcdGet64 (PcdGicRedistributorsBase), // UINT64 DiscoveryRangeBaseAddress
0x00200000, // UINT32 DiscoveryRangeLength
+ },
+
+ /* GIC ITS */
+ {
+ EFI_ACPI_6_1_GIC_ITS, // UINT8 Type
+ sizeof(EFI_ACPI_6_1_GIC_ITS_STRUCTURE), // UINT8 Length
+ EFI_ACPI_RESERVED_WORD, // UINT16 Reserved
+ 0x00000000, // UINT32 GicItsId
+ FixedPcdGet64 (PcdGicItsBase), // UINT64 GicItsBaseAddress
+ EFI_ACPI_RESERVED_DWORD, // UINT32 Reserved
}
};
diff --git a/Platforms/ARM/VExpress/AcpiTables/iort-smmuv3.asl b/Platforms/ARM/VExpress/AcpiTables/iort-smmuv3.asl
new file mode 100644
index 0000000..6caee57
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/iort-smmuv3.asl
@@ -0,0 +1,89 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20151124-64
+ * Copyright (c) 2000 - 2015 Intel Corporation
+ *
+ * Template for [IORT] ACPI Table (static data table)
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+[0004] Signature : "IORT" [IO Remapping Table]
+[0004] Table Length : 0000029e
+[0001] Revision : 00
+[0001] Checksum : BC
+[0006] Oem ID : "ARM "
+[0008] Oem Table ID : "VExpress"
+[0004] Oem Revision : 00000000
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20150410
+
+[0004] Node Count : 00000008
+[0004] Node Offset : 00000044
+[0004] Reserved : 00000000
+[0004] Optional Padding : 00 00 00 00
+
+/* ITS Group : 24-byte */
+[0001] Type : 00
+[0002] Length : 0018
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000000
+[0004] Mapping Offset : 00000000
+
+[0004] ItsCount : 00000001
+[0004] Identifiers : 00000000
+
+/* SMMUv3 : 80-byte */
+[0001] Type : 04
+[0002] Length : 0050
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 0000003C
+
+[0008] Base Address : 000000002b400000
+[0004] Flags (decoded below) : 00000001
+ COHACC Override : 1
+ HTTU Override : 0
+[0004] Reserved : 00000000
+[0008] VATOS Address : 0000000000000000
+[0004] Model : 00000000
+[0004] Event GSIV : 6a/*4a*/
+[0004] PRI GSIV : 6b/*4b*/
+[0004] GERR GSIV : 6f/*4f*/
+[0004] Sync GSIV : 6d/*4d*/
+[0004] Input base : 00000000
+[0004] ID Count : 0000ffff
+[0004] Output Base : 00000000
+[0004] Output Reference : 00000034 /* ITS Group node offset */
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
+/* RC 0 : 52-byte */
+[0001] Type : 02
+[0002] Length : 0034
+[0001] Revision : 00
+[0004] Reserved : 00000000
+[0004] Mapping Count : 00000001
+[0004] Mapping Offset : 00000020
+
+[0008] Memory Properties : [IORT Memory Access Properties]
+[0004] Cache Coherency : 00000001
+[0001] Hints (decoded below) : 00
+ Transient : 0
+ Write Allocate : 0
+ Read Allocate : 0
+ Override : 0
+[0002] Reserved : 0000
+[0001] Memory Flags (decoded below) : 00
+ Coherency : 0
+ Device Attribute : 0
+[0004] ATS Attribute : 00000000
+[0004] PCI Segment Number : 00000000
+
+[0004] Input base : 00000000
+[0004] ID Count : 0000ffff
+[0004] Output Base : 00000000
+[0004] Output Reference : 0000004C
+[0004] Flags (decoded below) : 00000000
+ Single Mapping : 0
+
diff --git a/Platforms/ARM/VExpress/AcpiTables/mcfg.asl b/Platforms/ARM/VExpress/AcpiTables/mcfg.asl
new file mode 100644
index 0000000..caa2b38
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/mcfg.asl
@@ -0,0 +1,25 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20160212-64
+ * Copyright (c) 2000 - 2016 Intel Corporation
+ *
+ * Template for [MCFG] ACPI Table (static data table)
+ * Format: [ByteLength] FieldName : HexFieldValue
+ */
+[0004] Signature : "MCFG" [Memory Mapped Configuration table]
+[0004] Table Length : 0000003C
+[0001] Revision : 01
+[0001] Checksum : 19
+[0006] Oem ID : "INTEL "
+[0008] Oem Table ID : "TEMPLATE"
+[0004] Oem Revision : 00000001
+[0004] Asl Compiler ID : "INTL"
+[0004] Asl Compiler Revision : 20100528
+
+[0008] Reserved : 0000000000000000
+
+[0008] Base Address : 0000000040000000
+[0002] Segment Group Number : 0000
+[0001] Start Bus Number : 00
+[0001] End Bus Number : 01
+[0004] Reserved : 00000000
diff --git a/Platforms/ARM/VExpress/AcpiTables/ssdt.asl b/Platforms/ARM/VExpress/AcpiTables/ssdt.asl
new file mode 100644
index 0000000..08c7e7b
--- /dev/null
+++ b/Platforms/ARM/VExpress/AcpiTables/ssdt.asl
@@ -0,0 +1,98 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20141107-64 [Feb 4 2015]
+ * Copyright (c) 2000 - 2015 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of ssdt.aml, Tue Aug 9 10:17:31 2016
+ *
+ * Original Table Header:
+ * Signature "SSDT"
+ * Length 0x00000168 (360)
+ * Revision 0x01
+ * Checksum 0x42
+ * OEM ID "ARMLTD"
+ * OEM Table ID "ARM-JUNO"
+ * OEM Revision 0x00000000 (0)
+ * Compiler ID "INTL"
+ * Compiler Version 0x20141107 (538185991)
+ */
+DefinitionBlock ("ssdt.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", 0x00000000)
+{
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, Zero) // _SEG: PCI Segment
+ Name (_BBN, Zero) // _BBN: BIOS Bus Number
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Device (RP0)
+ {
+ Name (_ADR, 0xF0000000) // _ADR: Address
+ }
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0001, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0002, // Length
+ ,, )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x50000000, // Range Minimum
+ 0x5FFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x10000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */
+ }
+
+ Name (SUPP, Zero)
+ Name (CTRL, Zero)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */
+ CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ If (((SUPP & 0x16) != 0x16))
+ {
+ CTRL &= 0x1E
+ }
+
+ CTRL &= 0x1D
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != CTRL))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = CTRL /* \_SB_.PCI0.CTRL */
+ Return (Arg3)
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ Return (Arg3)
+ }
+ }
+ }
+ }
+}
+
diff --git a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
index cf4b803..1d4db81 100644
--- a/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
+++ b/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
@@ -153,6 +153,7 @@
gArmTokenSpaceGuid.PcdGicDistributorBase|0x2f000000
gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x2f100000
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000
+ gArmTokenSpaceGuid.PcdGicItsBase|0x2f020000
#
# ARM OS Loader
--
2.7.4
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