From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5C42281843 for ; Tue, 3 Jan 2017 17:30:10 -0800 (PST) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP; 03 Jan 2017 17:30:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,457,1477983600"; d="scan'208";a="49224338" Received: from hmoustaf-mobl3.amr.corp.intel.com (HELO localhost) ([10.252.130.178]) by fmsmga005.fm.intel.com with ESMTP; 03 Jan 2017 17:30:09 -0800 MIME-Version: 1.0 To: Laszlo Ersek , "edk2-devel-01" Message-ID: <148349340944.16413.4237312013765520247@jljusten-ivb> From: Jordan Justen In-Reply-To: <20161202104844.6093-1-lersek@redhat.com> References: <20161202104844.6093-1-lersek@redhat.com> User-Agent: alot/0.3.7 Date: Tue, 03 Jan 2017 17:30:09 -0800 Subject: Re: [PATCH] OvmfPkg/SmmControl2Dxe: correct PCI_CONFIG_READ_WRITE in S3 boot script X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2017 01:30:10 -0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On 2016-12-02 02:48:44, Laszlo Ersek wrote: > EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE expects the PCI address to > access in UEFI encoding, not in edk2/PciLib encoding. Convert the > ICH9_GEN_PMCON_1 register's address to UEFI representation before storing > it in the boot script. > = > Cc: Jordan Justen > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Laszlo Ersek > --- > OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c | 32 +++++++++++++++++++++++++++= ++++- > 1 file changed, 31 insertions(+), 1 deletion(-) > = > diff --git a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c b/OvmfPkg/SmmControl= 2Dxe/SmmControl2Dxe.c > index c5e5ed02f5ad..3694282c82ad 100644 > --- a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c > +++ b/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c > @@ -33,6 +33,7 @@ > #include > #include > #include > +#include > #include > #include > = > @@ -307,6 +308,33 @@ FatalError: > } > = > /** > + Convert a PCI address originally composed with PCI_LIB_ADDRESS() to > + EFI_PCI_ADDRESS() representation (see Table 111. "PCI Configuration Ad= dress" > + in UEFI-2.6). > + > + @param[in] PciLibAddress A PCI address originally composed with > + PCI_LIB_ADDRESS(). > + > + @return The converted address suitable for consumers that expect > + EFI_PCI_ADDRESS() representation. > +**/ > +STATIC > +UINT64 > +ConvertPciLibToEfiPciAddress ( > + IN UINT32 PciLibAddress > + ) > +{ > + UINT32 Bus, Device, Function, Register; > + > + Register =3D BitFieldRead32 (PciLibAddress, 0, 11); > + Function =3D BitFieldRead32 (PciLibAddress, 12, 14); > + Device =3D BitFieldRead32 (PciLibAddress, 15, 19); > + Bus =3D BitFieldRead32 (PciLibAddress, 20, 27); > + > + return EFI_PCI_ADDRESS (Bus, Device, Function, Register); > +} > + > +/** > Notification callback for S3SaveState installation. > = > @param[in] Event Event whose notification function is being invoked. > @@ -362,7 +390,9 @@ OnS3SaveStateInstalled ( > S3SaveState, > EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE, > EfiBootScriptWidthUint16, > - (UINT64)POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCO= N_1), > + ConvertPciLibToEfiPciAddress ( > + POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1) I think we should just add a EFI_POWER_MGMT_REGISTER_Q35 macro. -Jordan > + ), > &GenPmCon1OrMask, > &GenPmCon1AndMask > ); > -- = > 2.9.2 >=20