From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7F5A681935 for ; Mon, 9 Jan 2017 10:40:52 -0800 (PST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP; 09 Jan 2017 10:40:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,340,1477983600"; d="scan'208";a="51823326" Received: from bpbrunin-mobl.amr.corp.intel.com (HELO localhost) ([10.252.133.160]) by fmsmga006.fm.intel.com with ESMTP; 09 Jan 2017 10:40:51 -0800 MIME-Version: 1.0 To: Laszlo Ersek , "edk2-devel-01" Message-ID: <148398725167.30686.8067182900377459343@jljusten-ivb> From: Jordan Justen In-Reply-To: <20170106172847.943-1-lersek@redhat.com> Cc: "Jiewen Yao" References: <20170106172847.943-1-lersek@redhat.com> User-Agent: alot/0.3.7 Date: Mon, 09 Jan 2017 10:40:51 -0800 Subject: Re: [PATCH v2] OvmfPkg/SmmControl2Dxe: correct PCI_CONFIG_READ_WRITE in S3 boot script X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Jan 2017 18:40:52 -0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jordan Justen On 2017-01-06 09:28:47, Laszlo Ersek wrote: > EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE expects the PCI address to > access in UEFI encoding, not in edk2/PciLib encoding. > = > Introduce the POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS() macro, and with > it, store the ICH9_GEN_PMCON_1 register's address to the boot script in > UEFI representation. > = > Cc: Jiewen Yao > Cc: Jordan Justen > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Laszlo Ersek > --- > = > Notes: > v2: > - replace ConvertPciLibToEfiPciAddress() with > POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS() [Jordan, Jiewen] > = > OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 6 ++++++ > OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c | 5 ++++- > 2 files changed, 10 insertions(+), 1 deletion(-) > = > diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Incl= ude/IndustryStandard/Q35MchIch9.h > index 4dc2c39901c1..f480455ae432 100644 > --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h > +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h > @@ -19,6 +19,9 @@ > #define __Q35_MCH_ICH9_H__ > = > #include > +#include > +#include > +#include > = > // > // Host Bridge Device ID (DID) value for Q35/MCH > @@ -75,6 +78,9 @@ > #define POWER_MGMT_REGISTER_Q35(Offset) \ > PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset)) > = > +#define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \ > + EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset)) > + > #define ICH9_PMBASE 0x40 > #define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT= 11 | \ > BIT10 | BIT9 | BIT8 | BIT7) > diff --git a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c b/OvmfPkg/SmmControl= 2Dxe/SmmControl2Dxe.c > index 82549b0a7e35..6c03e17a3a8d 100644 > --- a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c > +++ b/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c > @@ -311,6 +311,7 @@ OnS3SaveStateInstalled ( > EFI_STATUS Status; > EFI_S3_SAVE_STATE_PROTOCOL *S3SaveState; > UINT32 SmiEnOrMask, SmiEnAndMask; > + UINT64 GenPmCon1Address; > UINT16 GenPmCon1OrMask, GenPmCon1AndMask; > = > ASSERT (Event =3D=3D mS3SaveStateInstalled); > @@ -342,13 +343,15 @@ OnS3SaveStateInstalled ( > CpuDeadLoop (); > } > = > + GenPmCon1Address =3D POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS ( > + ICH9_GEN_PMCON_1); > GenPmCon1OrMask =3D ICH9_GEN_PMCON_1_SMI_LOCK; > GenPmCon1AndMask =3D MAX_UINT16; > Status =3D S3SaveState->Write ( > S3SaveState, > EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE, > EfiBootScriptWidthUint16, > - (UINT64)POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCO= N_1), > + GenPmCon1Address, > &GenPmCon1OrMask, > &GenPmCon1AndMask > ); > -- = > 2.9.3 >=20