From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x232.google.com (mail-wm0-x232.google.com [IPv6:2a00:1450:400c:c09::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9547281CAC for ; Fri, 20 Jan 2017 09:05:54 -0800 (PST) Received: by mail-wm0-x232.google.com with SMTP id r144so53563692wme.1 for ; Fri, 20 Jan 2017 09:05:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=HFEXlMQnyrpRDarC8OOYIkUk6iVcoq4hCfRjD+pKvGg=; b=Afa29pL+LOCBscrVsyk9htfdFKugRMBcsM1atJeNCt4TRaAy59SPORNezj9gzR1uEJ tLN1B2q186IuWjpSpyEAT5Qj5NgnCMTU9VcNXPQ+9go8moJt3vKVXDQH8xE5Je7d+86/ xsQc86fZuzLxXlV1TzqoibWd0plFqEo9pSr1g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=HFEXlMQnyrpRDarC8OOYIkUk6iVcoq4hCfRjD+pKvGg=; b=fyicLoeL5i2JVDLYY/B22r92Bsq2em6vTtFIDJcdt5bQxpt/QxoCnxBgW/twWoZAHe WuOjJzYzlr6fxRoYrevu12sEUyb6WVlfMlvoifLIPl9ST0t/VzHeEbqNbuQTnL4PqFYP h3mdDDjMqHc51BtmDAZpQNHCylsAdIlGaznyMrcnDrM2vuqR9vsRmFcddMeOsJkFn6OE e39qURd2gfOkJl23SD/P04czEhackePH0Is8SvaMbHo6KNpRpKowHxyNQWQOvgFOpJmQ V5dt3zXYWCaJ6IAUb0NX0k0Bf9WcXc4eXA2yIBVSqqSVPbljCSq9HeQJAl3dHoLFliCR r5BA== X-Gm-Message-State: AIkVDXINPQyFyi1iFrW5BRdikSQD/gMzMOdaWPjp89zKmmX8MgWSakBLft4y0lslVfaGlLJ2 X-Received: by 10.28.44.66 with SMTP id s63mr3972208wms.77.1484931952761; Fri, 20 Jan 2017 09:05:52 -0800 (PST) Received: from localhost.localdomain ([160.168.254.151]) by smtp.gmail.com with ESMTPSA id w17sm605467wra.28.2017.01.20.09.05.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Jan 2017 09:05:52 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, lersek@redhat.com, heyi.guo@linaro.org, ashedel@microsoft.com, Ard Biesheuvel Date: Fri, 20 Jan 2017 17:05:46 +0000 Message-Id: <1484931946-11648-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Subject: [PATCH] ArmPkg/ArmMmuLib: Revert "use a pool allocation for the root table" X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2017 17:05:54 -0000 This reverts commit d32702d2c2aa23e828363a7f88829b78ce36c3af. Using a pool allocation for the root translation table seemed like a good idea at the time, but as it turns out, such allocations are handled in a way that makes them unsuitable for this purpose: they are backed by HOBs that don't remain in the same place during the various PI phase changes, which means the address programmed into the TTBR register is no longer valid, and may refer to memory that is reported as available to the OS. So switch back to using a page based allocation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 29 ++++---------------- 1 file changed, 6 insertions(+), 23 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index c78297084207..540069a59b2e 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -553,12 +553,10 @@ ArmConfigureMmu ( ) { VOID* TranslationTable; - VOID* TranslationTableBuffer; UINT32 TranslationTableAttribute; UINT64 MaxAddress; UINTN T0SZ; UINTN RootTableEntryCount; - UINTN RootTableEntrySize; UINT64 TCR; RETURN_STATUS Status; @@ -643,19 +641,8 @@ ArmConfigureMmu ( // Set TCR ArmSetTCR (TCR); - // Allocate pages for translation table. Pool allocations are 8 byte aligned, - // but we may require a higher alignment based on the size of the root table. - RootTableEntrySize = RootTableEntryCount * sizeof(UINT64); - if (RootTableEntrySize < EFI_PAGE_SIZE / 2) { - TranslationTableBuffer = AllocatePool (2 * RootTableEntrySize - 8); - // - // Naturally align the root table. Preserves possible NULL value - // - TranslationTable = (VOID *)((UINTN)(TranslationTableBuffer - 1) | (RootTableEntrySize - 1)) + 1; - } else { - TranslationTable = AllocatePages (1); - TranslationTableBuffer = NULL; - } + // Allocate pages for translation table + TranslationTable = AllocatePages (1); if (TranslationTable == NULL) { return RETURN_OUT_OF_RESOURCES; } @@ -669,10 +656,10 @@ ArmConfigureMmu ( } if (TranslationTableSize != NULL) { - *TranslationTableSize = RootTableEntrySize; + *TranslationTableSize = RootTableEntryCount * sizeof(UINT64); } - ZeroMem (TranslationTable, RootTableEntrySize); + ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs ArmDisableMmu (); @@ -689,7 +676,7 @@ ArmConfigureMmu ( DEBUG_CODE_BEGIN (); // Find the memory attribute for the Translation Table if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase && - (UINTN)TranslationTable + RootTableEntrySize <= MemoryTable->PhysicalBase + + (UINTN)TranslationTable + EFI_PAGE_SIZE <= MemoryTable->PhysicalBase + MemoryTable->Length) { TranslationTableAttribute = MemoryTable->Attributes; } @@ -718,11 +705,7 @@ ArmConfigureMmu ( return RETURN_SUCCESS; FREE_TRANSLATION_TABLE: - if (TranslationTableBuffer != NULL) { - FreePool (TranslationTableBuffer); - } else { - FreePages (TranslationTable, 1); - } + FreePages (TranslationTable, 1); return Status; } -- 2.7.4