From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B443482027 for ; Wed, 8 Feb 2017 23:20:36 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 08 Feb 2017 23:20:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,349,1484035200"; d="scan'208";a="1124128247" Received: from jyao1-mobl.ccr.corp.intel.com ([10.254.176.87]) by fmsmga002.fm.intel.com with ESMTP; 08 Feb 2017 23:20:36 -0800 From: Jiewen Yao To: edk2-devel@lists.01.org Cc: Leif Lindholm , Ard Biesheuvel Date: Wed, 8 Feb 2017 23:20:30 -0800 Message-Id: <1486624832-15736-3-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1486624832-15736-1-git-send-email-jiewen.yao@intel.com> References: <1486624832-15736-1-git-send-email-jiewen.yao@intel.com> Subject: [PATCH V3 2/4] ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Feb 2017 07:20:36 -0000 Current Arm CpuDxe driver uses EFI_MEMORY_WP for write protection, according to UEFI spec, we should use EFI_MEMORY_RO for write protection. The EFI_MEMORY_WP is the cache attribute instead of memory attribute. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao --- ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 3 ++- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 14 ++++++-------- ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 5 +++-- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 3 ++- 4 files changed, 13 insertions(+), 12 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c index d8bb419..15d5a81 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -3,6 +3,7 @@ Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
Portions copyright (c) 2010, Apple Inc. All rights reserved.
Portions copyright (c) 2011-2013, ARM Ltd. All rights reserved.
+Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -224,7 +225,7 @@ EfiAttributeToArmAttribute ( ArmAttributes |= TT_AF; // Determine protection attributes - if (EfiAttributes & EFI_MEMORY_WP) { + if (EfiAttributes & EFI_MEMORY_RO) { ArmAttributes |= TT_AP_RO_RO; } diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c index 14fc22d..6dcfba6 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -3,6 +3,7 @@ Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.
Portions copyright (c) 2010, Apple Inc. All rights reserved.
Portions copyright (c) 2013, ARM Ltd. All rights reserved.
+Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -62,7 +63,7 @@ SectionToGcdAttributes ( // determine protection attributes switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) { case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write - //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP; + //*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP; break; case TT_DESCRIPTOR_SECTION_AP_RW_NO: @@ -73,7 +74,7 @@ SectionToGcdAttributes ( // read only cases map to write-protect case TT_DESCRIPTOR_SECTION_AP_RO_NO: case TT_DESCRIPTOR_SECTION_AP_RO_RO: - *GcdAttributes |= EFI_MEMORY_WP; + *GcdAttributes |= EFI_MEMORY_RO; break; default: @@ -126,7 +127,7 @@ PageToGcdAttributes ( // determine protection attributes switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) { case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write - //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP; + //*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP; break; case TT_DESCRIPTOR_PAGE_AP_RW_NO: @@ -137,7 +138,7 @@ PageToGcdAttributes ( // read only cases map to write-protect case TT_DESCRIPTOR_PAGE_AP_RO_NO: case TT_DESCRIPTOR_PAGE_AP_RO_RO: - *GcdAttributes |= EFI_MEMORY_WP; + *GcdAttributes |= EFI_MEMORY_RO; break; default: @@ -730,9 +731,6 @@ EfiAttributeToArmAttribute ( ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 break; - case EFI_MEMORY_WP: - case EFI_MEMORY_XP: - case EFI_MEMORY_RP: case EFI_MEMORY_UCE: default: // Cannot be implemented UEFI definition unclear for ARM @@ -743,7 +741,7 @@ EfiAttributeToArmAttribute ( } // Determine protection attributes - if (EfiAttributes & EFI_MEMORY_WP) { + if (EfiAttributes & EFI_MEMORY_RO) { ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RO_RO; } else { ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RW_RW; diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c index 723604d..54d9b01 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c @@ -1,6 +1,7 @@ /** @file * * Copyright (c) 2013, ARM Limited. All rights reserved. +* Copyright (c) 2017, Intel Corporation. All rights reserved.
* * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -236,7 +237,7 @@ CpuConvertPagesToUncachedVirtualAddress ( // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask // to that address. // - Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0); + Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_RO, 0); if (!EFI_ERROR (Status)) { Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask); } @@ -264,7 +265,7 @@ CpuReconvertPages ( // // Unmap the aliased Address // - Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0); + Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_RO, 0); if (!EFI_ERROR (Status)) { // // Restore atttributes diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 540069a..6aa970b 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -3,6 +3,7 @@ * * Copyright (c) 2011-2014, ARM Limited. All rights reserved. * Copyright (c) 2016, Linaro Limited. All rights reserved. +* Copyright (c) 2017, Intel Corporation. All rights reserved.
* * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -89,7 +90,7 @@ PageAttributeToGcdAttribute ( // Determine protection attributes if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) || ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) { // Read only cases map to write-protect - GcdAttributes |= EFI_MEMORY_WP; + GcdAttributes |= EFI_MEMORY_RO; } // Process eXecute Never attribute -- 2.7.4.windows.1