From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x232.google.com (mail-wm0-x232.google.com [IPv6:2a00:1450:400c:c09::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CC34C81F3E for ; Thu, 9 Feb 2017 09:38:25 -0800 (PST) Received: by mail-wm0-x232.google.com with SMTP id r141so26785570wmg.1 for ; Thu, 09 Feb 2017 09:38:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ywl5qAGk6g336cBaMwBM9i/ltNTTTzquouWD/dFG750=; b=GxhkaRsn0gEmhAYj5U+ZswR2sk6hOVNPcPo3K3q1YU9aQrpJ97G/yWJ+VAmpJJE1FZ aEKcTBeWA4NBCzKuYdFKhEEsNfU7uCo6Lqxz9Vwmu8DnOsz8fUfuQVstd/0o+F9q/1Cx aJA6Gmnsxbrw2Wa5djuaXLePS2sVeCbGZ28sA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ywl5qAGk6g336cBaMwBM9i/ltNTTTzquouWD/dFG750=; b=ikwo+R1cbpwsC2Z46w47whoB8POcmuUab7Pie5gwNX5ECj2r6D2lNU7sTwolxn9zd7 00EJxiX4LohkDylzN4d/SVhcFLMtAq4lQr0P1MWV3qu6yB8CqU5iPwgv7a9xK60OxKLt pk2bCcdw+imJlEQJe9xZnwKNbZGFdzkL+zphLx97XkeebvMiDX3xG3dQ2CiM7dGRJVJp y3FdOA1CwcpZvLL9OQrQVDEybygFfoK/zVcLaKD4nTEa8CX3EGR0qWmMtGveZHE5rxoY mIUHdSwcGWydgNt/EIUdIIpNVrMuS1k7+bTVxuJBFqVLd7AP8GxzRBDsJaFjLJXnzL/a 00aQ== X-Gm-Message-State: AMke39n2EgyA0e1ZbSanSRAjUkpZ/ZRQgT0hotW95fU0Of6+dBvfT8a0mvzLw62V0f2u84S2 X-Received: by 10.28.98.2 with SMTP id w2mr4320782wmb.66.1486661903944; Thu, 09 Feb 2017 09:38:23 -0800 (PST) Received: from localhost.localdomain ([160.169.163.122]) by smtp.gmail.com with ESMTPSA id p49sm19530786wrb.10.2017.02.09.09.38.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Feb 2017 09:38:23 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, jiewen.yao@intel.com Cc: feng.tian@intel.com, michael.d.kinney@intel.com, jeff.fan@intel.com, star.zeng@intel.com, Ard Biesheuvel Date: Thu, 9 Feb 2017 17:38:07 +0000 Message-Id: <1486661891-7888-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Subject: [PATCH 0/4] ArmPkg: add groundwork for DXE image protection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Feb 2017 17:38:26 -0000 The upcoming DXE image protection feature expects the EFI_CPU_ARCH_PROTOCOL method SetMemoryAttributes() to deal with invocations that only modify permission attributes, but leave the cacheability attributes alone. This requires some groundwork to be performed in the MMU code for ARM. Patch #1 is Jiewen's patch to retire EFI_MEMORY_WP, which is no longer used as a permission attribute. Patch #2 updates EfiAttributeToArmAttribute () so it can deal with unspecified caching modes. Patch #3 makes ARM deal with EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() calls that do not specify memory attributes. On ARM, we don't have code that manages the permission bits in the page tables, so this does little more than ignore such attributes. Patch #4 implements the handling for AARCH64 to manage the permissions bits without touching or caring about the memory type attributes. Ard Biesheuvel (3): ArmPkg/CpuDxe: translate invalid memory types in EfiAttributeToArmAttribute ArmPkg/CpuDxe: ARM: ignore page table updates that only change permissions ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissions Jiewen Yao (1): ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 7 +- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 24 ++++--- ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 5 +- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 76 +++++++++++++++----- 4 files changed, 77 insertions(+), 35 deletions(-) -- 2.7.4