From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x235.google.com (mail-wm0-x235.google.com [IPv6:2a00:1450:400c:c09::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B718981FF7 for ; Thu, 9 Feb 2017 09:38:29 -0800 (PST) Received: by mail-wm0-x235.google.com with SMTP id v77so26676453wmv.0 for ; Thu, 09 Feb 2017 09:38:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C7MyAVGHImQtQ8bJQJ1Mw8WfLuTPyFcdFkKD3ny+GNM=; b=G0K/3LdmnzvBLgrtJYVgd8azgG28Lq5DQJM5R5iwduMOHja3U2ZduKOHEUbC73RUoQ pYrnbaro1lNHo7Gay/3krtu/jxPiYKf18zCmescQglN8mmSCveL4BFGrQVKUMCEoeRw6 MHoe8aBfa9SuDwioHWL9uFalkF8xbTgN709Ow= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C7MyAVGHImQtQ8bJQJ1Mw8WfLuTPyFcdFkKD3ny+GNM=; b=F/qEHuj4AzeN/rBfTuSjsnVAmG1pA/WRqPFpps+wvLZ6nd3Hbl3AxmDAMS7edj7obG ++IIV/SydAfsehcp5IxQJCDPq3ZQU1sFZZ/wrQPL2H45nthgUWvIYlzaYqEKhTQKwoHn T9ax+MDr5TwLlcRf1aAiMvCUw+vRoc4/JU5/bMwZrh7DD0flx2xE9iHoIIJY0F08fDih ojUnDMA9mHOQiUIk43cylJMkqS2NF2TaA+4lOZpZf32ZruERh1XzkcVhJAOFli0QHMtE jhDeUekBnGq7/T/wTG33JIKvtT7EwHCNdIwC1hc8V2zL1nCYkUcw8SavcV/vLI/2bpoo nFWQ== X-Gm-Message-State: AMke39mWxlWQbe3WeiTqRzMDw0YGXIsC9tKWnpB3te1DEgMpY3ulJhpPp2pJm0jbfHIJrZ6/ X-Received: by 10.28.178.16 with SMTP id b16mr25607598wmf.83.1486661908352; Thu, 09 Feb 2017 09:38:28 -0800 (PST) Received: from localhost.localdomain ([160.169.163.122]) by smtp.gmail.com with ESMTPSA id p49sm19530786wrb.10.2017.02.09.09.38.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Feb 2017 09:38:27 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, jiewen.yao@intel.com Cc: feng.tian@intel.com, michael.d.kinney@intel.com, jeff.fan@intel.com, star.zeng@intel.com, Ard Biesheuvel Date: Thu, 9 Feb 2017 17:38:09 +0000 Message-Id: <1486661891-7888-3-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486661891-7888-1-git-send-email-ard.biesheuvel@linaro.org> References: <1486661891-7888-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH 2/4] ArmPkg/CpuDxe: translate invalid memory types in EfiAttributeToArmAttribute X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Feb 2017 17:38:30 -0000 The single user of EfiAttributeToArmAttribute () is the protocol method EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes(), which uses the return value to compare against the ARM attributes of an existing mapping, to infer whether it is actually necessary to change anything, or whether the requested update is redundant. This saves some cache and TLB maintenance on 32-bit ARM systems that use uncached translation tables. However, EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() may be invoked with only permission bits set, in which case the implied requested action is to update the permissions of the region without modifying the cacheability attributes. This is currently not possible, because EfiAttributeToArmAttribute () ASSERT()s [on AArch64] on Attributes arguments that lack a cacheability bit. So let's simply return TT_ATTR_INDX_INVALID (AArch64) or TT_DESCRIPTOR_SECTION_TYPE_FAULT (ARM) in these cases (or'ed with the appropriate permission bits). This way, the return value is equally suitable for checking whether the attributes need to be modified, but in a way that accommodates the use without a cacheability bit set. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 4 +--- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 3 --- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c index 15d5a8173233..7688846e70cb 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -216,9 +216,7 @@ EfiAttributeToArmAttribute ( ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK; break; default: - DEBUG ((EFI_D_ERROR, "EfiAttributeToArmAttribute: 0x%lX attributes is not supported.\n", EfiAttributes)); - ASSERT (0); - ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY; + ArmAttributes = TT_ATTR_INDX_MASK; } // Set the access flag to match the block attributes diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c index 6dcfba69e879..b6ba975b353a 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -733,10 +733,7 @@ EfiAttributeToArmAttribute ( case EFI_MEMORY_UCE: default: - // Cannot be implemented UEFI definition unclear for ARM - // Cause a page fault if these ranges are accessed. ArmAttributes = TT_DESCRIPTOR_SECTION_TYPE_FAULT; - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): Unsupported attribute %x will page fault on access\n", EfiAttributes)); break; } -- 2.7.4