From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22b.google.com (mail-wr0-x22b.google.com [IPv6:2a00:1450:400c:c0c::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C046281FFB for ; Thu, 9 Feb 2017 09:38:31 -0800 (PST) Received: by mail-wr0-x22b.google.com with SMTP id k90so88606062wrc.3 for ; Thu, 09 Feb 2017 09:38:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9eVjZ13EEuxccdTzIKv7cVNyuRkk/74EnZjy0bKKUnc=; b=BRcsfAoiyk8d8UOzjgn8K4zsZjf4tTKox+UYaEEGZbjvBOji/BDPBa1sr6HVlVrswU xEG32KSTVnXJbLajRdzTc6UNeOxzpqPtnS765VATdzda5Eg+ESG0SGoNiztgVCivWbyM XLpvRe5coI61gNxkzxIQnQYPXnTX4XJps1awc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9eVjZ13EEuxccdTzIKv7cVNyuRkk/74EnZjy0bKKUnc=; b=WNu7HHSh4Qxr3wUdpynxZKbMkP2MCotb8rh2hQa5aP4SKEnisSK9MQxnE4YAu0kWso gGPuzYoDIgbAw38APuWsvth6Hx+Ff0g/KGVOxksmOdx1OyCqMsb3nIK55qL0mqt4eP/s HEVnOLIooFyMdFAHSSaE9OQT3P2laR//OxAAfwNZjrB96cyqkGX9KhqOvDirlioZsEXW Yun9La2QNaIINEcAja2/coE/RtH7gYq1Bccqnfo5ca8ojO3U7nvfmDYfUv4gNzGcpkVR f0ZunJq2wX93pflV1CsqGCDsFEZNYm1+noCjrhhJ33rLh+ne3v4Omw9HyuzQuGI6vAL7 lNSg== X-Gm-Message-State: AMke39newioSDyEtluWIwGdyFOYXWEPxks9FWFIa3G6WUKp0daBtZeaV232BCsasMKK5jIkc X-Received: by 10.223.172.136 with SMTP id o8mr3939672wrc.76.1486661910416; Thu, 09 Feb 2017 09:38:30 -0800 (PST) Received: from localhost.localdomain ([160.169.163.122]) by smtp.gmail.com with ESMTPSA id p49sm19530786wrb.10.2017.02.09.09.38.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Feb 2017 09:38:29 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, jiewen.yao@intel.com Cc: feng.tian@intel.com, michael.d.kinney@intel.com, jeff.fan@intel.com, star.zeng@intel.com, Ard Biesheuvel Date: Thu, 9 Feb 2017 17:38:10 +0000 Message-Id: <1486661891-7888-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486661891-7888-1-git-send-email-ard.biesheuvel@linaro.org> References: <1486661891-7888-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH 3/4] ArmPkg/CpuDxe: ARM: ignore page table updates that only change permissions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Feb 2017 17:38:32 -0000 Currently, we have not implemented support on 32-bit ARM for managing permission bits in the page tables. Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, let's simply ignore those for now. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c index b6ba975b353a..89e429925ba9 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -680,6 +680,13 @@ SetMemoryAttributes ( { EFI_STATUS Status; + // + // Ignore invocations that only modify permission bits + // + if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) { + return EFI_SUCCESS; + } + if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) { // Is the base and length a multiple of 1 MB? DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes)); -- 2.7.4