From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, jiewen.yao@intel.com
Cc: feng.tian@intel.com, michael.d.kinney@intel.com,
jeff.fan@intel.com, star.zeng@intel.com,
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: [PATCH 4/4] ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissions
Date: Thu, 9 Feb 2017 17:38:11 +0000 [thread overview]
Message-ID: <1486661891-7888-5-git-send-email-ard.biesheuvel@linaro.org> (raw)
In-Reply-To: <1486661891-7888-1-git-send-email-ard.biesheuvel@linaro.org>
Since the new DXE page protection for PE/COFF images may invoke
EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission
attributes set, add support for this in the AARCH64 MMU code.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 73 +++++++++++++++-----
1 file changed, 56 insertions(+), 17 deletions(-)
diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
index 6aa970bc0514..764e54b5d747 100644
--- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
+++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c
@@ -28,6 +28,10 @@
// We use this index definition to define an invalid block entry
#define TT_ATTR_INDX_INVALID ((UINT32)~0)
+#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
+ EFI_MEMORY_WT | EFI_MEMORY_WB | \
+ EFI_MEMORY_UCE)
+
STATIC
UINT64
ArmMemoryAttributeToPageAttribute (
@@ -101,25 +105,46 @@ PageAttributeToGcdAttribute (
return GcdAttributes;
}
-ARM_MEMORY_REGION_ATTRIBUTES
-GcdAttributeToArmAttribute (
+STATIC
+UINT64
+GcdAttributeToPageAttribute (
IN UINT64 GcdAttributes
)
{
- switch (GcdAttributes & 0xFF) {
+ UINT64 PageAttributes;
+
+ switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {
case EFI_MEMORY_UC:
- return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
+ break;
case EFI_MEMORY_WC:
- return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+ PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
+ break;
case EFI_MEMORY_WT:
- return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH;
+ PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
+ break;
case EFI_MEMORY_WB:
- return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+ PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
+ break;
default:
- DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes));
- ASSERT (0);
- return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ PageAttributes = TT_ATTR_INDX_MASK;
+ break;
}
+
+ if ((GcdAttributes & EFI_MEMORY_XP) != 0 ||
+ (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC) {
+ if (ArmReadCurrentEL () == AARCH64_EL2) {
+ PageAttributes |= TT_XN_MASK;
+ } else {
+ PageAttributes |= TT_UXN_MASK | TT_PXN_MASK;
+ }
+ }
+
+ if ((GcdAttributes & EFI_MEMORY_RO) != 0) {
+ PageAttributes |= TT_AP_RO_RO;
+ }
+
+ return PageAttributes | TT_AF;
}
#define MIN_T0SZ 16
@@ -434,17 +459,31 @@ SetMemoryAttributes (
)
{
RETURN_STATUS Status;
- ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion;
UINT64 *TranslationTable;
-
- MemoryRegion.PhysicalBase = BaseAddress;
- MemoryRegion.VirtualBase = BaseAddress;
- MemoryRegion.Length = Length;
- MemoryRegion.Attributes = GcdAttributeToArmAttribute (Attributes);
+ UINT64 PageAttributes;
+ UINT64 PageAttributeMask;
+
+ PageAttributes = GcdAttributeToPageAttribute (Attributes);
+ PageAttributeMask = 0;
+
+ if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) {
+ //
+ // No memory type was set in Attributes, so we are going to update the
+ // permissions only.
+ //
+ PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK;
+ PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK |
+ TT_PXN_MASK | TT_XN_MASK);
+ }
TranslationTable = ArmGetTTBR0BaseAddress ();
- Status = FillTranslationTable (TranslationTable, &MemoryRegion);
+ Status = UpdateRegionMapping (
+ TranslationTable,
+ BaseAddress,
+ Length,
+ PageAttributes,
+ PageAttributeMask);
if (RETURN_ERROR (Status)) {
return Status;
}
--
2.7.4
next prev parent reply other threads:[~2017-02-09 17:38 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-09 17:38 [PATCH 0/4] ArmPkg: add groundwork for DXE image protection Ard Biesheuvel
2017-02-09 17:38 ` [PATCH 1/4] ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage Ard Biesheuvel
2017-02-10 18:17 ` Leif Lindholm
2017-02-10 18:25 ` Ard Biesheuvel
2017-02-10 19:36 ` Leif Lindholm
2017-02-09 17:38 ` [PATCH 2/4] ArmPkg/CpuDxe: translate invalid memory types in EfiAttributeToArmAttribute Ard Biesheuvel
2017-02-10 17:54 ` Leif Lindholm
2017-02-10 17:56 ` Ard Biesheuvel
2017-02-09 17:38 ` [PATCH 3/4] ArmPkg/CpuDxe: ARM: ignore page table updates that only change permissions Ard Biesheuvel
2017-02-10 17:59 ` Leif Lindholm
2017-02-09 17:38 ` Ard Biesheuvel [this message]
2017-02-10 18:16 ` [PATCH 4/4] ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissions Leif Lindholm
2017-02-10 18:23 ` Ard Biesheuvel
2017-02-11 14:35 ` Leif Lindholm
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