From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22c.google.com (mail-wm0-x22c.google.com [IPv6:2a00:1450:400c:c09::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 08E9482090 for ; Wed, 15 Feb 2017 09:12:10 -0800 (PST) Received: by mail-wm0-x22c.google.com with SMTP id v186so47363201wmd.0 for ; Wed, 15 Feb 2017 09:12:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=3Ws3cOFv1Qv3GxaKjV8XFIKK82br+8GLmU+tBvOanuA=; b=N3ERg+LXuUAN2Xm4dR1YgrlXkpHfOzTf/y95rIB8OewvXwoRMtkGqNEY8fQkSpxpv/ az7ADv0tj3ZSHXgH9iue2pGpGKgFSZ0+TtzAP1M/UYmO7a7/G0d1G/XvHd3SlibI8KPw kaKLSwxG64orBxViiD/ev+7Csj+3eeuk1V4yg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=3Ws3cOFv1Qv3GxaKjV8XFIKK82br+8GLmU+tBvOanuA=; b=nMX3S2ssH9jV7omb21SUgHCMXcbTPCZ/MZEgLOUfF3GyJ3Lbq+4ZZWdj3XdeJuXG3n PG51sZjsImcQQyVqK8O7tS9O5jhRKa6MJeh4wyMRU5xqUKBCTXgcX4hIo7L1eeKDsnIM kpMSlL0mnOFkLekJbVbgx60hdJ0Up08X3hJUZHmJyFswIKJcgB5eQEPdAf7tYCtfdRne Q2z99J0O0bdfdoS5RqmkXGVWyQ6QS6Fka/QMKpJyQjyoZVMxIzbodyLZ3gYGa5M7gCRx htkgtSepBDlSmMqdG34gcbGzcrrpQx8gZ8oIOWiR+spB8GxFO7H8RRKxGHcdme9R0V1n vxpQ== X-Gm-Message-State: AMke39nrUDJxVqtTUTzmSNv8GYLtGzEJi0mFuZM09MfNZTNcffKi3o9LEJesLqLnRutMHPVR X-Received: by 10.28.69.194 with SMTP id l63mr8662827wmi.23.1487178728387; Wed, 15 Feb 2017 09:12:08 -0800 (PST) Received: from localhost.localdomain ([196.80.229.213]) by smtp.gmail.com with ESMTPSA id n13sm5606276wrn.40.2017.02.15.09.12.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Feb 2017 09:12:07 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Cc: jiewen.yao@intel.com, Ard Biesheuvel Date: Wed, 15 Feb 2017 17:11:52 +0000 Message-Id: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Subject: [PATCH v2 0/4] ArmPkg: add groundwork for DXE image protection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Feb 2017 17:12:10 -0000 The upcoming DXE image protection feature expects the EFI_CPU_ARCH_PROTOCOL method SetMemoryAttributes() to deal with invocations that only modify permission attributes, but leave the cacheability attributes alone. This requires some groundwork to be performed in the MMU code for ARM. Patch #1 is Jiewen's patch to retire EFI_MEMORY_WP, which is no longer used as a permission attribute. Patch #2 updates EfiAttributeToArmAttribute () so it can deal with unspecified caching modes. Patch #3 makes ARM deal with EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() calls that do not specify memory attributes. On ARM, we don't have code that manages the permission bits in the page tables, so this does little more than ignore such attributes. Patch #4 implements the handling for AARCH64 to manage the permissions bits without touching or caring about the memory type attributes. Changes since v1: - add Leif's and my R-b to #1 - add Leif's R-b to #3 - fix reference to TT_ATTR_INDX_MASK in commit log (#2) - move rather than redefine EFI_MEMORY_CACHETYPE_MASK macro (#4) Ard Biesheuvel (3): ArmPkg/CpuDxe: translate invalid memory types in EfiAttributeToArmAttribute ArmPkg/CpuDxe: ARM: ignore page table updates that only change permissions ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissions Jiewen Yao (1): ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 7 +- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 24 ++--- ArmPkg/Drivers/CpuDxe/CpuDxe.h | 8 -- ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 5 +- ArmPkg/Include/Library/ArmLib.h | 4 + ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 94 ++++++++++++++------ 6 files changed, 88 insertions(+), 54 deletions(-) -- 2.7.4