From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x235.google.com (mail-wm0-x235.google.com [IPv6:2a00:1450:400c:c09::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 079B382098 for ; Wed, 15 Feb 2017 09:12:13 -0800 (PST) Received: by mail-wm0-x235.google.com with SMTP id v186so47364577wmd.0 for ; Wed, 15 Feb 2017 09:12:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W9mBkPQBZ2xJecjpowmoGf0x4J/DKjvrZJwQv85vuXU=; b=jNh90TplLQ46u3TSaBrs0qOT1IajHASBo4z6CWWoKV90Rbu+vePIjwvGPaFVoeDUyX kYlhVj17AdqA+yD0XqXW5EaRL1YxIJdm36FXtxNJbSGCKulkFLryHI03jZp6F+1v0bRi hv60QCI6dR3NGiRvMWAR7V/qo+oVklHTxRcd4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W9mBkPQBZ2xJecjpowmoGf0x4J/DKjvrZJwQv85vuXU=; b=fJgCv6GP4/TocgqHJsFR/ehbeTkf+4G29GPk99yM4v0gVZWwqbnW7gOjtaoL+Oo7Qw sQXzYzlcb/+NQEJvWfh0fYmHG39vo1g6/q7kZyNtqjZ82vG9/D6K+ZQfrLRipaMVrP+0 hbGMXtm8moY5Vob5OYJ9OYVbua9HKkov4yqC0dZNKM9KqiAk9PlrtZU9M1GZzHy+89Xm I5Q8Os1c4m3VceJVLEMkCQivMmdWbVzWhK5rZAcZ1K3tUK8rSe0NczE2681P9urfAebS oaW5bgJ+rJyE7DbS0dfqwaIGDhsgCfUSJJ7LlvuJ0q/F+jq4tsGw1EBGtEP5J1AOoNN0 N4kg== X-Gm-Message-State: AMke39kjhlBDXlAZQXAEEhsBKqSWZ9xkumJvhbidbCBhZHiRKy0n09zlM3CisJIpNX54WV+L X-Received: by 10.28.109.27 with SMTP id i27mr8745753wmc.54.1487178731473; Wed, 15 Feb 2017 09:12:11 -0800 (PST) Received: from localhost.localdomain ([196.80.229.213]) by smtp.gmail.com with ESMTPSA id n13sm5606276wrn.40.2017.02.15.09.12.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Feb 2017 09:12:10 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Cc: jiewen.yao@intel.com, Ard Biesheuvel Date: Wed, 15 Feb 2017 17:11:54 +0000 Message-Id: <1487178716-24569-3-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> References: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH v2 2/4] ArmPkg/CpuDxe: translate invalid memory types in EfiAttributeToArmAttribute X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Feb 2017 17:12:13 -0000 The single user of EfiAttributeToArmAttribute () is the protocol method EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes(), which uses the return value to compare against the ARM attributes of an existing mapping, to infer whether it is actually necessary to change anything, or whether the requested update is redundant. This saves some cache and TLB maintenance on 32-bit ARM systems that use uncached translation tables. However, EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() may be invoked with only permission bits set, in which case the implied requested action is to update the permissions of the region without modifying the cacheability attributes. This is currently not possible, because EfiAttributeToArmAttribute () ASSERT()s [on AArch64] on Attributes arguments that lack a cacheability bit. So let's simply return TT_ATTR_INDX_MASK (AArch64) or TT_DESCRIPTOR_SECTION_TYPE_FAULT (ARM) in these cases (or'ed with the appropriate permission bits). This way, the return value is equally suitable for checking whether the attributes need to be modified, but in a way that accommodates the use without a cacheability bit set. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 4 +--- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 3 --- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c index 15d5a8173233..7688846e70cb 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -216,9 +216,7 @@ EfiAttributeToArmAttribute ( ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK; break; default: - DEBUG ((EFI_D_ERROR, "EfiAttributeToArmAttribute: 0x%lX attributes is not supported.\n", EfiAttributes)); - ASSERT (0); - ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY; + ArmAttributes = TT_ATTR_INDX_MASK; } // Set the access flag to match the block attributes diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c index 6dcfba69e879..b6ba975b353a 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -733,10 +733,7 @@ EfiAttributeToArmAttribute ( case EFI_MEMORY_UCE: default: - // Cannot be implemented UEFI definition unclear for ARM - // Cause a page fault if these ranges are accessed. ArmAttributes = TT_DESCRIPTOR_SECTION_TYPE_FAULT; - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): Unsupported attribute %x will page fault on access\n", EfiAttributes)); break; } -- 2.7.4