From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x232.google.com (mail-wm0-x232.google.com [IPv6:2a00:1450:400c:c09::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 603B982098 for ; Wed, 15 Feb 2017 09:12:14 -0800 (PST) Received: by mail-wm0-x232.google.com with SMTP id r141so45887471wmg.1 for ; Wed, 15 Feb 2017 09:12:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/6G7fvFSTF0PF+7NmXcLXKQcm+tAQmeeDvuefLvTFYw=; b=gMvvA32B9fm00gmZVEpmOrvoh/B5yNnv2UcNlTg5nucABJkj1uObxp0z5O5/OCTPee AP25iQaadto9H9hS4E6mtUm2ZSIQjepDXVASRo6Ki9LthuJ8L5cDOyUTB6B0JvwOGdvx 2bso324rpKAZwVmkrwxg+0sR8mB6Xc6/JC+4s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/6G7fvFSTF0PF+7NmXcLXKQcm+tAQmeeDvuefLvTFYw=; b=XgxJwv6I/sGhrXymg3em4Ls5uvOzK8I1Lze5f7ijpe+dKknkKoHLS6ay3lxQY4gA8h fjyRbhkAPrgxkgRRhSKzW1VIfWouN1zap8jhNdlb6BahDx/k/Oi2pXOR4VfkNt/3zPKE ARov8QOs+5L5D4WPvEFSHutYr4dvOmybmS7Y71kr6oPtOTUYUHz4DemW94LWptkU1A4Z xSALlpq1NoJ8GPmq2mU4koVVt8QpOw0BtTCuKUSnG9ltMTr+JjUgBF1Hwbopz64jbxLk /myTQwgjX4g0/o/ikuDsQ4kJD9fHd1/IyfmrQ+4v0cYNKudgbYvvE6hkrrUzXxKGuVAl 1EVw== X-Gm-Message-State: AMke39nYTNl6VpAbzyoxbRC9vIrnL9RhucE4NmvciX0B9Lda4uAF1IyMQ8ps2MDrLeEIS5v+ X-Received: by 10.28.210.65 with SMTP id j62mr8952875wmg.9.1487178732949; Wed, 15 Feb 2017 09:12:12 -0800 (PST) Received: from localhost.localdomain ([196.80.229.213]) by smtp.gmail.com with ESMTPSA id n13sm5606276wrn.40.2017.02.15.09.12.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Feb 2017 09:12:12 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Cc: jiewen.yao@intel.com, Ard Biesheuvel Date: Wed, 15 Feb 2017 17:11:55 +0000 Message-Id: <1487178716-24569-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> References: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH v2 3/4] ArmPkg/CpuDxe: ARM: ignore page table updates that only change permissions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Feb 2017 17:12:14 -0000 Currently, we have not implemented support on 32-bit ARM for managing permission bits in the page tables. Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, let's simply ignore those for now. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c index b6ba975b353a..89e429925ba9 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -680,6 +680,13 @@ SetMemoryAttributes ( { EFI_STATUS Status; + // + // Ignore invocations that only modify permission bits + // + if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) { + return EFI_SUCCESS; + } + if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) { // Is the base and length a multiple of 1 MB? DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes)); -- 2.7.4