From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x235.google.com (mail-wr0-x235.google.com [IPv6:2a00:1450:400c:c0c::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3F3C482090 for ; Wed, 15 Feb 2017 09:12:16 -0800 (PST) Received: by mail-wr0-x235.google.com with SMTP id c4so37600921wrd.2 for ; Wed, 15 Feb 2017 09:12:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ApY7PI37whBifL85OS0d5SqTQ98eo2ofcxBtWw2+Yq8=; b=ES0ZNDAImnKj4A1RJlzWc+U+vsI1eL8UbsKF+kmkOR+/zZVetQOdUI6jGx09Zn+VX3 5yOD+EddJolnC/eHz4MSGdimmdsJStUIF/l3XVUGvSXuKiWzRW850e1G8Io4ZGZiAddX f3ASwupTlG2APZpuFiEOhhC3cuZtE5Ay14pbo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ApY7PI37whBifL85OS0d5SqTQ98eo2ofcxBtWw2+Yq8=; b=oN9FHKn7bz3kY7RByqjUVhv6m48pA1QDk+701qh9RciQWZj5/z9fIIo9w4kvgvFLr1 nClWYXd+4ZzL+SUM7iRiMpQbju8MrqT54HUjNro6FY+l0Iy+RcbBkxcIPJsyqOX3wELL HpIPdFI+l6SQhkZujjiuIC5hUSr9bQ60wF0z2BHViKIHBPVleFuDtPHApFj3cwRs6v8D 9BB4ePkDdWxPE2rXEux3SGX4O3JERRea7B6hseu33qmcjN+4PY3A9BDO1AYsTrDl/2Fx Eox6QYi0r3J1liHF/1CX/kYScVCVmEi/5c5Uv0fmifUDA/PLePChnAOHzfZkhvvkOEjf smpA== X-Gm-Message-State: AMke39k6S+RrW6ebyHRyrrZ0oaqCjns1TBcJnH/e9ls8n0nc7QHSUrL8ZM8BajxrxgKiAVkg X-Received: by 10.223.163.75 with SMTP id d11mr30622319wrb.87.1487178734601; Wed, 15 Feb 2017 09:12:14 -0800 (PST) Received: from localhost.localdomain ([196.80.229.213]) by smtp.gmail.com with ESMTPSA id n13sm5606276wrn.40.2017.02.15.09.12.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Feb 2017 09:12:13 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Cc: jiewen.yao@intel.com, Ard Biesheuvel Date: Wed, 15 Feb 2017 17:11:56 +0000 Message-Id: <1487178716-24569-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> References: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH v2 4/4] ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Feb 2017 17:12:16 -0000 Since the new DXE page protection for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission attributes set, add support for this in the AARCH64 MMU code. Move the EFI_MEMORY_CACHETYPE_MASK macro to a shared location between CpuDxe and ArmMmuLib so we don't have to introduce yet another definition. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/CpuDxe.h | 8 -- ArmPkg/Include/Library/ArmLib.h | 4 + ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 91 ++++++++++++++------ 3 files changed, 67 insertions(+), 36 deletions(-) diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h index d16abe400ef3..80c305d53dd1 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h @@ -39,14 +39,6 @@ #include -#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | \ - EFI_MEMORY_WC | \ - EFI_MEMORY_WT | \ - EFI_MEMORY_WB | \ - EFI_MEMORY_UCE \ - ) - - /** This function registers and enables the handler specified by InterruptHandler for a processor interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index 19501efa991f..24ffe9f1aaa7 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -26,6 +26,10 @@ #error "Unknown chipset." #endif +#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \ + EFI_MEMORY_WT | EFI_MEMORY_WB | \ + EFI_MEMORY_UCE) + /** * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes. * diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 6aa970bc0514..9e0593ce598b 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -101,27 +101,6 @@ PageAttributeToGcdAttribute ( return GcdAttributes; } -ARM_MEMORY_REGION_ATTRIBUTES -GcdAttributeToArmAttribute ( - IN UINT64 GcdAttributes - ) -{ - switch (GcdAttributes & 0xFF) { - case EFI_MEMORY_UC: - return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; - case EFI_MEMORY_WC: - return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; - case EFI_MEMORY_WT: - return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH; - case EFI_MEMORY_WB: - return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; - default: - DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes)); - ASSERT (0); - return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; - } -} - #define MIN_T0SZ 16 #define BITS_PER_LEVEL 9 @@ -425,6 +404,48 @@ FillTranslationTable ( ); } +STATIC +UINT64 +GcdAttributeToPageAttribute ( + IN UINT64 GcdAttributes + ) +{ + UINT64 PageAttributes; + + switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) { + case EFI_MEMORY_UC: + PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY; + break; + case EFI_MEMORY_WC: + PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE; + break; + case EFI_MEMORY_WT: + PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE; + break; + case EFI_MEMORY_WB: + PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; + break; + default: + PageAttributes = TT_ATTR_INDX_MASK; + break; + } + + if ((GcdAttributes & EFI_MEMORY_XP) != 0 || + (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC) { + if (ArmReadCurrentEL () == AARCH64_EL2) { + PageAttributes |= TT_XN_MASK; + } else { + PageAttributes |= TT_UXN_MASK | TT_PXN_MASK; + } + } + + if ((GcdAttributes & EFI_MEMORY_RO) != 0) { + PageAttributes |= TT_AP_RO_RO; + } + + return PageAttributes | TT_AF; +} + RETURN_STATUS SetMemoryAttributes ( IN EFI_PHYSICAL_ADDRESS BaseAddress, @@ -434,17 +455,31 @@ SetMemoryAttributes ( ) { RETURN_STATUS Status; - ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion; UINT64 *TranslationTable; - - MemoryRegion.PhysicalBase = BaseAddress; - MemoryRegion.VirtualBase = BaseAddress; - MemoryRegion.Length = Length; - MemoryRegion.Attributes = GcdAttributeToArmAttribute (Attributes); + UINT64 PageAttributes; + UINT64 PageAttributeMask; + + PageAttributes = GcdAttributeToPageAttribute (Attributes); + PageAttributeMask = 0; + + if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) { + // + // No memory type was set in Attributes, so we are going to update the + // permissions only. + // + PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK; + PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK | + TT_PXN_MASK | TT_XN_MASK); + } TranslationTable = ArmGetTTBR0BaseAddress (); - Status = FillTranslationTable (TranslationTable, &MemoryRegion); + Status = UpdateRegionMapping ( + TranslationTable, + BaseAddress, + Length, + PageAttributes, + PageAttributeMask); if (RETURN_ERROR (Status)) { return Status; } -- 2.7.4