From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x230.google.com (mail-wm0-x230.google.com [IPv6:2a00:1450:400c:c09::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A305282242 for ; Wed, 22 Feb 2017 01:38:31 -0800 (PST) Received: by mail-wm0-x230.google.com with SMTP id r141so6491370wmg.1 for ; Wed, 22 Feb 2017 01:38:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZUw2/P7GBxsGNHcylEHCoxJ0hXc3n8xyehM+TZlTXCM=; b=WGalF2qu4mWagZSXt84lGwk6wKv6mYotUo+ViKm1DOXdXP2CcSaykog+C6sX7Ww8i/ O6PSwZUXbdbyBWLFrlfOcCRBMP2BRNFttJVBWQqobdyj1Ratv+MuYZxPkC53nX21+FJE KGgXuVnQpKIHAtaf1/sMCEMlVqDQu41AGfuD4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZUw2/P7GBxsGNHcylEHCoxJ0hXc3n8xyehM+TZlTXCM=; b=SR1TwgLkT+F4SERWU3J1IujJAlQ38tTEpTUaBw2lzpXWVcdUeK0OSYNGVe5OZyzeP5 raFiGu8T2gRYfgSHddpCWOAWcYPok93IRi3j4PILweWECJxntDJkVmCS+TRmekEJFVy7 bAkOKFRh2s2DjUJbSOh7bDuFIcfCuubrskSfbpE3+5mbE0oMvYCK+29Rh99K+IbtGymS qTB4Ky5egn7EQZe31XAt+bp59I7rUEeoEOJH/IrgNQSWVE3cESvK63y0HQx8M50FK2Sj xNT91V+nm787AasjWl2hdt9QSMgj6CepdD/DUj12VCTFtEyyAuUdIn/Fp/M40KedYZfO vYfA== X-Gm-Message-State: AMke39konextWjDuWSQxMO4QD3TSdJ8NeLUcmCGuuDgvCuwbUhoYvI+nD41AQ8R7s5OHIwi0 X-Received: by 10.28.61.136 with SMTP id k130mr1481020wma.128.1487756310057; Wed, 22 Feb 2017 01:38:30 -0800 (PST) Received: from localhost.localdomain ([160.163.32.105]) by smtp.gmail.com with ESMTPSA id c36sm976544wrc.49.2017.02.22.01.38.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Feb 2017 01:38:29 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Cc: heyi.guo@linaro.org, Ard Biesheuvel Date: Wed, 22 Feb 2017 09:38:18 +0000 Message-Id: <1487756301-15646-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487756301-15646-1-git-send-email-ard.biesheuvel@linaro.org> References: <1487756301-15646-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH 1/4] ArmPlatformPkg/ArmPlatformStackLib: use callee preserved registers X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Feb 2017 09:38:32 -0000 The entry code in ArmPlatformStackSet () is a 1:1 transliteration of the ARM version, which uses the callee preserved registers r3 - r7 (*) to preserve the function arguments and the link register across a call to ArmPlatformIsPrimaryCore (). However, x4 - x7 are not callee preserved on AARCH64, and so we should use registers >= x18 instead. While we're at it, drop an unnecessary preserve of the link register, and simplify/deobfuscate the calculation of the secondary stack position. (*) On ARM, r3 is not callee preserved either, but this should be addressed in a separate patch. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/Library/ArmPlatformStackLib/AArch64/ArmPlatformStackLib.S | 43 +++++++++----------- 1 file changed, 19 insertions(+), 24 deletions(-) diff --git a/ArmPlatformPkg/Library/ArmPlatformStackLib/AArch64/ArmPlatformStackLib.S b/ArmPlatformPkg/Library/ArmPlatformStackLib/AArch64/ArmPlatformStackLib.S index 65d7d6c6d686..e219d53cb71d 100644 --- a/ArmPlatformPkg/Library/ArmPlatformStackLib/AArch64/ArmPlatformStackLib.S +++ b/ArmPlatformPkg/Library/ArmPlatformStackLib/AArch64/ArmPlatformStackLib.S @@ -22,13 +22,13 @@ // ); ASM_FUNC(ArmPlatformStackSet) // Save parameters - mov x6, x3 - mov x5, x2 - mov x4, x1 - mov x3, x0 + mov x26, x3 + mov x25, x2 + mov x24, x1 + mov x23, x0 // Save the Link register - mov x7, x30 + mov x27, x30 // Identify Stack mov x0, x1 @@ -36,13 +36,13 @@ ASM_FUNC(ArmPlatformStackSet) cmp x0, #1 // Restore parameters - mov x0, x3 - mov x1, x4 - mov x2, x5 - mov x3, x6 + mov x0, x23 + mov x1, x24 + mov x2, x25 + mov x3, x26 // Restore the Link register - mov x30, x7 + mov x30, x27 b.ne 0f @@ -57,10 +57,7 @@ ASM_FUNC(ArmPlatformStackSet) // IN UINTN SecondaryStackSize // ); ASM_FUNC(ArmPlatformStackSetPrimary) - // Save the Link register - mov x4, x30 - - // Add stack of primary stack to StackBase + // Add size of primary stack to StackBase add x0, x0, x2 // Compute SecondaryCoresCount * SecondaryCoreStackSize @@ -70,7 +67,7 @@ ASM_FUNC(ArmPlatformStackSetPrimary) // Set Primary Stack ((StackBase + PrimaryStackSize) + (SecondaryCoresCount * SecondaryCoreStackSize)) add sp, x0, x3 - br x4 + ret //VOID //ArmPlatformStackSetSecondary ( @@ -81,30 +78,28 @@ ASM_FUNC(ArmPlatformStackSetPrimary) // ); ASM_FUNC(ArmPlatformStackSetSecondary) // Save the Link register - mov x4, x30 + mov x24, x30 mov sp, x0 // Get Core Position mov x0, x1 bl ASM_PFX(ArmPlatformGetCorePosition) - mov x5, x0 + mov x25, x0 // Get Primary Core Position bl ASM_PFX(ArmPlatformGetPrimaryCoreMpId) bl ASM_PFX(ArmPlatformGetCorePosition) // Get Secondary Core Position. We should get consecutive secondary stack number from 1...(CoreCount-1) - cmp x5, x0 - b.ls 1f + cmp x25, x0 + // Decrement the position if after the primary core - sub x5, x5, #1 -1: - add x5, x5, #1 + cinc x25, x25, ls // Compute top of the secondary stack - mul x3, x3, x5 + mul x3, x3, x25 // Set stack add sp, sp, x3 - br x4 + ret x24 -- 2.7.4