From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22f.google.com (mail-wr0-x22f.google.com [IPv6:2a00:1450:400c:c0c::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E61D98221B for ; Wed, 22 Feb 2017 01:38:35 -0800 (PST) Received: by mail-wr0-x22f.google.com with SMTP id z61so4141648wrc.1 for ; Wed, 22 Feb 2017 01:38:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VovwjWH0Hl3ZnSMI3jQVFpr5wy9FuPNZiVU283Mc/7I=; b=aBQeYolgRhV13mMjOYXYCMbUmEx+UBOaQiNS3bgRl2KLbLVEVLppRQYeoaX9MMIdVE LwjuU9A1qLYNtHMJnkJVBlm9og6OpbsXT9h86n97XCC+CvIB1w2MoQcIUGEXsd+nkG/P kYGEzvG1nUkUtb2kolX6owroJg8ABiMINbnjg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VovwjWH0Hl3ZnSMI3jQVFpr5wy9FuPNZiVU283Mc/7I=; b=MQffrYC25O7ysbUqcgHRbLZO4CWlbIEQvkTwljeMJ+yUT6xDSnbmdiHpQtZqf7xUzn c7/fX6FRuY/ErVMEAOdz43VOYxKbVYUuC6C1Sfzuel7TLlzNDozmy0tkvcZyOnFyQkTJ mdVbukDpypZZ1dmCziwACgnDpf3CRicWS/I35mwVy7hY34wMnCS5TQoZdYAt/QawFMvc cdfIYdeJXZrO3OuaMSBWOZSvtJRUsSp5imsSJswNysUDQu6fN9DtZwCez6ianMnXHWvM PoedM1Os7VPqSZJCnxXmZtJLeZp/RFHgqrkM+fXbsavnpABQIcabVxvYHhePot0+u/ev 6M7g== X-Gm-Message-State: AMke39nf7zCEBZk1jUHPZoJvXIdoF8mCm3JcR0lMaH+3SDw0+XMGSEozKrmJeG48X5fqjmih X-Received: by 10.223.131.193 with SMTP id 59mr22373863wre.186.1487756314465; Wed, 22 Feb 2017 01:38:34 -0800 (PST) Received: from localhost.localdomain ([160.163.32.105]) by smtp.gmail.com with ESMTPSA id c36sm976544wrc.49.2017.02.22.01.38.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Feb 2017 01:38:33 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Cc: heyi.guo@linaro.org, Ard Biesheuvel Date: Wed, 22 Feb 2017 09:38:20 +0000 Message-Id: <1487756301-15646-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487756301-15646-1-git-send-email-ard.biesheuvel@linaro.org> References: <1487756301-15646-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH 3/4] ArmPkg/ArmLib: AARCH64: allow the stack aligment (SA) bit to be managed X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Feb 2017 09:38:36 -0000 In preparation of enabling stack alignment checking, which is mandated by the UEFI spec for AARCH64, add the code to manage this bit to ArmLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Include/Chipset/AArch64.h | 12 +++++++ ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 34 ++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h index 9aecb1df81e0..cebfc5da426a 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -194,6 +194,18 @@ ArmEnableAlignmentCheck ( VOID EFIAPI +ArmDisableStackAlignmentCheck ( + VOID + ); + +VOID +EFIAPI +ArmEnableStackAlignmentCheck ( + VOID + ); + +VOID +EFIAPI ArmDisableAllExceptions ( VOID ); diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S index c35c05fdf681..e53b5fdc5986 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S @@ -20,6 +20,7 @@ .set CTRL_M_BIT, (1 << 0) .set CTRL_A_BIT, (1 << 1) .set CTRL_C_BIT, (1 << 2) +.set CTRL_SA_BIT, (1 << 3) .set CTRL_I_BIT, (1 << 12) .set CTRL_V_BIT, (1 << 12) .set CPACR_VFP_BITS, (3 << 20) @@ -259,6 +260,39 @@ ASM_FUNC(ArmDisableAlignmentCheck) isb ret +ASM_FUNC(ArmEnableStackAlignmentCheck) + EL1_OR_EL2(x1) +1: mrs x0, sctlr_el1 // Get control register EL1 + b 3f +2: mrs x0, sctlr_el2 // Get control register EL2 +3: orr x0, x0, #CTRL_SA_BIT // Set SA (stack alignment check) bit + EL1_OR_EL2(x1) +1: msr sctlr_el1, x0 // Write back control register + b 3f +2: msr sctlr_el2, x0 // Write back control register +3: dsb sy + isb + ret + + +ASM_FUNC(ArmDisableStackAlignmentCheck) + EL1_OR_EL2_OR_EL3(x1) +1: mrs x0, sctlr_el1 // Get control register EL1 + b 4f +2: mrs x0, sctlr_el2 // Get control register EL2 + b 4f +3: mrs x0, sctlr_el3 // Get control register EL3 +4: bic x0, x0, #CTRL_SA_BIT // Clear SA (stack alignment check) bit + EL1_OR_EL2_OR_EL3(x1) +1: msr sctlr_el1, x0 // Write back control register + b 4f +2: msr sctlr_el2, x0 // Write back control register + b 4f +3: msr sctlr_el3, x0 // Write back control register +4: dsb sy + isb + ret + // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now ASM_FUNC(ArmEnableBranchPrediction) -- 2.7.4