From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22f.google.com (mail-wr0-x22f.google.com [IPv6:2a00:1450:400c:c0c::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 39DA28224A for ; Wed, 22 Feb 2017 10:25:17 -0800 (PST) Received: by mail-wr0-x22f.google.com with SMTP id 97so8011564wrb.0 for ; Wed, 22 Feb 2017 10:25:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iedE+i6gHuMm+L5i3+BKqJiqQgPaoaiplSFJX26Gx8M=; b=OxrSnZJx9Kjhno23WrJk//of6zROUP8bcyX/dJ4TWyqoi8alOIH/zsqtQpGPHEucKU vA/+B3Q/Pv/jI5tScdC52Aws850cLS/Wq1SEQiqqrp8TD5yJDMI5yMaZzqRY/Oll3rTC J0ldccOEFQgPu9Js5kzL55jPljUVGMbR8d/x0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iedE+i6gHuMm+L5i3+BKqJiqQgPaoaiplSFJX26Gx8M=; b=Yj20LmctpgQDtAWmsCP8R2m5rnUeLyGkQulqi1bA+jXUX+tlJ2XQKk+WZrCD1FoIgT kajGqxQMcUejY/UeSWGmSJl5L2V2AWUSdwChxCEEiGSZ3zLn9lrIBdcq+QAF/orYl76h Y0Bh1Y2e1PvkwpsJvuEXc8WBD0g2BPqWcWIQA4SbJkPhg808Y0Yz8SBJb61fTKm5pLN5 V21R21UDNplbxWGVaxw6BKYds0hl0x0cBrZJhSJIKaJ7vudM1ywigJUvc5PNBvUic2/N rZcc7Y/hnFtuB/bcrrCXFX3/hgWf1YcI+4M97IMzbw6lciPFqAQegIWodkdEs5wLHjTi A21w== X-Gm-Message-State: AMke39n7rimzVO/46MzkjibtfSdSqA8Kjj46p9A+ynBAtx+rsG1wCq4tQB1hjxJMAZxPuj2+ X-Received: by 10.223.145.193 with SMTP id 59mr4589392wri.82.1487787915792; Wed, 22 Feb 2017 10:25:15 -0800 (PST) Received: from localhost.localdomain ([196.80.204.181]) by smtp.gmail.com with ESMTPSA id e73sm3504667wmi.32.2017.02.22.10.25.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Feb 2017 10:25:15 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, afish@apple.com, leif.lindholm@linaro.org, michael.d.kinney@intel.com, liming.gao@intel.com, jiewen.yao@intel.com Cc: lersek@redhat.com, feng.tian@intel.com, star.zeng@intel.com, Ard Biesheuvel Date: Wed, 22 Feb 2017 18:24:58 +0000 Message-Id: <1487787898-5222-5-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487787898-5222-1-git-send-email-ard.biesheuvel@linaro.org> References: <1487787898-5222-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [RFC PATCH 4/4] ArmPkg/CpuDxe: remap all data regions non-executable X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Feb 2017 18:25:17 -0000 When installing the CPU arch protocol, iterate over the UEFI memory map and remove the executable permissions from each encountered non-code region. Those will be re-added later selectively, to the extent required according to the image protection policy and section alignment. With a strict image protection policy in place, this all but eliminates any regions that are mapped both writable and executable, which is an significant improvement in security. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/CpuDxe.c | 76 ++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c index 7d328d096b1e..dd3bf44a00b3 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c @@ -15,6 +15,9 @@ #include "CpuDxe.h" +#include +#include + #include @@ -237,6 +240,74 @@ InitializeDma ( CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule (); } +STATIC +VOID +RemapAllDataRegionsNonExec ( + VOID + ) +{ + UINTN MemoryMapSize; + UINTN MapKey; + UINTN DescriptorSize; + UINT32 DescriptorVersion; + EFI_MEMORY_DESCRIPTOR *MemoryMap; + EFI_MEMORY_DESCRIPTOR *MemoryMapEntry; + EFI_MEMORY_DESCRIPTOR *MemoryMapEnd; + EFI_STATUS Status; + + // + // Iterate over the memory map, and remove execute permissions from all + // memory regions that are not BootServiceCode or RuntimeServicesCode. + // + + // + // Get the EFI memory map. + // + MemoryMapSize = 0; + MemoryMap = NULL; + + Status = gBS->GetMemoryMap ( + &MemoryMapSize, + MemoryMap, + &MapKey, + &DescriptorSize, + &DescriptorVersion + ); + ASSERT (Status == EFI_BUFFER_TOO_SMALL); + do { + MemoryMap = (EFI_MEMORY_DESCRIPTOR *) AllocatePool (MemoryMapSize); + ASSERT (MemoryMap != NULL); + Status = gBS->GetMemoryMap ( + &MemoryMapSize, + MemoryMap, + &MapKey, + &DescriptorSize, + &DescriptorVersion + ); + if (EFI_ERROR (Status)) { + FreePool (MemoryMap); + } + } while (Status == EFI_BUFFER_TOO_SMALL); + ASSERT_EFI_ERROR (Status); + + MemoryMapEntry = MemoryMap; + MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *) ((UINT8 *) MemoryMap + MemoryMapSize); + while ((UINTN) MemoryMapEntry < (UINTN) MemoryMapEnd) { + if ((MemoryMapEntry->Type != EfiBootServicesCode) && + (MemoryMapEntry->Type != EfiRuntimeServicesCode)) { + + CpuSetMemoryAttributes (&mCpu, MemoryMapEntry->PhysicalStart, + EFI_PAGES_TO_SIZE(MemoryMapEntry->NumberOfPages), EFI_MEMORY_XP); + DEBUG((DEBUG_ERROR, "%a: removing exec permissions from 0x%lx - 0x%lx (Type == 0x%x)\n", + __FUNCTION__, MemoryMapEntry->PhysicalStart, + MemoryMapEntry->PhysicalStart + EFI_PAGES_TO_SIZE(MemoryMapEntry->NumberOfPages) - 1, + MemoryMapEntry->Type)); + } + MemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); + } + FreePool (MemoryMap); +} + EFI_STATUS CpuDxeInitialize ( IN EFI_HANDLE ImageHandle, @@ -264,6 +335,11 @@ CpuDxeInitialize ( // SyncCacheConfig (&mCpu); + // + // Remap all conventional memory as non-executable. + // + RemapAllDataRegionsNonExec (); + // If the platform is a MPCore system then install the Configuration Table describing the // secondary core states if (ArmIsMpCore()) { -- 2.7.4