From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x234.google.com (mail-wm0-x234.google.com [IPv6:2a00:1450:400c:c09::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 07D5881D77 for ; Fri, 24 Feb 2017 07:05:10 -0800 (PST) Received: by mail-wm0-x234.google.com with SMTP id v77so16557622wmv.1 for ; Fri, 24 Feb 2017 07:05:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=igZoV7AQ3PUnmkt4nmhLtMJaGR+e0YyS4h7zrFfbUDQ=; b=X+eQJtOyIN7p1mnG2akul5Axj6XT7QBtg5QJV8Nj9zMEYyIwgNrohVM69DizvIbWFQ YV/Eft4Z/SmgRZrPpmZ9Nt0F2i3dGq9mX8gHFS70p11fVKb4EtNcHLDC6V21nviX/1B4 y40rqMFVDwhuYRnvbbZcMRLOYFxgzNXNdGC2k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=igZoV7AQ3PUnmkt4nmhLtMJaGR+e0YyS4h7zrFfbUDQ=; b=cX0NjUfLBpm390TFrY5+jfX7gxc9IPAPikh+N9ZFquZBBeJ21cbkkYumzU8wri5fhU PBXwFh+ZTbLeggIahG9lYU9ATVaJcaUvCyTmMGzxNafOtn4q+coZO8sj2IO9JjXd2i5r jjgMg54YYoGvx7Vf7AMc48Q07om650XaDoioIAl/ZHidVU6CPYT5h+eev+1Nw8Am5sB1 kPzOkGi/8M36G6pkIurlOWtQU7EPxGyJJcQUBEkHeTzkaqpaxITB0iOuEGPvai23NYWh /MtP4QPB8kstPNV0mAKzyRJHxboKzkAAHd5PYgerzw72XXwwOoZ0dAhnXmIBFzjRHMWZ w5LA== X-Gm-Message-State: AMke39lU8QPSSXg5gzpv7ZNuvmd8MdXTjLoxptyWo7TdVzPzyqJVxD7dR0UZN3pMpjd17Sli X-Received: by 10.28.165.70 with SMTP id o67mr768383wme.123.1487948708590; Fri, 24 Feb 2017 07:05:08 -0800 (PST) Received: from localhost.localdomain ([105.149.201.216]) by smtp.gmail.com with ESMTPSA id w207sm2687048wmw.1.2017.02.24.07.05.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Feb 2017 07:05:07 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, afish@apple.com, leif.lindholm@linaro.org, michael.d.kinney@intel.com, liming.gao@intel.com, jiewen.yao@intel.com Cc: lersek@redhat.com, feng.tian@intel.com, star.zeng@intel.com, Ard Biesheuvel Date: Fri, 24 Feb 2017 15:04:55 +0000 Message-Id: <1487948699-3179-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487948699-3179-1-git-send-email-ard.biesheuvel@linaro.org> References: <1487948699-3179-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH v2 1/5] ArmPkg/CpuDxe: ignore attribute changes during SyncCacheConfig() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Feb 2017 15:05:10 -0000 To prevent the initial MMU->GCD memory space map synchronization from stripping permissions attributes [which we cannot use in the GCD memory space map, unfortunately], implement the same approach as x86, and ignore SetMemoryAttributes() calls during the time SyncCacheConfig() is in progress. This is a horrible hack, but is currently the only way we can implement strict permissions on arbitrary memory regions [as opposed to PE/COFF text/data sections only] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/CpuDxe/CpuDxe.c | 3 +++ ArmPkg/Drivers/CpuDxe/CpuDxe.h | 1 + ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 4 ++++ 3 files changed, 8 insertions(+) diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c index 5aa5b874144a..1955d1dece03 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c @@ -17,6 +17,7 @@ #include +BOOLEAN gIsFlushingGCD; /** This function flushes the range of addresses from Start to Start+Length @@ -261,7 +262,9 @@ CpuDxeInitialize ( // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go // after the protocol is installed // + gIsFlushingGCD = TRUE; SyncCacheConfig (&mCpu); + gIsFlushingGCD = FALSE; // If the platform is a MPCore system then install the Configuration Table describing the // secondary core states diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h index a00fc3064362..085e4cab2921 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h @@ -37,6 +37,7 @@ #include #include +extern BOOLEAN gIsFlushingGCD; /** This function registers and enables the handler specified by InterruptHandler for a processor diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c index ebe593d1c325..6dfec7e55888 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c @@ -188,6 +188,10 @@ CpuSetMemoryAttributes ( UINTN RegionLength; UINTN RegionArmAttributes; + if (gIsFlushingGCD) { + return EFI_SUCCESS; + } + if ((BaseAddress & (SIZE_4KB - 1)) != 0) { // Minimum granularity is SIZE_4KB (4KB on ARM) DEBUG ((EFI_D_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum ganularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes)); -- 2.7.4