From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x231.google.com (mail-wm0-x231.google.com [IPv6:2a00:1450:400c:c09::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E958B82126 for ; Sun, 26 Feb 2017 10:30:35 -0800 (PST) Received: by mail-wm0-x231.google.com with SMTP id v186so47150662wmd.0 for ; Sun, 26 Feb 2017 10:30:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZLo/mBL996UMzCYelE+fogyf+t/RimtJ0Aw/ZCfm+o4=; b=EuKQxoubJbBH6y8B/4O9L+6rTjjUb9zxgx9I1g4QiIuonUgGoB+zsIyVBrn6iDf7ik mlG3wgQF2fQzxLlnfshnEv73JM3FxRCch/nsj4Sbcq53PBAOyNRl2I3Ky2OEp7qZ+KFM WinblUGz69sA7EIFtXEjD+IestKvYlgSiNkI8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZLo/mBL996UMzCYelE+fogyf+t/RimtJ0Aw/ZCfm+o4=; b=JE+TwiuJ7ViLdBkuYiv14UqM4Qh6UL73W/LC13DCKLnVacvrXVZrYWjA3Co+mKMOHh V1SmQgYhpi+e3LuX/VWnO3xsWBR61FdMTs8v0aFk+l0Ft8I4Xo0ZxY2+dwFyyPD4BTjG kBf4VJjFmpRb/kgY7ONayXZjSrBEVOER4W23k75IDw9fqVJVPx/hdGHi+TtfaaWy991j 3hRZplvJ0n79DS8mp3IkhAMd4gE+NzY/+rbMv0b8+lJAWIDfz0LT8h0uUXfVYfVH6KLu 6SiT5CyBVWgv13HAxetw5LlOkLgjuKUmytFDTkXF1ewOCPADV8eMWKNzh4OlD8kj4EdN ASBQ== X-Gm-Message-State: AMke39lK/TY4DLPm9zYh4RHyzqIUg9v1won9Ipn4qiOBtXr+xh1ONDO9FbEBh9+WoGviytku X-Received: by 10.28.91.1 with SMTP id p1mr10267909wmb.102.1488133834500; Sun, 26 Feb 2017 10:30:34 -0800 (PST) Received: from localhost.localdomain ([105.149.201.216]) by smtp.gmail.com with ESMTPSA id s103sm4499474wrc.6.2017.02.26.10.30.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 26 Feb 2017 10:30:33 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, jiewen.yao@intel.com, leif.lindholm@linaro.org Cc: afish@apple.com, michael.d.kinney@intel.com, liming.gao@Intel.com, lersek@redhat.com, feng.tian@intel.com, star.zeng@intel.com, Ard Biesheuvel Date: Sun, 26 Feb 2017 18:30:00 +0000 Message-Id: <1488133805-4773-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488133805-4773-1-git-send-email-ard.biesheuvel@linaro.org> References: <1488133805-4773-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH v3 1/6] ArmPkg/CpuDxe: ignore attribute changes during SyncCacheConfig() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 26 Feb 2017 18:30:36 -0000 To prevent the initial MMU->GCD memory space map synchronization from stripping permissions attributes [which we cannot use in the GCD memory space map, unfortunately], implement the same approach as x86, and ignore SetMemoryAttributes() calls during the time SyncCacheConfig() is in progress. This is a horrible hack, but is currently the only way we can implement strict permissions on arbitrary memory regions [as opposed to PE/COFF text/data sections only] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Jiewen Yao --- ArmPkg/Drivers/CpuDxe/CpuDxe.c | 3 +++ ArmPkg/Drivers/CpuDxe/CpuDxe.h | 1 + ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 4 ++++ 3 files changed, 8 insertions(+) diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c index 5aa5b874144a..1955d1dece03 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c @@ -17,6 +17,7 @@ #include +BOOLEAN gIsFlushingGCD; /** This function flushes the range of addresses from Start to Start+Length @@ -261,7 +262,9 @@ CpuDxeInitialize ( // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go // after the protocol is installed // + gIsFlushingGCD = TRUE; SyncCacheConfig (&mCpu); + gIsFlushingGCD = FALSE; // If the platform is a MPCore system then install the Configuration Table describing the // secondary core states diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h index a00fc3064362..085e4cab2921 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h @@ -37,6 +37,7 @@ #include #include +extern BOOLEAN gIsFlushingGCD; /** This function registers and enables the handler specified by InterruptHandler for a processor diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c index ebe593d1c325..6dfec7e55888 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c @@ -188,6 +188,10 @@ CpuSetMemoryAttributes ( UINTN RegionLength; UINTN RegionArmAttributes; + if (gIsFlushingGCD) { + return EFI_SUCCESS; + } + if ((BaseAddress & (SIZE_4KB - 1)) != 0) { // Minimum granularity is SIZE_4KB (4KB on ARM) DEBUG ((EFI_D_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum ganularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes)); -- 2.7.4