From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x234.google.com (mail-wr0-x234.google.com [IPv6:2a00:1450:400c:c0c::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C8CD781F68 for ; Mon, 27 Feb 2017 06:38:22 -0800 (PST) Received: by mail-wr0-x234.google.com with SMTP id l37so9543975wrc.1 for ; Mon, 27 Feb 2017 06:38:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZLo/mBL996UMzCYelE+fogyf+t/RimtJ0Aw/ZCfm+o4=; b=SB/IufSdv3f0XgzjbgTYm6NqJQFq2GWZvPZlpTIBnB4SlH55Ezqx3qnAmnVQZgTZwS ln4iHtVtyAyr36Ax/n05jZE130YjM11cpdJ+JWfmKzbZkR98dJNKhCvTVlGMBRykTdro cjUHeNKF9UDY8lbSKbM9E2iO0OHobhCsZo5yU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZLo/mBL996UMzCYelE+fogyf+t/RimtJ0Aw/ZCfm+o4=; b=koOubkF0z8hcWhkanGjk6UgAaSVoMuEIIRdCwF04FtYXloF9RByvTQjuVddwu6o7iq 2VMOXLKNOrv1xtN2jhC3rdjillahHW1Ms6UeYTR5VhxOReUXumsoqDHVmfazKGl3upxD IWkRvjBcP/KA+k6L4KzIwoziGjjdH+zKuF8EUBBkSqYTwyOzN2GEwcJJondF8gg1YNZT hKmnVz3d2LkABrx+4ZFE+UpoLtDra7314+pwD9++tSt0Avw4880OfYTEE/508jBaBcVC Br1q9kxJWF6F79N4J56PsIFQe6c9nX3Vo64yUUcraaL/0GWKl0yO5g/HiwDX0GVEbPXA 9xiA== X-Gm-Message-State: AMke39nAGT0eN89B6XA4tFCh7b/bNqQ1RzzY98O1qtqgsh1kNjBRW+7XLb3LgsENzw7AoTsV X-Received: by 10.223.130.101 with SMTP id 92mr6061487wrb.192.1488206301349; Mon, 27 Feb 2017 06:38:21 -0800 (PST) Received: from localhost.localdomain ([105.149.201.216]) by smtp.gmail.com with ESMTPSA id z134sm14475167wmc.20.2017.02.27.06.38.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 27 Feb 2017 06:38:20 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, afish@apple.com, leif.lindholm@linaro.org, michael.d.kinney@intel.com, liming.gao@intel.com, jiewen.yao@intel.com Cc: lersek@redhat.com, feng.tian@intel.com, star.zeng@intel.com, Ard Biesheuvel Date: Mon, 27 Feb 2017 14:38:05 +0000 Message-Id: <1488206291-25768-2-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488206291-25768-1-git-send-email-ard.biesheuvel@linaro.org> References: <1488206291-25768-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [PATCH v4 1/7] ArmPkg/CpuDxe: ignore attribute changes during SyncCacheConfig() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Feb 2017 14:38:23 -0000 To prevent the initial MMU->GCD memory space map synchronization from stripping permissions attributes [which we cannot use in the GCD memory space map, unfortunately], implement the same approach as x86, and ignore SetMemoryAttributes() calls during the time SyncCacheConfig() is in progress. This is a horrible hack, but is currently the only way we can implement strict permissions on arbitrary memory regions [as opposed to PE/COFF text/data sections only] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Jiewen Yao --- ArmPkg/Drivers/CpuDxe/CpuDxe.c | 3 +++ ArmPkg/Drivers/CpuDxe/CpuDxe.h | 1 + ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 4 ++++ 3 files changed, 8 insertions(+) diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c index 5aa5b874144a..1955d1dece03 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c @@ -17,6 +17,7 @@ #include +BOOLEAN gIsFlushingGCD; /** This function flushes the range of addresses from Start to Start+Length @@ -261,7 +262,9 @@ CpuDxeInitialize ( // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go // after the protocol is installed // + gIsFlushingGCD = TRUE; SyncCacheConfig (&mCpu); + gIsFlushingGCD = FALSE; // If the platform is a MPCore system then install the Configuration Table describing the // secondary core states diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h index a00fc3064362..085e4cab2921 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h @@ -37,6 +37,7 @@ #include #include +extern BOOLEAN gIsFlushingGCD; /** This function registers and enables the handler specified by InterruptHandler for a processor diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c index ebe593d1c325..6dfec7e55888 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c @@ -188,6 +188,10 @@ CpuSetMemoryAttributes ( UINTN RegionLength; UINTN RegionArmAttributes; + if (gIsFlushingGCD) { + return EFI_SUCCESS; + } + if ((BaseAddress & (SIZE_4KB - 1)) != 0) { // Minimum granularity is SIZE_4KB (4KB on ARM) DEBUG ((EFI_D_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum ganularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes)); -- 2.7.4